| 02428682 | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
Rename the Clock Conditioning Circuit (CCC) reference clock to match the fixed clock bindings naming recommendation.
Update
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
Rename the Clock Conditioning Circuit (CCC) reference clock to match the fixed clock bindings naming recommendation.
Update the reserved memory regions in the Icicle Kit common dtsi to use lowercase hex and drop the redundant status properties from the memory regions, as they are not required.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 2775e87c | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: add icicle kit with production device
With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sampl
riscv: dts: microchip: add icicle kit with production device
With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sample (-es) variant. Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata.
Add a new device tree (mpfs-icicle-kit-prod.dts) for the production board which includes the icicle kit common dtsi and enable the system controller SPI flash, which is only accessible on production silicon.
Remove redundant board compatible from fabric dtsi and update board compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP cluster communication.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| f401a8ba | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: add common board dtsi for icicle kit variants
In preparation for supporting the Icicle Kit with production silicon, add a common board dtsi for the icicle kit with hardware sh
riscv: dts: microchip: add common board dtsi for icicle kit variants
In preparation for supporting the Icicle Kit with production silicon, add a common board dtsi for the icicle kit with hardware shared by both the engineering sample and production versions.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 5669bb5a | 08-Dec-2023 |
Shravan Chippa <shravan.chippa@microchip.com> |
riscv: dts: microchip: add specific compatible for mpfs pdma
Add specific compatible for PolarFire SoC for The SiFive PDMA driver
Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-b
riscv: dts: microchip: add specific compatible for mpfs pdma
Add specific compatible for PolarFire SoC for The SiFive PDMA driver
Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| e77da13b | 07-Mar-2023 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix the mpfs' mailbox regs
The mailbox on PolarFire SoC should really have three reg properties, not two. Without splitting into three sections, the system controller's QSPI c
riscv: dts: microchip: fix the mpfs' mailbox regs
The mailbox on PolarFire SoC should really have three reg properties, not two. Without splitting into three sections, the system controller's QSPI cannot be accessed as it sits inside the current first range. The driver & binding have been adapted to account for both two & three ranges, so fix the dts too.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d9c36d01 | 25-Jan-2023 |
Conor Dooley <conor.dooley@microchip.com> |
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"
As it says on the tin, add a DT for this board. It's been sitting on my desk for a while, so may as well have it upstream...
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"
As it says on the tin, add a DT for this board. It's been sitting on my desk for a while, so may as well have it upstream...
The DT is only partially complete, as it needs the fabric content added. Unfortunately, I don't have a reference design in RTL or SmartDesign for it and therefore don't know what that fabric content is.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| f4e700fd | 15-Nov-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and M100PFSEVP are connected via one, not two Fabric Interface Controllers (FIC). The
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and M100PFSEVP are connected via one, not two Fabric Interface Controllers (FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from the dt node.
The same clock provides both, so this is harmless but inaccurate.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| bdd28ab3 | 07-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix the icicle's #pwm-cells
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support
riscv: dts: microchip: fix the icicle's #pwm-cells
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support inverted operation, so update the entry to correctly report its capabilities.
Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit") Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d6105a8b | 25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix memory node unit address for icicle
Evidently I forgot to update the unit address for the 38-bit cached memory node when I changed the address in the reg property.. Update
riscv: dts: microchip: fix memory node unit address for icicle
Evidently I forgot to update the unit address for the 38-bit cached memory node when I changed the address in the reg property.. Update it to match.
Fixes: 6c1193301791 ("riscv: dts: microchip: update memory configuration for v2022.10") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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