| 5669bb5a | 08-Dec-2023 |
Shravan Chippa <shravan.chippa@microchip.com> |
riscv: dts: microchip: add specific compatible for mpfs pdma
Add specific compatible for PolarFire SoC for The SiFive PDMA driver
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-b
riscv: dts: microchip: add specific compatible for mpfs pdma
Add specific compatible for PolarFire SoC for The SiFive PDMA driver
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| e77da13b | 07-Mar-2023 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix the mpfs' mailbox regs
The mailbox on PolarFire SoC should really have three reg properties,
not two. Without splitting into three sections, the system controller's
QSPI c
riscv: dts: microchip: fix the mpfs' mailbox regs
The mailbox on PolarFire SoC should really have three reg properties,
not two. Without splitting into three sections, the system controller's
QSPI cannot be accessed as it sits inside the current first range. The
driver & binding have been adapted to account for both two & three
ranges, so fix the dts too.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d9c36d01 | 25-Jan-2023 |
Conor Dooley <conor.dooley@microchip.com> |
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"
As it says on the tin, add a DT for this board. It's been sitting on my
desk for a while, so may as well have it upstream...
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"
As it says on the tin, add a DT for this board. It's been sitting on my
desk for a while, so may as well have it upstream...
The DT is only partially complete, as it needs the fabric content added.
Unfortunately, I don't have a reference design in RTL or SmartDesign
for it and therefore don't know what that fabric content is.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| f4e700fd | 15-Nov-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and
M100PFSEVP are connected via one, not two Fabric Interface Controllers
(FIC). The
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and
M100PFSEVP are connected via one, not two Fabric Interface Controllers
(FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from
the dt node.
The same clock provides both, so this is harmless but inaccurate.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| bdd28ab3 | 07-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix the icicle's #pwm-cells
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
blindly overridden by the (out of tree) driver anyway. The core can
support
riscv: dts: microchip: fix the icicle's #pwm-cells
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
blindly overridden by the (out of tree) driver anyway. The core can
support inverted operation, so update the entry to correctly report its
capabilities.
Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d6105a8b | 25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix memory node unit address for icicle
Evidently I forgot to update the unit address for the 38-bit cached
memory node when I changed the address in the reg property..
Update
riscv: dts: microchip: fix memory node unit address for icicle
Evidently I forgot to update the unit address for the 38-bit cached
memory node when I changed the address in the reg property..
Update it to match.
Fixes: 6c1193301791 ("riscv: dts: microchip: update memory configuration for v2022.10")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 0d814000 | 20-Oct-2022 |
Emil Renner Berthing <emil.renner.berthing@canonical.com> |
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
Add the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC Icicle
Kit device tree. The schematic doesn't specify any special function
for t
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
Add the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC Icicle
Kit device tree. The schematic doesn't specify any special function
for the LEDs, so they're added here without any default triggers and
named led1, led2, led3 and led4 just like in the schematic.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| c210b918 | 20-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix fabric i2c reg size
The size of the reg should've been changed when the address was changed,
but obviously I forgot to do so.
Fixes: ab291621a8b8 ("riscv: dts: microchip:
riscv: dts: microchip: fix fabric i2c reg size
The size of the reg should've been changed when the address was changed,
but obviously I forgot to do so.
Fixes: ab291621a8b8 ("riscv: dts: microchip: icicle: re-jig fabric peripheral addresses")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 6c119330 | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: update memory configuration for v2022.10
In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux
riscv: dts: microchip: update memory configuration for v2022.10
In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux.
A small 4M reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload.bin between
reboots of a specific context.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d4916664 | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: add a devicetree for aries' m100pfsevp
Add device trees for both configs used by the Aries Embedded
M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,
featuring:
- 2G
riscv: dts: microchip: add a devicetree for aries' m100pfsevp
Add device trees for both configs used by the Aries Embedded
M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,
featuring:
- 2GB DDR4 SDRAM dedicated to the HMS
- 512MB DDR4 SDRAM dedicated to the FPGA
- 32 MB SPI NOR Flash
- 4 GByte eMMC
and a carrier board with:
- 2x Gigabit Ethernet
- USB
- 2x UART
- 2x CAN
- TFT connector
- HSMC extension connector
- 3x PMOD extension connectors
- microSD-card slot
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod
Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf
Co-developed-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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