riscv: dts: microchip: update pcie reg properties to new formatThe existing PolarFire SoC devicetrees all use root port instance 1,update the reg properties in PCIe nodes to use the new format tha
riscv: dts: microchip: update pcie reg properties to new formatThe existing PolarFire SoC devicetrees all use root port instance 1,update the reg properties in PCIe nodes to use the new format thatspecifies the instance in use. Failing to do so would still work butproduces warnings:mpfs-icicle-kit.dtb: pcie@3000000000: reg: [[48, 0, 0, 134217728], [0, 1124073472, 0, 65536]] is too shortmpfs-icicle-kit.dtb: pcie@3000000000: reg-names: ['cfg', 'apb'] is too shortSigned-off-by: Conor Dooley <conor.dooley@microchip.com>---CC: Conor Dooley <conor@kernel.org>CC: Daire McNamara <daire.mcnamara@microchip.com>CC: valentina.fernandezalanis@microchip.comCC: Rob Herring <robh@kernel.org>CC: Krzysztof Kozlowski <krzk+dt@kernel.org>CC: linux-riscv@lists.infradead.orgCC: devicetree@vger.kernel.orgCC: linux-kernel@vger.kernel.org
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riscv: dts: microchip: add an initial devicetree for the BeagleV FireAdd an initial devicetree for the BeagleV Fire. This devicetree differsfrom that in the BeagleBoard BSP as it has a different m
riscv: dts: microchip: add an initial devicetree for the BeagleV FireAdd an initial devicetree for the BeagleV Fire. This devicetree differsfrom that in the BeagleBoard BSP as it has a different memoryconfiguration, however it will boot on the same FPGA images. PCI isdisabled for now, as the Linux PCI driver (and the binding) assumewhich root port instance is in use. This will need to be fixed beforePCI can be enabled.Link: https://www.beagleboard.org/boards/beaglev-fireCo-developed-by: Jamie Gibbons <jamie.gibbons@microchip.com>Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: add pac1934 power-monitor to icicleThe binding for this landed in v6.9, add the description. In theoff-chance that there were people carrying local patches for this basedon
riscv: dts: microchip: add pac1934 power-monitor to icicleThe binding for this landed in v6.9, add the description. In theoff-chance that there were people carrying local patches for this basedon the driver shipped on the Microchip website (or vendor kernel) boththe binding and sysfs filenames changed during upstreaming.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socPull more ARM SoC updates from Arnd Bergmann: "These are changes that for some reason ended up not making it into t
Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socPull more ARM SoC updates from Arnd Bergmann: "These are changes that for some reason ended up not making it into the first four branches but that should still make it into 6.9: - A rework of the omap clock support that touches both drivers and device tree files - The reset controller branch changes that had a dependency on late bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the drivers branch - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree changes that got delayed and needed some extra time in linux-next for wider testing"* tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits) soc: fsl: dpio: fix kcalloc() argument order bus: ts-nbus: Improve error reporting bus: ts-nbus: Convert to atomic pwm API riscv: dts: starfive: jh7110: Add camera subsystem nodes ARM: bcm: stop selecing CONFIG_TICK_ONESHOT ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift clk: ti: Improve clksel clock bit parsing for reg property clk: ti: Handle possible address in the node name dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID reset: Instantiate reset GPIO controller for shared reset-gpios reset: gpio: Add GPIO-based reset controller cpufreq: do not open-code of_phandle_args_equal() of: Add of_phandle_args_equal() helper reset: simple: add support for Sophgo SG2042 dt-bindings: reset: sophgo: support SG2042 riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks ARM: brcmstb: Add debug UART entry for 74165 ...
riscv: dts: Move BUILTIN_DTB_SOURCE to common KconfigThe BUILTIN_DTB_SOURCE was only configured for K210 before. SinceSOC_BUILTIN_DTB_DECLARE was removed at commit d5805af9fe9f ("riscv: Fixbuilti
riscv: dts: Move BUILTIN_DTB_SOURCE to common KconfigThe BUILTIN_DTB_SOURCE was only configured for K210 before. SinceSOC_BUILTIN_DTB_DECLARE was removed at commit d5805af9fe9f ("riscv: Fixbuiltin DTB handling") from patch [1], the kernel cannot choose one of thedtbs from then on and always take the first one dtb to use. Then, anothercommit 0ddd7eaffa64 ("riscv: Fix BUILTIN_DTB for sifive and microchip soc")from patch [2] supports BUILTIN_DTB_SOURCE for other SoCs. However, thisfeature will only work if the Kconfig we use links the dtb we expected inthe first place as mentioned in the thread [3]. Thus, a configBUILTIN_DTB_SOURCE is needed for all SoCs to choose one dtb to use.For some considerations, this patch also removes default y if XIP_KERNELfor BUILTIN_DTB, as this requires setting a proper dtb to use on theBUILTIN_DTB_SOURCE, else the kernel with XIP but does not setBUILTIN_DTB_SOURCE or unselect BUILTIN_DTB will not boot.Also, this patch removes the default dtb string for k210 from Kconfig tonommu_k210_defconfig and nommu_k210_sdcard_defconfig to avoid complexKconfig settings for other SoCs in the future.[1] https://lore.kernel.org/linux-riscv/20201208073355.40828-5-damien.lemoal@wdc.com/[2] https://lore.kernel.org/linux-riscv/20210604120639.1447869-1-alex@ghiti.fr/[3] https://lore.kernel.org/linux-riscv/CAK7LNATt_56mO2Le4v4EnPnAfd3gC8S_Sm5-GCsfa=qXy=8Lrg@mail.gmail.com/Signed-off-by: Yangyu Chen <cyy@cyyself.name>Reviewed-by: Conor Dooley <conor.dooley@microchip.com>Acked-by: Palmer Dabbelt <palmer@rivosinc.com>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: add specific compatible for mpfs pdmaAdd specific compatible for PolarFire SoC for The SiFive PDMA driverReviewed-by: Conor Dooley <conor.dooley@microchip.com>Signed-off-b
riscv: dts: microchip: add specific compatible for mpfs pdmaAdd specific compatible for PolarFire SoC for The SiFive PDMA driverReviewed-by: Conor Dooley <conor.dooley@microchip.com>Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: add missing CAN bus clocksThe CAN controller on PolarFire SoC has an AHB peripheral clock _and_ aCAN bus clock. The bus clock was omitted when the binding was written,but i
riscv: dts: microchip: add missing CAN bus clocksThe CAN controller on PolarFire SoC has an AHB peripheral clock _and_ aCAN bus clock. The bus clock was omitted when the binding was written,but is required for operation. Make up for lost time and add to the DT.Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers")Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socPull SoC DT updates from Arnd Bergmann: "There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both the R
Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socPull SoC DT updates from Arnd Bergmann: "There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both the Rockchips rv1109 and Sopgho CV1812H are just minor variations of already supported chips. The other six new SoCs are all part of existing arm64 families, but are somewhat more interesting: - Samsung ExynosAutov920 is an automotive chip, and the first one we support based on the Cortex-A78AE core with lockstep mode. - Google gs101 (Tensor G1) is the chip used in a number of Pixel phones, and is grouped with Samsung Exynos here since it is based on the same SoC design, sharing most of its IP blocks with that series. - MediaTek MT8188 is a new chip used for mid-range tablets and Chromebooks, using two Cortex-A78 cores where the older MT8195 had four of them. - Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range phone SoC and the first supported chip based on Cortex-X4, Cortex-A720 and Cortex-A520. - Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest Laptop chip using the custom Oryon cores. - Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on Cortex-A76 and Cortex-A55 In terms of boards, we have - Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs. - Multiple Rockchips mobile gaming systems (Anbernic RG351V, Powkiddy RK2023, Powkiddy X55) along with the Sonoff iHost Smart Home Hub and a few Rockchips SBCs - Some ComXpress boards based on Marvell CN913x, which is the follow-up to Armada 7xxx/8xxx. - Six new industrial/embedded boards based on NXP i.MX8 and i.MX9 - Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer. - Toradex Verdin AM62 Mallow carrier for TI AM62 - Huashan Pi board based on the SophGo CV1812H RISC-V chip - Two boards based on Allwinner H616/H618 - A number of reference boards for various added SoCs from Qualcomm, Mediatek, Google, Samsung, NXP and Spreadtrum As usual, there are cleanups and warning fixes across all platforms as well as added features for several of them"* tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (857 commits) ARM: dts: usr8200: Fix phy registers arm64: dts: intel: minor whitespace cleanup around '=' arm64: dts: socfpga: agilex: drop redundant status arm64: dts: socfpga: agilex: add unit address to soc node arm64: dts: socfpga: agilex: move firmware out of soc node arm64: dts: socfpga: agilex: move FPGA region out of soc node arm64: dts: socfpga: agilex: align pin-controller name with bindings arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings arm64: dts: socfpga: stratix10: add unit address to soc node arm64: dts: socfpga: stratix10: move firmware out of soc node arm64: dts: socfpga: stratix10: move FPGA region out of soc node arm64: dts: socfpga: stratix10: align pincfg nodes with bindings arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size ARM: dts: socfpga: align NAND controller name with bindings ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size arm64: dts: rockchip: Fix led pinctrl of lubancat 1 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b ...
riscv: dts: microchip: add the mpfs' system controller qspi & associated flashThe system controller's flash can be accessed via an MSS-exposed QSPIcontroller sitting, which sits between the mailbo
riscv: dts: microchip: add the mpfs' system controller qspi & associated flashThe system controller's flash can be accessed via an MSS-exposed QSPIcontroller sitting, which sits between the mailbox's control & dataregisters. On Icicle, it has an MT25QL01GBBB8ESF connected to it.The system controller and MSS both have separate QSPI controllers, bothof which can access the flash, although the system controller takespriority.Unfortunately, on engineering sample silicon, such as that on Iciclekits, the MSS' QSPI controller cannot write to the flash due to a bug.As a workaround, a QSPI controller can be implemented in the FPGAfabric and the IO routing modified to connect it to the flash in placeof the "hard" controller in the MSS.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: move timebase-frequency to mpfs.dtsiThe timebase-frequency on PolarFire SoC is not set by an oscillator onthe board, but rather by an internal divider, so move the property
riscv: dts: microchip: move timebase-frequency to mpfs.dtsiThe timebase-frequency on PolarFire SoC is not set by an oscillator onthe board, but rather by an internal divider, so move the property tompfs.dtsi.This looks to be copy-pasta from the SiFive Unleashed as the commentsin both places were almost identical. In the Unleashed's case this looksto actually be valid, as the clock is provided by a crystal on the PCB.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>---CC: Conor Dooley <conor.dooley@microchip.com>CC: Daire McNamara <daire.mcnamara@microchip.com>CC: Rob Herring <robh+dt@kernel.org>CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>CC: Paul Walmsley <paul.walmsley@sifive.com>CC: Palmer Dabbelt <palmer@dabbelt.com>CC: linux-riscv@lists.infradead.orgCC: devicetree@vger.kernel.org
riscv: dts: microchip: convert isa detection to new propertiesConvert the PolarFire SoC devicetrees to use the new properties"riscv,isa-base" & "riscv,isa-extensions".For compatibility with other
riscv: dts: microchip: convert isa detection to new propertiesConvert the PolarFire SoC devicetrees to use the new properties"riscv,isa-base" & "riscv,isa-extensions".For compatibility with other projects, "riscv,isa" remains.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: fix the mpfs' mailbox regsThe mailbox on PolarFire SoC should really have three reg properties,not two. Without splitting into three sections, the system controller'sQSPI c
riscv: dts: microchip: fix the mpfs' mailbox regsThe mailbox on PolarFire SoC should really have three reg properties,not two. Without splitting into three sections, the system controller'sQSPI cannot be accessed as it sits inside the current first range. Thedriver & binding have been adapted to account for both two & threeranges, so fix the dts too.Acked-by: Palmer Dabbelt <palmer@rivosinc.com>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: add mpfs specific macb reset supportThe macb on PolarFire SoC has reset support which the generic compatibledoes not use. Add the newly introduced MPFS specific compatible a
riscv: dts: microchip: add mpfs specific macb reset supportThe macb on PolarFire SoC has reset support which the generic compatibledoes not use. Add the newly introduced MPFS specific compatible as theprimary compatible to avail of this support & wire up the reset to theclock controllers devicetree entry.Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"As it says on the tin, add a DT for this board. It's been sitting on mydesk for a while, so may as well have it upstream...
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"As it says on the tin, add a DT for this board. It's been sitting on mydesk for a while, so may as well have it upstream...The DT is only partially complete, as it needs the fabric content added.Unfortunately, I don't have a reference design in RTL or SmartDesignfor it and therefore don't know what that fabric content is.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: add the Aldec TySoM's devicetreeThe TySOM-M-MPFS250 is a compact SoC prototyping board featuringa Microchip PolarFire SoC MPFS250T-FCG1152. Features include:- 16 Gib FPGA D
riscv: dts: microchip: add the Aldec TySoM's devicetreeThe TySOM-M-MPFS250 is a compact SoC prototyping board featuringa Microchip PolarFire SoC MPFS250T-FCG1152. Features include:- 16 Gib FPGA DDR4- 16 Gib MSS DDR4 with ECC- eMMC- SPI flash memory- 2x Ethernet 10/100/1000- USB 2.0- PCIe x4 Gen2- HDMI OUT- 2x FMC connector (HPC and LPC)Specifically flag this board as rev2, in case later boards have anFPGA design revision with more features available in the future.Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250[Fixed a mistake where I read 16 Gib as 16 GiB!]Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOOConvert all non user visible use of SOC_FOO symbols to their ARCH_FOOvariants. The canaan DTs are an outlier in that they're gated at thedire
RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOOConvert all non user visible use of SOC_FOO symbols to their ARCH_FOOvariants. The canaan DTs are an outlier in that they're gated at thedirectory and the file level. Drop the directory level gating while weare swapping the symbol names over.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: remove unused pcie clocksThe PCIe root port in the designs that ship with the PolarBerry andM100PFSEVP are connected via one, not two Fabric Interface Controllers(FIC). The
riscv: dts: microchip: remove unused pcie clocksThe PCIe root port in the designs that ship with the PolarBerry andM100PFSEVP are connected via one, not two Fabric Interface Controllers(FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks fromthe dt node.The same clock provides both, so this is harmless but inaccurate.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: remove pcie node from the sev kitThe SEV kit reference design does not hook up the PCIe root port to thecore complex including it is misleading.The entry is a re-use mistak
riscv: dts: microchip: remove pcie node from the sev kitThe SEV kit reference design does not hook up the PCIe root port to thecore complex including it is misleading.The entry is a re-use mistake - I was not aware of this when I movedthe PCIe node out of mpfs.dtsi so that individual bistreams couldconnect it to different fics etc.The node is disabled, so there should be no functional change here.Fixes: 978a17d1a688 ("riscv: dts: microchip: add sevkit device tree")Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: fix the icicle's #pwm-cells\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &blindly overridden by the (out of tree) driver anyway. The core cansupport
riscv: dts: microchip: fix the icicle's #pwm-cells\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &blindly overridden by the (out of tree) driver anyway. The core cansupport inverted operation, so update the entry to correctly report itscapabilities.Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: fix memory node unit address for icicleEvidently I forgot to update the unit address for the 38-bit cachedmemory node when I changed the address in the reg property..Update
riscv: dts: microchip: fix memory node unit address for icicleEvidently I forgot to update the unit address for the 38-bit cachedmemory node when I changed the address in the reg property..Update it to match.Fixes: 6c1193301791 ("riscv: dts: microchip: update memory configuration for v2022.10")Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: icicle: Add GPIO controlled LEDsAdd the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC IcicleKit device tree. The schematic doesn't specify any special functionfor t
riscv: dts: microchip: icicle: Add GPIO controlled LEDsAdd the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC IcicleKit device tree. The schematic doesn't specify any special functionfor the LEDs, so they're added here without any default triggers andnamed led1, led2, led3 and led4 just like in the schematic.Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: add the mpfs' fabric clock controlThe "fabric clocks" in current PolarFire SoC device trees are notreally fixed clocks. Their frequency is set by the bitstream, so havingth
riscv: dts: microchip: add the mpfs' fabric clock controlThe "fabric clocks" in current PolarFire SoC device trees are notreally fixed clocks. Their frequency is set by the bitstream, so havingthem located in -fabric.dtsi is not a problem - they're just as "fixed"as the IP blocks etc used in the FPGA fabric.However, their configuration can be read at runtime (and to an extentthey can be controlled, although the intended usage is staticconfigurations set by the bitstream) through the system controller bus.In the v2022.09 icicle kit reference design a single CCC (north-westcorner) is enabled, using a 50 MHz off-chip oscillator as its reference.Updating to the v2022.09 icicle kit reference design is required, asprior to this release, the CCC was not fixed & could change for anygiven run of the synthesis tool.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Merge tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into for-nextMicrochip RISC-V devicetrees for v6.1Fixups, reference design changes and new boards:
Merge tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into for-nextMicrochip RISC-V devicetrees for v6.1Fixups, reference design changes and new boards:- The addition of QSPI support for mpfs had a corresponding change to the devicetree node.- The v2022.{09,10} reference designs brought with them several memory map changes which are not backwards compatible. The old devicetrees from the v2022.08 and earlier releases still work with current kernels.- Two new devicetrees for a first-party development kit and for the Aries Embedded M100FPSEVP kit.- Corresponding dt-bindings changes for the above.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>* tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: microchip: fix fabric i2c reg size riscv: dts: microchip: update memory configuration for v2022.10 riscv: dts: microchip: add a devicetree for aries' m100pfsevp riscv: dts: microchip: add sevkit device tree riscv: dts: microchip: reduce the fic3 clock rate riscv: dts: microchip: icicle: re-jig fabric peripheral addresses riscv: dts: microchip: icicle: update pci address properties riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi riscv: dts: microchip: add pci dma ranges for the icicle kit dt-bindings: riscv: microchip: document the sev kit dt-bindings: riscv: microchip: document the aries m100pfsevp dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: add qspi compatible fallbackSigned-off-by: Palmer Dabbelt <palmer@rivosinc.com>
riscv: dts: microchip: fix fabric i2c reg sizeThe size of the reg should've been changed when the address was changed,but obviously I forgot to do so.Fixes: ab291621a8b8 ("riscv: dts: microchip:
riscv: dts: microchip: fix fabric i2c reg sizeThe size of the reg should've been changed when the address was changed,but obviously I forgot to do so.Fixes: ab291621a8b8 ("riscv: dts: microchip: icicle: re-jig fabric peripheral addresses")Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
riscv: dts: microchip: update memory configuration for v2022.10In the v2022.10 reference design, the seg registers are going to bechanged, resulting in a required change to the memory map in Linux
riscv: dts: microchip: update memory configuration for v2022.10In the v2022.10 reference design, the seg registers are going to bechanged, resulting in a required change to the memory map in Linux.A small 4M reservation is made at the end of 32-bit DDR to provide somememory for the HSS to use, so that it can cache its payload.bin betweenreboots of a specific context.Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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