| b0258f69 | 10-Feb-2026 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPI
riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used
to ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct
mode", as they provide an exclusive connection from a GPIO to the PLIC.
The 3 remaining interrupts are used to mux the interrupts which do not
have a exclusive connection, one for each GPIO controller.
The mux was overlooked when the bindings and driver were originally
written for the GPIO controllers on Polarfire SoC, and the interrupts
property in the GPIO nodes used to try and convey what the mapping was.
Instead, the mux should be a device in its own right, and the GPIO
controllers should be connected to it, rather than to the PLIC.
Now that a binding exists for that mux, fix the inaccurate description
of the interrupt controller hierarchy.
GPIO controllers 0 and 1 do not have all 32 possible GPIO lines, so
ngpios needs to be set to match the number of lines/interrupts.
The m100pfsevp has conflicting interrupt mappings for controllers 0 and
2, as they cannot both be using an interrupt in "direct mode" at the
same time, so the default replaces this impossible configuration.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 4a1739c3 | 20-Nov-2025 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: add tsu clock to macb on mpfs
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
a
riscv: dts: microchip: add tsu clock to macb on mpfs
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is required for
correct rate selection.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 0aa19240 | 17-Nov-2025 |
Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> |
riscv: dts: microchip: remove POLARFIRE mention in Makefile
Substitute user hidden CONFIG_ARCH_MICROCHIP_POLARFIRE by user visible
CONFIG_ARCH_MICROCHIP.
Signed-off-by: Pierre-Henry Moussay <pierre
riscv: dts: microchip: remove POLARFIRE mention in Makefile
Substitute user hidden CONFIG_ARCH_MICROCHIP_POLARFIRE by user visible
CONFIG_ARCH_MICROCHIP.
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 7219d20f | 17-Nov-2025 |
Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> |
riscv: dts: microchip: add pic64gx and its curiosity kit
The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC
prototyping board featuring a Microchip PIC64GX SoC PIC64GC-1000.
Features
riscv: dts: microchip: add pic64gx and its curiosity kit
The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC
prototyping board featuring a Microchip PIC64GX SoC PIC64GC-1000.
Features include:
- 1 GB DDR4 SDRAM
- Gigabit Ethernet
- microSD-card slot
note: due to issue on some board, the SDHCI is limited to HS (High
speed mode, with a clock of 50MHz and 3.3V signals).
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 26535e84 | 10-Nov-2025 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: convert clock and reset to use syscon
The "subblock" clocks and reset registers on PolarFire SoC are located
in the mss-top-sysreg region, alongside pinctrl and interrupt cont
riscv: dts: microchip: convert clock and reset to use syscon
The "subblock" clocks and reset registers on PolarFire SoC are located
in the mss-top-sysreg region, alongside pinctrl and interrupt control
functionality. Re-write the devicetree to describe the sys explicitly,
as its own node, rather than as a region of the clock node.
Correspondingly, the phandles to the reset controller must be updated to
the new provider. The drivers will continue to support the old way of
doing things.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 02428682 | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
Rename the Clock Conditioning Circuit (CCC) reference clock to match
the fixed clock bindings naming recommendation.
Update
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
Rename the Clock Conditioning Circuit (CCC) reference clock to match
the fixed clock bindings naming recommendation.
Update the reserved memory regions in the Icicle Kit common dtsi to
use lowercase hex and drop the redundant status properties from the
memory regions, as they are not required.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 2775e87c | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: add icicle kit with production device
With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sampl
riscv: dts: microchip: add icicle kit with production device
With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sample
(-es) variant. Engineering samples cannot write to flash from the MSS,
as noted in the PolarFire SoC FPGA ES errata.
Add a new device tree (mpfs-icicle-kit-prod.dts) for the production
board which includes the icicle kit common dtsi and enable the system
controller SPI flash, which is only accessible on production silicon.
Remove redundant board compatible from fabric dtsi and update board
compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP
cluster communication.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| f401a8ba | 08-Sep-2025 |
Valentina Fernandez <valentina.fernandezalanis@microchip.com> |
riscv: dts: microchip: add common board dtsi for icicle kit variants
In preparation for supporting the Icicle Kit with production silicon,
add a common board dtsi for the icicle kit with hardware sh
riscv: dts: microchip: add common board dtsi for icicle kit variants
In preparation for supporting the Icicle Kit with production silicon,
add a common board dtsi for the icicle kit with hardware shared by both
the engineering sample and production versions.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 5669bb5a | 08-Dec-2023 |
Shravan Chippa <shravan.chippa@microchip.com> |
riscv: dts: microchip: add specific compatible for mpfs pdma
Add specific compatible for PolarFire SoC for The SiFive PDMA driver
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-b
riscv: dts: microchip: add specific compatible for mpfs pdma
Add specific compatible for PolarFire SoC for The SiFive PDMA driver
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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