xref: /linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision 0e9b70c1e3623fa110fb6be553e644524228ef60) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - renesas,r9a07g043-plic
57          - const: andestech,nceplic100
58      - items:
59          - enum:
60              - sifive,fu540-c000-plic
61              - starfive,jh7100-plic
62              - canaan,k210-plic
63          - const: sifive,plic-1.0.0
64      - items:
65          - enum:
66              - allwinner,sun20i-d1-plic
67          - const: thead,c900-plic
68      - items:
69          - const: sifive,plic-1.0.0
70          - const: riscv,plic0
71        deprecated: true
72        description: For the QEMU virt machine only
73
74  reg:
75    maxItems: 1
76
77  '#address-cells':
78    const: 0
79
80  '#interrupt-cells': true
81
82  interrupt-controller: true
83
84  interrupts-extended:
85    minItems: 1
86    maxItems: 15872
87    description:
88      Specifies which contexts are connected to the PLIC, with "-1" specifying
89      that a context is not present. Each node pointed to should be a
90      riscv,cpu-intc node, which has a riscv node as parent.
91
92  riscv,ndev:
93    $ref: "/schemas/types.yaml#/definitions/uint32"
94    description:
95      Specifies how many external interrupts are supported by this controller.
96
97  clocks: true
98
99  power-domains: true
100
101  resets: true
102
103required:
104  - compatible
105  - '#address-cells'
106  - '#interrupt-cells'
107  - interrupt-controller
108  - reg
109  - interrupts-extended
110  - riscv,ndev
111
112allOf:
113  - if:
114      properties:
115        compatible:
116          contains:
117            enum:
118              - andestech,nceplic100
119              - thead,c900-plic
120
121    then:
122      properties:
123        '#interrupt-cells':
124          const: 2
125
126    else:
127      properties:
128        '#interrupt-cells':
129          const: 1
130
131  - if:
132      properties:
133        compatible:
134          contains:
135            const: renesas,r9a07g043-plic
136
137    then:
138      properties:
139        clocks:
140          maxItems: 1
141
142        power-domains:
143          maxItems: 1
144
145        resets:
146          maxItems: 1
147
148      required:
149        - clocks
150        - power-domains
151        - resets
152
153additionalProperties: false
154
155examples:
156  - |
157    plic: interrupt-controller@c000000 {
158      #address-cells = <0>;
159      #interrupt-cells = <1>;
160      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
161      interrupt-controller;
162      interrupts-extended = <&cpu0_intc 11>,
163                            <&cpu1_intc 11>, <&cpu1_intc 9>,
164                            <&cpu2_intc 11>, <&cpu2_intc 9>,
165                            <&cpu3_intc 11>, <&cpu3_intc 9>,
166                            <&cpu4_intc 11>, <&cpu4_intc 9>;
167      reg = <0xc000000 0x4000000>;
168      riscv,ndev = <10>;
169    };
170