xref: /linux/drivers/clk/meson/clk-pll.h (revision 561add0da6d3d07c9bccb0832fb6ed5619167d26)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2019 BayLibre, SAS.
4  * Author: Jerome Brunet <jbrunet@baylibre.com>
5  */
6 
7 #ifndef __MESON_CLK_PLL_H
8 #define __MESON_CLK_PLL_H
9 
10 #include <linux/clk-provider.h>
11 #include <linux/regmap.h>
12 #include "parm.h"
13 
14 struct pll_params_table {
15 	unsigned int	m;
16 	unsigned int	n;
17 };
18 
19 struct pll_mult_range {
20 	unsigned int	min;
21 	unsigned int	max;
22 };
23 
24 #define PLL_PARAMS(_m, _n)						\
25 	{								\
26 		.m		= (_m),					\
27 		.n		= (_n),					\
28 	}
29 
30 #define CLK_MESON_PLL_ROUND_CLOSEST	BIT(0)
31 
32 struct meson_clk_pll_data {
33 	struct parm en;
34 	struct parm m;
35 	struct parm n;
36 	struct parm frac;
37 	struct parm l;
38 	struct parm rst;
39 	struct parm current_en;
40 	struct parm l_detect;
41 	const struct reg_sequence *init_regs;
42 	unsigned int init_count;
43 	const struct pll_params_table *table;
44 	const struct pll_mult_range *range;
45 	u8 flags;
46 };
47 
48 extern const struct clk_ops meson_clk_pll_ro_ops;
49 extern const struct clk_ops meson_clk_pll_ops;
50 extern const struct clk_ops meson_clk_pcie_pll_ops;
51 
52 #endif /* __MESON_CLK_PLL_H */
53