1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 3 * Copyright (c) 2023 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,ipq9574-gcc.h> 14 #include <dt-bindings/reset/qcom,ipq9574-gcc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "clk-regmap-phy-mux.h" 23 #include "common.h" 24 #include "reset.h" 25 26 /* Need to match the order of clocks in DT binding */ 27 enum { 28 DT_XO, 29 DT_SLEEP_CLK, 30 DT_BIAS_PLL_UBI_NC_CLK, 31 DT_PCIE30_PHY0_PIPE_CLK, 32 DT_PCIE30_PHY1_PIPE_CLK, 33 DT_PCIE30_PHY2_PIPE_CLK, 34 DT_PCIE30_PHY3_PIPE_CLK, 35 DT_USB3PHY_0_CC_PIPE_CLK, 36 }; 37 38 enum { 39 P_XO, 40 P_PCIE30_PHY0_PIPE, 41 P_PCIE30_PHY1_PIPE, 42 P_PCIE30_PHY2_PIPE, 43 P_PCIE30_PHY3_PIPE, 44 P_USB3PHY_0_PIPE, 45 P_GPLL0, 46 P_GPLL0_DIV2, 47 P_GPLL0_OUT_AUX, 48 P_GPLL2, 49 P_GPLL4, 50 P_PI_SLEEP, 51 P_BIAS_PLL_UBI_NC_CLK, 52 }; 53 54 static const struct parent_map gcc_xo_map[] = { 55 { P_XO, 0 }, 56 }; 57 58 static const struct clk_parent_data gcc_xo_data[] = { 59 { .index = DT_XO }, 60 }; 61 62 static const struct clk_parent_data gcc_sleep_clk_data[] = { 63 { .index = DT_SLEEP_CLK }, 64 }; 65 66 static struct clk_alpha_pll gpll0_main = { 67 .offset = 0x20000, 68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 69 .clkr = { 70 .enable_reg = 0x0b000, 71 .enable_mask = BIT(0), 72 .hw.init = &(const struct clk_init_data) { 73 .name = "gpll0_main", 74 .parent_data = gcc_xo_data, 75 .num_parents = ARRAY_SIZE(gcc_xo_data), 76 .ops = &clk_alpha_pll_ops, 77 }, 78 }, 79 }; 80 81 static struct clk_fixed_factor gpll0_out_main_div2 = { 82 .mult = 1, 83 .div = 2, 84 .hw.init = &(const struct clk_init_data) { 85 .name = "gpll0_out_main_div2", 86 .parent_hws = (const struct clk_hw *[]) { 87 &gpll0_main.clkr.hw 88 }, 89 .num_parents = 1, 90 .flags = CLK_SET_RATE_PARENT, 91 .ops = &clk_fixed_factor_ops, 92 }, 93 }; 94 95 static struct clk_alpha_pll_postdiv gpll0 = { 96 .offset = 0x20000, 97 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 98 .width = 4, 99 .clkr.hw.init = &(const struct clk_init_data) { 100 .name = "gpll0", 101 .parent_hws = (const struct clk_hw *[]) { 102 &gpll0_main.clkr.hw 103 }, 104 .num_parents = 1, 105 .flags = CLK_SET_RATE_PARENT, 106 .ops = &clk_alpha_pll_postdiv_ro_ops, 107 }, 108 }; 109 110 static struct clk_alpha_pll gpll4_main = { 111 .offset = 0x22000, 112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 113 .clkr = { 114 .enable_reg = 0x0b000, 115 .enable_mask = BIT(2), 116 .hw.init = &(const struct clk_init_data) { 117 .name = "gpll4_main", 118 .parent_data = gcc_xo_data, 119 .num_parents = ARRAY_SIZE(gcc_xo_data), 120 .ops = &clk_alpha_pll_ops, 121 }, 122 }, 123 }; 124 125 static struct clk_alpha_pll_postdiv gpll4 = { 126 .offset = 0x22000, 127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 128 .width = 4, 129 .clkr.hw.init = &(const struct clk_init_data) { 130 .name = "gpll4", 131 .parent_hws = (const struct clk_hw *[]) { 132 &gpll4_main.clkr.hw 133 }, 134 .num_parents = 1, 135 .flags = CLK_SET_RATE_PARENT, 136 .ops = &clk_alpha_pll_postdiv_ro_ops, 137 }, 138 }; 139 140 static struct clk_alpha_pll gpll2_main = { 141 .offset = 0x21000, 142 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 143 .clkr = { 144 .enable_reg = 0x0b000, 145 .enable_mask = BIT(1), 146 .hw.init = &(const struct clk_init_data) { 147 .name = "gpll2_main", 148 .parent_data = gcc_xo_data, 149 .num_parents = ARRAY_SIZE(gcc_xo_data), 150 .ops = &clk_alpha_pll_ops, 151 }, 152 }, 153 }; 154 155 static struct clk_alpha_pll_postdiv gpll2 = { 156 .offset = 0x21000, 157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 158 .width = 4, 159 .clkr.hw.init = &(const struct clk_init_data) { 160 .name = "gpll2", 161 .parent_hws = (const struct clk_hw *[]) { 162 &gpll2_main.clkr.hw 163 }, 164 .num_parents = 1, 165 .flags = CLK_SET_RATE_PARENT, 166 .ops = &clk_alpha_pll_postdiv_ro_ops, 167 }, 168 }; 169 170 static struct clk_branch gcc_sleep_clk_src = { 171 .halt_reg = 0x3400c, 172 .clkr = { 173 .enable_reg = 0x3400c, 174 .enable_mask = BIT(1), 175 .hw.init = &(const struct clk_init_data) { 176 .name = "gcc_sleep_clk_src", 177 .parent_data = gcc_sleep_clk_data, 178 .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), 179 .flags = CLK_IS_CRITICAL, 180 .ops = &clk_branch2_ops, 181 }, 182 }, 183 }; 184 185 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { 186 { .index = DT_XO }, 187 { .hw = &gpll0.clkr.hw }, 188 { .hw = &gpll0_out_main_div2.hw }, 189 }; 190 191 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { 192 { P_XO, 0 }, 193 { P_GPLL0, 1 }, 194 { P_GPLL0_DIV2, 4 }, 195 }; 196 197 static const struct clk_parent_data gcc_xo_gpll0[] = { 198 { .index = DT_XO }, 199 { .hw = &gpll0.clkr.hw }, 200 }; 201 202 static const struct parent_map gcc_xo_gpll0_map[] = { 203 { P_XO, 0 }, 204 { P_GPLL0, 1 }, 205 }; 206 207 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 208 { .index = DT_XO }, 209 { .hw = &gpll0.clkr.hw }, 210 { .hw = &gpll4.clkr.hw }, 211 }; 212 213 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 214 { P_XO, 0 }, 215 { P_GPLL0, 1 }, 216 { P_GPLL4, 2 }, 217 }; 218 219 static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = { 220 { .index = DT_XO }, 221 { .hw = &gpll0.clkr.hw }, 222 { .hw = &gpll0_out_main_div2.hw }, 223 { .hw = &gpll0.clkr.hw }, 224 }; 225 226 static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = { 227 { P_XO, 0 }, 228 { P_GPLL0, 1 }, 229 { P_GPLL0_DIV2, 4 }, 230 { P_GPLL0, 5 }, 231 }; 232 233 static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = { 234 { .index = DT_XO }, 235 { .hw = &gpll0.clkr.hw }, 236 { .hw = &gpll0_out_main_div2.hw }, 237 { .index = DT_SLEEP_CLK }, 238 }; 239 240 static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = { 241 { P_XO, 0 }, 242 { P_GPLL0, 1 }, 243 { P_GPLL0_DIV2, 4 }, 244 { P_PI_SLEEP, 6 }, 245 }; 246 247 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = { 248 { .index = DT_XO }, 249 { .hw = &gpll0.clkr.hw }, 250 { .index = DT_SLEEP_CLK }, 251 }; 252 253 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = { 254 { P_XO, 0 }, 255 { P_GPLL0, 2 }, 256 { P_PI_SLEEP, 6 }, 257 }; 258 259 static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = { 260 { .index = DT_XO }, 261 { .hw = &gpll0.clkr.hw }, 262 { .hw = &gpll4.clkr.hw }, 263 { .index = DT_BIAS_PLL_UBI_NC_CLK }, 264 }; 265 266 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = { 267 { P_XO, 0 }, 268 { P_GPLL0, 1 }, 269 { P_GPLL4, 2 }, 270 { P_BIAS_PLL_UBI_NC_CLK, 3 }, 271 }; 272 273 static const struct clk_parent_data 274 gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = { 275 { .index = DT_XO }, 276 { .hw = &gpll0.clkr.hw }, 277 { .hw = &gpll0.clkr.hw }, 278 { .index = DT_SLEEP_CLK }, 279 }; 280 281 static const struct parent_map 282 gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = { 283 { P_XO, 0 }, 284 { P_GPLL0, 1 }, 285 { P_GPLL0_OUT_AUX, 2 }, 286 { P_PI_SLEEP, 6 }, 287 }; 288 289 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = { 290 { .index = DT_XO }, 291 { .hw = &gpll0.clkr.hw }, 292 { .hw = &gpll0_out_main_div2.hw }, 293 }; 294 295 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { 296 { P_XO, 0 }, 297 { P_GPLL0, 1 }, 298 { P_GPLL0_DIV2, 4 }, 299 }; 300 301 static const struct clk_parent_data 302 gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = { 303 { .index = DT_XO }, 304 { .hw = &gpll4.clkr.hw }, 305 { .hw = &gpll0.clkr.hw }, 306 { .hw = &gpll0_out_main_div2.hw }, 307 }; 308 309 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = { 310 { P_XO, 0 }, 311 { P_GPLL4, 1 }, 312 { P_GPLL0, 3 }, 313 { P_GPLL0_DIV2, 4 }, 314 }; 315 316 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { 317 { .index = DT_USB3PHY_0_CC_PIPE_CLK }, 318 { .index = DT_XO }, 319 }; 320 321 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { 322 { P_USB3PHY_0_PIPE, 0 }, 323 { P_XO, 2 }, 324 }; 325 326 static const struct clk_parent_data 327 gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { 328 { .index = DT_XO }, 329 { .hw = &gpll0.clkr.hw }, 330 { .hw = &gpll2.clkr.hw }, 331 { .hw = &gpll0_out_main_div2.hw }, 332 }; 333 334 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { 335 { P_XO, 0 }, 336 { P_GPLL0, 1 }, 337 { P_GPLL2, 2 }, 338 { P_GPLL0_DIV2, 4 }, 339 }; 340 341 static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = { 342 { .index = DT_XO}, 343 { .hw = &gpll0.clkr.hw }, 344 { .hw = &gpll4.clkr.hw }, 345 { .hw = &gpll0_out_main_div2.hw }, 346 }; 347 348 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = { 349 { P_XO, 0 }, 350 { P_GPLL0, 1 }, 351 { P_GPLL4, 2 }, 352 { P_GPLL0_DIV2, 4 }, 353 }; 354 355 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = { 356 { .index = DT_XO }, 357 { .hw = &gpll4.clkr.hw }, 358 { .hw = &gpll0.clkr.hw }, 359 { .hw = &gpll0_out_main_div2.hw }, 360 }; 361 362 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = { 363 { P_XO, 0 }, 364 { P_GPLL4, 1 }, 365 { P_GPLL0, 2 }, 366 { P_GPLL0_DIV2, 4 }, 367 }; 368 369 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { 370 { .index = DT_XO }, 371 { .hw = &gpll0.clkr.hw }, 372 { .hw = &gpll2.clkr.hw }, 373 }; 374 375 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 376 { P_XO, 0 }, 377 { P_GPLL0, 1 }, 378 { P_GPLL2, 2 }, 379 }; 380 381 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = { 382 { .index = DT_XO }, 383 { .hw = &gpll0.clkr.hw }, 384 { .hw = &gpll2.clkr.hw }, 385 { .hw = &gpll4.clkr.hw }, 386 { .index = DT_SLEEP_CLK }, 387 }; 388 389 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = { 390 { P_XO, 0 }, 391 { P_GPLL0, 1 }, 392 { P_GPLL2, 2 }, 393 { P_GPLL4, 3 }, 394 { P_PI_SLEEP, 6 }, 395 }; 396 397 static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = { 398 { .index = DT_XO }, 399 { .hw = &gpll0.clkr.hw }, 400 { .hw = &gpll0.clkr.hw }, 401 { .hw = &gpll2.clkr.hw }, 402 }; 403 404 static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = { 405 { P_XO, 0 }, 406 { P_GPLL0, 1 }, 407 { P_GPLL0_OUT_AUX, 2 }, 408 { P_GPLL2, 3 }, 409 }; 410 411 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { 412 F(24000000, P_XO, 1, 0, 0), 413 F(50000000, P_GPLL0, 16, 0, 0), 414 F(100000000, P_GPLL0, 8, 0, 0), 415 { } 416 }; 417 418 static struct clk_rcg2 apss_ahb_clk_src = { 419 .cmd_rcgr = 0x2400c, 420 .freq_tbl = ftbl_apss_ahb_clk_src, 421 .hid_width = 5, 422 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 423 .clkr.hw.init = &(const struct clk_init_data) { 424 .name = "apss_ahb_clk_src", 425 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 426 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 427 .ops = &clk_rcg2_ops, 428 }, 429 }; 430 431 static const struct freq_tbl ftbl_apss_axi_clk_src[] = { 432 F(533000000, P_GPLL0, 1.5, 0, 0), 433 { } 434 }; 435 436 static struct clk_rcg2 apss_axi_clk_src = { 437 .cmd_rcgr = 0x24004, 438 .freq_tbl = ftbl_apss_axi_clk_src, 439 .hid_width = 5, 440 .parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map, 441 .clkr.hw.init = &(const struct clk_init_data) { 442 .name = "apss_axi_clk_src", 443 .parent_data = gcc_xo_gpll0_gpll0_div2_gpll0, 444 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0), 445 .ops = &clk_rcg2_ops, 446 }, 447 }; 448 449 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { 450 F(9600000, P_XO, 2.5, 0, 0), 451 F(24000000, P_XO, 1, 0, 0), 452 F(50000000, P_GPLL0, 16, 0, 0), 453 { } 454 }; 455 456 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 457 .cmd_rcgr = 0x02018, 458 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 459 .hid_width = 5, 460 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 461 .clkr.hw.init = &(const struct clk_init_data) { 462 .name = "blsp1_qup1_i2c_apps_clk_src", 463 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 464 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 465 .ops = &clk_rcg2_ops, 466 }, 467 }; 468 469 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { 470 F(960000, P_XO, 10, 2, 5), 471 F(4800000, P_XO, 5, 0, 0), 472 F(9600000, P_XO, 2, 4, 5), 473 F(16000000, P_GPLL0, 10, 1, 5), 474 F(24000000, P_XO, 1, 0, 0), 475 F(25000000, P_GPLL0, 16, 1, 2), 476 F(50000000, P_GPLL0, 16, 0, 0), 477 { } 478 }; 479 480 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 481 .cmd_rcgr = 0x02004, 482 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 483 .mnd_width = 8, 484 .hid_width = 5, 485 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 486 .clkr.hw.init = &(const struct clk_init_data) { 487 .name = "blsp1_qup1_spi_apps_clk_src", 488 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 489 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 490 .ops = &clk_rcg2_ops, 491 }, 492 }; 493 494 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 495 .cmd_rcgr = 0x03018, 496 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 497 .hid_width = 5, 498 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 499 .clkr.hw.init = &(const struct clk_init_data) { 500 .name = "blsp1_qup2_i2c_apps_clk_src", 501 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 502 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 503 .ops = &clk_rcg2_ops, 504 }, 505 }; 506 507 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 508 .cmd_rcgr = 0x03004, 509 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 510 .mnd_width = 8, 511 .hid_width = 5, 512 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 513 .clkr.hw.init = &(const struct clk_init_data) { 514 .name = "blsp1_qup2_spi_apps_clk_src", 515 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 516 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 517 .ops = &clk_rcg2_ops, 518 }, 519 }; 520 521 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 522 .cmd_rcgr = 0x04018, 523 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 524 .hid_width = 5, 525 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 526 .clkr.hw.init = &(const struct clk_init_data) { 527 .name = "blsp1_qup3_i2c_apps_clk_src", 528 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 529 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 530 .ops = &clk_rcg2_ops, 531 }, 532 }; 533 534 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 535 .cmd_rcgr = 0x04004, 536 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 537 .mnd_width = 8, 538 .hid_width = 5, 539 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 540 .clkr.hw.init = &(const struct clk_init_data) { 541 .name = "blsp1_qup3_spi_apps_clk_src", 542 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 543 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 549 .cmd_rcgr = 0x05018, 550 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 551 .hid_width = 5, 552 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 553 .clkr.hw.init = &(const struct clk_init_data) { 554 .name = "blsp1_qup4_i2c_apps_clk_src", 555 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 556 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 557 .ops = &clk_rcg2_ops, 558 }, 559 }; 560 561 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 562 .cmd_rcgr = 0x05004, 563 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 564 .mnd_width = 8, 565 .hid_width = 5, 566 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 567 .clkr.hw.init = &(const struct clk_init_data) { 568 .name = "blsp1_qup4_spi_apps_clk_src", 569 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 570 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 571 .ops = &clk_rcg2_ops, 572 }, 573 }; 574 575 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 576 .cmd_rcgr = 0x06018, 577 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 578 .hid_width = 5, 579 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 580 .clkr.hw.init = &(const struct clk_init_data) { 581 .name = "blsp1_qup5_i2c_apps_clk_src", 582 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 583 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 584 .ops = &clk_rcg2_ops, 585 }, 586 }; 587 588 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 589 .cmd_rcgr = 0x06004, 590 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 591 .mnd_width = 8, 592 .hid_width = 5, 593 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 594 .clkr.hw.init = &(const struct clk_init_data) { 595 .name = "blsp1_qup5_spi_apps_clk_src", 596 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 597 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 598 .ops = &clk_rcg2_ops, 599 }, 600 }; 601 602 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 603 .cmd_rcgr = 0x07018, 604 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 605 .hid_width = 5, 606 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 607 .clkr.hw.init = &(const struct clk_init_data) { 608 .name = "blsp1_qup6_i2c_apps_clk_src", 609 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 610 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 611 .ops = &clk_rcg2_ops, 612 }, 613 }; 614 615 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 616 .cmd_rcgr = 0x07004, 617 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 618 .mnd_width = 8, 619 .hid_width = 5, 620 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 621 .clkr.hw.init = &(const struct clk_init_data) { 622 .name = "blsp1_qup6_spi_apps_clk_src", 623 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 624 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 625 .ops = &clk_rcg2_ops, 626 }, 627 }; 628 629 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { 630 F(3686400, P_GPLL0_DIV2, 1, 144, 15625), 631 F(7372800, P_GPLL0_DIV2, 1, 288, 15625), 632 F(14745600, P_GPLL0_DIV2, 1, 576, 15625), 633 F(24000000, P_XO, 1, 0, 0), 634 F(25000000, P_GPLL0, 16, 1, 2), 635 F(32000000, P_GPLL0, 1, 1, 25), 636 F(40000000, P_GPLL0, 1, 1, 20), 637 F(46400000, P_GPLL0, 1, 29, 500), 638 F(48000000, P_GPLL0, 1, 3, 50), 639 F(51200000, P_GPLL0, 1, 8, 125), 640 F(56000000, P_GPLL0, 1, 7, 100), 641 F(58982400, P_GPLL0, 1, 1152, 15625), 642 F(60000000, P_GPLL0, 1, 3, 40), 643 F(64000000, P_GPLL0, 12.5, 0, 0), 644 { } 645 }; 646 647 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 648 .cmd_rcgr = 0x0202c, 649 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 650 .mnd_width = 16, 651 .hid_width = 5, 652 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 653 .clkr.hw.init = &(const struct clk_init_data) { 654 .name = "blsp1_uart1_apps_clk_src", 655 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 656 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 657 .ops = &clk_rcg2_ops, 658 }, 659 }; 660 661 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 662 .cmd_rcgr = 0x0302c, 663 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 664 .mnd_width = 16, 665 .hid_width = 5, 666 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 667 .clkr.hw.init = &(const struct clk_init_data) { 668 .name = "blsp1_uart2_apps_clk_src", 669 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 670 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 671 .ops = &clk_rcg2_ops, 672 }, 673 }; 674 675 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 676 .cmd_rcgr = 0x0402c, 677 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 678 .mnd_width = 16, 679 .hid_width = 5, 680 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 681 .clkr.hw.init = &(const struct clk_init_data) { 682 .name = "blsp1_uart3_apps_clk_src", 683 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 684 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 685 .ops = &clk_rcg2_ops, 686 }, 687 }; 688 689 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 690 .cmd_rcgr = 0x0502c, 691 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 692 .mnd_width = 16, 693 .hid_width = 5, 694 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 695 .clkr.hw.init = &(const struct clk_init_data) { 696 .name = "blsp1_uart4_apps_clk_src", 697 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 698 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 699 .ops = &clk_rcg2_ops, 700 }, 701 }; 702 703 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 704 .cmd_rcgr = 0x0602c, 705 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 706 .mnd_width = 16, 707 .hid_width = 5, 708 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 709 .clkr.hw.init = &(const struct clk_init_data) { 710 .name = "blsp1_uart5_apps_clk_src", 711 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 712 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 713 .ops = &clk_rcg2_ops, 714 }, 715 }; 716 717 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 718 .cmd_rcgr = 0x0702c, 719 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 720 .mnd_width = 16, 721 .hid_width = 5, 722 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 723 .clkr.hw.init = &(const struct clk_init_data) { 724 .name = "blsp1_uart6_apps_clk_src", 725 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 726 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 727 .ops = &clk_rcg2_ops, 728 }, 729 }; 730 731 static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = { 732 F(160000000, P_GPLL0, 5, 0, 0), 733 { } 734 }; 735 736 static struct clk_rcg2 gcc_crypto_clk_src = { 737 .cmd_rcgr = 0x16004, 738 .freq_tbl = ftbl_gcc_crypto_clk_src, 739 .hid_width = 5, 740 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 741 .clkr.hw.init = &(const struct clk_init_data) { 742 .name = "gcc_crypto_clk_src", 743 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 744 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 745 .ops = &clk_rcg2_ops, 746 }, 747 }; 748 749 static struct clk_branch gcc_crypto_clk = { 750 .halt_reg = 0x1600c, 751 .halt_check = BRANCH_HALT_VOTED, 752 .clkr = { 753 .enable_reg = 0x0b004, 754 .enable_mask = BIT(14), 755 .hw.init = &(const struct clk_init_data) { 756 .name = "gcc_crypto_clk", 757 .parent_hws = (const struct clk_hw *[]) { 758 &gcc_crypto_clk_src.clkr.hw }, 759 .num_parents = 1, 760 .flags = CLK_SET_RATE_PARENT, 761 .ops = &clk_branch2_ops, 762 }, 763 }, 764 }; 765 766 static struct clk_branch gcc_apss_ahb_clk = { 767 .halt_reg = 0x24018, 768 .halt_check = BRANCH_HALT_VOTED, 769 .clkr = { 770 .enable_reg = 0x0b004, 771 .enable_mask = BIT(0), 772 .hw.init = &(const struct clk_init_data) { 773 .name = "gcc_apss_ahb_clk", 774 .parent_hws = (const struct clk_hw *[]) { 775 &apss_ahb_clk_src.clkr.hw 776 }, 777 .num_parents = 1, 778 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 779 .ops = &clk_branch2_ops, 780 }, 781 }, 782 }; 783 784 static struct clk_branch gcc_apss_axi_clk = { 785 .halt_reg = 0x2401c, 786 .halt_check = BRANCH_HALT_VOTED, 787 .clkr = { 788 .enable_reg = 0x0b004, 789 .enable_mask = BIT(1), 790 .hw.init = &(const struct clk_init_data) { 791 .name = "gcc_apss_axi_clk", 792 .parent_hws = (const struct clk_hw *[]) { 793 &apss_axi_clk_src.clkr.hw 794 }, 795 .num_parents = 1, 796 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 797 .ops = &clk_branch2_ops, 798 }, 799 }, 800 }; 801 802 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 803 .halt_reg = 0x2024, 804 .clkr = { 805 .enable_reg = 0x2024, 806 .enable_mask = BIT(0), 807 .hw.init = &(const struct clk_init_data) { 808 .name = "gcc_blsp1_qup1_i2c_apps_clk", 809 .parent_hws = (const struct clk_hw *[]) { 810 &blsp1_qup1_i2c_apps_clk_src.clkr.hw 811 }, 812 .num_parents = 1, 813 .flags = CLK_SET_RATE_PARENT, 814 .ops = &clk_branch2_ops, 815 }, 816 }, 817 }; 818 819 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 820 .halt_reg = 0x02020, 821 .clkr = { 822 .enable_reg = 0x02020, 823 .enable_mask = BIT(0), 824 .hw.init = &(const struct clk_init_data) { 825 .name = "gcc_blsp1_qup1_spi_apps_clk", 826 .parent_hws = (const struct clk_hw *[]) { 827 &blsp1_qup1_spi_apps_clk_src.clkr.hw 828 }, 829 .num_parents = 1, 830 .flags = CLK_SET_RATE_PARENT, 831 .ops = &clk_branch2_ops, 832 }, 833 }, 834 }; 835 836 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 837 .halt_reg = 0x03024, 838 .clkr = { 839 .enable_reg = 0x03024, 840 .enable_mask = BIT(0), 841 .hw.init = &(const struct clk_init_data) { 842 .name = "gcc_blsp1_qup2_i2c_apps_clk", 843 .parent_hws = (const struct clk_hw *[]) { 844 &blsp1_qup2_i2c_apps_clk_src.clkr.hw 845 }, 846 .num_parents = 1, 847 .flags = CLK_SET_RATE_PARENT, 848 .ops = &clk_branch2_ops, 849 }, 850 }, 851 }; 852 853 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 854 .halt_reg = 0x03020, 855 .clkr = { 856 .enable_reg = 0x03020, 857 .enable_mask = BIT(0), 858 .hw.init = &(const struct clk_init_data) { 859 .name = "gcc_blsp1_qup2_spi_apps_clk", 860 .parent_hws = (const struct clk_hw *[]) { 861 &blsp1_qup2_spi_apps_clk_src.clkr.hw 862 }, 863 .num_parents = 1, 864 .flags = CLK_SET_RATE_PARENT, 865 .ops = &clk_branch2_ops, 866 }, 867 }, 868 }; 869 870 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 871 .halt_reg = 0x04024, 872 .clkr = { 873 .enable_reg = 0x04024, 874 .enable_mask = BIT(0), 875 .hw.init = &(const struct clk_init_data) { 876 .name = "gcc_blsp1_qup3_i2c_apps_clk", 877 .parent_hws = (const struct clk_hw *[]) { 878 &blsp1_qup3_i2c_apps_clk_src.clkr.hw 879 }, 880 .num_parents = 1, 881 .flags = CLK_SET_RATE_PARENT, 882 .ops = &clk_branch2_ops, 883 }, 884 }, 885 }; 886 887 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 888 .halt_reg = 0x04020, 889 .clkr = { 890 .enable_reg = 0x04020, 891 .enable_mask = BIT(0), 892 .hw.init = &(const struct clk_init_data) { 893 .name = "gcc_blsp1_qup3_spi_apps_clk", 894 .parent_hws = (const struct clk_hw *[]) { 895 &blsp1_qup3_spi_apps_clk_src.clkr.hw 896 }, 897 .num_parents = 1, 898 .flags = CLK_SET_RATE_PARENT, 899 .ops = &clk_branch2_ops, 900 }, 901 }, 902 }; 903 904 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 905 .halt_reg = 0x05024, 906 .clkr = { 907 .enable_reg = 0x05024, 908 .enable_mask = BIT(0), 909 .hw.init = &(const struct clk_init_data) { 910 .name = "gcc_blsp1_qup4_i2c_apps_clk", 911 .parent_hws = (const struct clk_hw *[]) { 912 &blsp1_qup4_i2c_apps_clk_src.clkr.hw 913 }, 914 .num_parents = 1, 915 .flags = CLK_SET_RATE_PARENT, 916 .ops = &clk_branch2_ops, 917 }, 918 }, 919 }; 920 921 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 922 .halt_reg = 0x05020, 923 .clkr = { 924 .enable_reg = 0x05020, 925 .enable_mask = BIT(0), 926 .hw.init = &(const struct clk_init_data) { 927 .name = "gcc_blsp1_qup4_spi_apps_clk", 928 .parent_hws = (const struct clk_hw *[]) { 929 &blsp1_qup4_spi_apps_clk_src.clkr.hw 930 }, 931 .num_parents = 1, 932 .flags = CLK_SET_RATE_PARENT, 933 .ops = &clk_branch2_ops, 934 }, 935 }, 936 }; 937 938 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 939 .halt_reg = 0x06024, 940 .clkr = { 941 .enable_reg = 0x06024, 942 .enable_mask = BIT(0), 943 .hw.init = &(const struct clk_init_data) { 944 .name = "gcc_blsp1_qup5_i2c_apps_clk", 945 .parent_hws = (const struct clk_hw *[]) { 946 &blsp1_qup5_i2c_apps_clk_src.clkr.hw 947 }, 948 .num_parents = 1, 949 .flags = CLK_SET_RATE_PARENT, 950 .ops = &clk_branch2_ops, 951 }, 952 }, 953 }; 954 955 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 956 .halt_reg = 0x06020, 957 .clkr = { 958 .enable_reg = 0x06020, 959 .enable_mask = BIT(0), 960 .hw.init = &(const struct clk_init_data) { 961 .name = "gcc_blsp1_qup5_spi_apps_clk", 962 .parent_hws = (const struct clk_hw *[]) { 963 &blsp1_qup5_spi_apps_clk_src.clkr.hw 964 }, 965 .num_parents = 1, 966 .flags = CLK_SET_RATE_PARENT, 967 .ops = &clk_branch2_ops, 968 }, 969 }, 970 }; 971 972 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 973 .halt_reg = 0x07024, 974 .clkr = { 975 .enable_reg = 0x07024, 976 .enable_mask = BIT(0), 977 .hw.init = &(const struct clk_init_data) { 978 .name = "gcc_blsp1_qup6_i2c_apps_clk", 979 .parent_hws = (const struct clk_hw *[]) { 980 &blsp1_qup6_i2c_apps_clk_src.clkr.hw 981 }, 982 .num_parents = 1, 983 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 984 .ops = &clk_branch2_ops, 985 }, 986 }, 987 }; 988 989 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 990 .halt_reg = 0x07020, 991 .clkr = { 992 .enable_reg = 0x07020, 993 .enable_mask = BIT(0), 994 .hw.init = &(const struct clk_init_data) { 995 .name = "gcc_blsp1_qup6_spi_apps_clk", 996 .parent_hws = (const struct clk_hw *[]) { 997 &blsp1_qup6_spi_apps_clk_src.clkr.hw 998 }, 999 .num_parents = 1, 1000 .flags = CLK_SET_RATE_PARENT, 1001 .ops = &clk_branch2_ops, 1002 }, 1003 }, 1004 }; 1005 1006 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1007 .halt_reg = 0x02040, 1008 .clkr = { 1009 .enable_reg = 0x02040, 1010 .enable_mask = BIT(0), 1011 .hw.init = &(const struct clk_init_data) { 1012 .name = "gcc_blsp1_uart1_apps_clk", 1013 .parent_hws = (const struct clk_hw *[]) { 1014 &blsp1_uart1_apps_clk_src.clkr.hw 1015 }, 1016 .num_parents = 1, 1017 .flags = CLK_SET_RATE_PARENT, 1018 .ops = &clk_branch2_ops, 1019 }, 1020 }, 1021 }; 1022 1023 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1024 .halt_reg = 0x03040, 1025 .clkr = { 1026 .enable_reg = 0x03040, 1027 .enable_mask = BIT(0), 1028 .hw.init = &(const struct clk_init_data) { 1029 .name = "gcc_blsp1_uart2_apps_clk", 1030 .parent_hws = (const struct clk_hw *[]) { 1031 &blsp1_uart2_apps_clk_src.clkr.hw 1032 }, 1033 .num_parents = 1, 1034 .flags = CLK_SET_RATE_PARENT, 1035 .ops = &clk_branch2_ops, 1036 }, 1037 }, 1038 }; 1039 1040 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1041 .halt_reg = 0x04054, 1042 .clkr = { 1043 .enable_reg = 0x04054, 1044 .enable_mask = BIT(0), 1045 .hw.init = &(const struct clk_init_data) { 1046 .name = "gcc_blsp1_uart3_apps_clk", 1047 .parent_hws = (const struct clk_hw *[]) { 1048 &blsp1_uart3_apps_clk_src.clkr.hw 1049 }, 1050 .num_parents = 1, 1051 .flags = CLK_SET_RATE_PARENT, 1052 .ops = &clk_branch2_ops, 1053 }, 1054 }, 1055 }; 1056 1057 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1058 .halt_reg = 0x05040, 1059 .clkr = { 1060 .enable_reg = 0x05040, 1061 .enable_mask = BIT(0), 1062 .hw.init = &(const struct clk_init_data) { 1063 .name = "gcc_blsp1_uart4_apps_clk", 1064 .parent_hws = (const struct clk_hw *[]) { 1065 &blsp1_uart4_apps_clk_src.clkr.hw 1066 }, 1067 .num_parents = 1, 1068 .flags = CLK_SET_RATE_PARENT, 1069 .ops = &clk_branch2_ops, 1070 }, 1071 }, 1072 }; 1073 1074 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1075 .halt_reg = 0x06040, 1076 .clkr = { 1077 .enable_reg = 0x06040, 1078 .enable_mask = BIT(0), 1079 .hw.init = &(const struct clk_init_data) { 1080 .name = "gcc_blsp1_uart5_apps_clk", 1081 .parent_hws = (const struct clk_hw *[]) { 1082 &blsp1_uart5_apps_clk_src.clkr.hw 1083 }, 1084 .num_parents = 1, 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1092 .halt_reg = 0x07040, 1093 .clkr = { 1094 .enable_reg = 0x07040, 1095 .enable_mask = BIT(0), 1096 .hw.init = &(const struct clk_init_data) { 1097 .name = "gcc_blsp1_uart6_apps_clk", 1098 .parent_hws = (const struct clk_hw *[]) { 1099 &blsp1_uart6_apps_clk_src.clkr.hw 1100 }, 1101 .num_parents = 1, 1102 .flags = CLK_SET_RATE_PARENT, 1103 .ops = &clk_branch2_ops, 1104 }, 1105 }, 1106 }; 1107 1108 static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = { 1109 F(240000000, P_GPLL4, 5, 0, 0), 1110 { } 1111 }; 1112 1113 static struct clk_rcg2 pcie0_axi_m_clk_src = { 1114 .cmd_rcgr = 0x28018, 1115 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1116 .hid_width = 5, 1117 .parent_map = gcc_xo_gpll0_gpll4_map, 1118 .clkr.hw.init = &(const struct clk_init_data) { 1119 .name = "pcie0_axi_m_clk_src", 1120 .parent_data = gcc_xo_gpll0_gpll4, 1121 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1122 .ops = &clk_rcg2_ops, 1123 }, 1124 }; 1125 1126 static struct clk_branch gcc_pcie0_axi_m_clk = { 1127 .halt_reg = 0x28038, 1128 .clkr = { 1129 .enable_reg = 0x28038, 1130 .enable_mask = BIT(0), 1131 .hw.init = &(const struct clk_init_data) { 1132 .name = "gcc_pcie0_axi_m_clk", 1133 .parent_hws = (const struct clk_hw *[]) { 1134 &pcie0_axi_m_clk_src.clkr.hw 1135 }, 1136 .num_parents = 1, 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_branch2_ops, 1139 }, 1140 }, 1141 }; 1142 1143 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = { 1144 .halt_reg = 0x2e07c, 1145 .clkr = { 1146 .enable_reg = 0x2e07c, 1147 .enable_mask = BIT(0), 1148 .hw.init = &(const struct clk_init_data) { 1149 .name = "gcc_anoc_pcie0_1lane_m_clk", 1150 .parent_hws = (const struct clk_hw *[]) { 1151 &pcie0_axi_m_clk_src.clkr.hw 1152 }, 1153 .num_parents = 1, 1154 .flags = CLK_SET_RATE_PARENT, 1155 .ops = &clk_branch2_ops, 1156 }, 1157 }, 1158 }; 1159 1160 static struct clk_rcg2 pcie1_axi_m_clk_src = { 1161 .cmd_rcgr = 0x29018, 1162 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1163 .hid_width = 5, 1164 .parent_map = gcc_xo_gpll0_gpll4_map, 1165 .clkr.hw.init = &(const struct clk_init_data) { 1166 .name = "pcie1_axi_m_clk_src", 1167 .parent_data = gcc_xo_gpll0_gpll4, 1168 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1169 .ops = &clk_rcg2_ops, 1170 }, 1171 }; 1172 1173 static struct clk_branch gcc_pcie1_axi_m_clk = { 1174 .halt_reg = 0x29038, 1175 .clkr = { 1176 .enable_reg = 0x29038, 1177 .enable_mask = BIT(0), 1178 .hw.init = &(const struct clk_init_data) { 1179 .name = "gcc_pcie1_axi_m_clk", 1180 .parent_hws = (const struct clk_hw *[]) { 1181 &pcie1_axi_m_clk_src.clkr.hw 1182 }, 1183 .num_parents = 1, 1184 .flags = CLK_SET_RATE_PARENT, 1185 .ops = &clk_branch2_ops, 1186 }, 1187 }, 1188 }; 1189 1190 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = { 1191 .halt_reg = 0x2e08c, 1192 .clkr = { 1193 .enable_reg = 0x2e08c, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(const struct clk_init_data) { 1196 .name = "gcc_anoc_pcie1_1lane_m_clk", 1197 .parent_hws = (const struct clk_hw *[]) { 1198 &pcie1_axi_m_clk_src.clkr.hw 1199 }, 1200 .num_parents = 1, 1201 .flags = CLK_SET_RATE_PARENT, 1202 .ops = &clk_branch2_ops, 1203 }, 1204 }, 1205 }; 1206 1207 static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = { 1208 F(342857143, P_GPLL4, 3.5, 0, 0), 1209 { } 1210 }; 1211 1212 static struct clk_rcg2 pcie2_axi_m_clk_src = { 1213 .cmd_rcgr = 0x2a018, 1214 .freq_tbl = ftbl_pcie2_axi_m_clk_src, 1215 .hid_width = 5, 1216 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, 1217 .clkr.hw.init = &(const struct clk_init_data) { 1218 .name = "pcie2_axi_m_clk_src", 1219 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, 1220 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), 1221 .ops = &clk_rcg2_ops, 1222 }, 1223 }; 1224 1225 static struct clk_branch gcc_pcie2_axi_m_clk = { 1226 .halt_reg = 0x2a038, 1227 .clkr = { 1228 .enable_reg = 0x2a038, 1229 .enable_mask = BIT(0), 1230 .hw.init = &(const struct clk_init_data) { 1231 .name = "gcc_pcie2_axi_m_clk", 1232 .parent_hws = (const struct clk_hw *[]) { 1233 &pcie2_axi_m_clk_src.clkr.hw 1234 }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 .ops = &clk_branch2_ops, 1238 }, 1239 }, 1240 }; 1241 1242 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = { 1243 .halt_reg = 0x2e080, 1244 .clkr = { 1245 .enable_reg = 0x2e080, 1246 .enable_mask = BIT(0), 1247 .hw.init = &(const struct clk_init_data) { 1248 .name = "gcc_anoc_pcie2_2lane_m_clk", 1249 .parent_hws = (const struct clk_hw *[]) { 1250 &pcie2_axi_m_clk_src.clkr.hw 1251 }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257 }; 1258 1259 static struct clk_rcg2 pcie3_axi_m_clk_src = { 1260 .cmd_rcgr = 0x2b018, 1261 .freq_tbl = ftbl_pcie2_axi_m_clk_src, 1262 .hid_width = 5, 1263 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, 1264 .clkr.hw.init = &(const struct clk_init_data) { 1265 .name = "pcie3_axi_m_clk_src", 1266 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, 1267 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), 1268 .ops = &clk_rcg2_ops, 1269 }, 1270 }; 1271 1272 static struct clk_branch gcc_pcie3_axi_m_clk = { 1273 .halt_reg = 0x2b038, 1274 .clkr = { 1275 .enable_reg = 0x2b038, 1276 .enable_mask = BIT(0), 1277 .hw.init = &(const struct clk_init_data) { 1278 .name = "gcc_pcie3_axi_m_clk", 1279 .parent_hws = (const struct clk_hw *[]) { 1280 &pcie3_axi_m_clk_src.clkr.hw 1281 }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT, 1284 .ops = &clk_branch2_ops, 1285 }, 1286 }, 1287 }; 1288 1289 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = { 1290 .halt_reg = 0x2e090, 1291 .clkr = { 1292 .enable_reg = 0x2e090, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(const struct clk_init_data) { 1295 .name = "gcc_anoc_pcie3_2lane_m_clk", 1296 .parent_hws = (const struct clk_hw *[]) { 1297 &pcie3_axi_m_clk_src.clkr.hw 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_rcg2 pcie0_axi_s_clk_src = { 1307 .cmd_rcgr = 0x28020, 1308 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1309 .hid_width = 5, 1310 .parent_map = gcc_xo_gpll0_gpll4_map, 1311 .clkr.hw.init = &(const struct clk_init_data) { 1312 .name = "pcie0_axi_s_clk_src", 1313 .parent_data = gcc_xo_gpll0_gpll4, 1314 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1315 .ops = &clk_rcg2_ops, 1316 }, 1317 }; 1318 1319 static struct clk_branch gcc_pcie0_axi_s_clk = { 1320 .halt_reg = 0x2803c, 1321 .clkr = { 1322 .enable_reg = 0x2803c, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(const struct clk_init_data) { 1325 .name = "gcc_pcie0_axi_s_clk", 1326 .parent_hws = (const struct clk_hw *[]) { 1327 &pcie0_axi_s_clk_src.clkr.hw 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { 1337 .halt_reg = 0x28040, 1338 .clkr = { 1339 .enable_reg = 0x28040, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(const struct clk_init_data) { 1342 .name = "gcc_pcie0_axi_s_bridge_clk", 1343 .parent_hws = (const struct clk_hw *[]) { 1344 &pcie0_axi_s_clk_src.clkr.hw 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = { 1354 .halt_reg = 0x2e048, 1355 .clkr = { 1356 .enable_reg = 0x2e048, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(const struct clk_init_data) { 1359 .name = "gcc_snoc_pcie0_1lane_s_clk", 1360 .parent_hws = (const struct clk_hw *[]) { 1361 &pcie0_axi_s_clk_src.clkr.hw 1362 }, 1363 .num_parents = 1, 1364 .flags = CLK_SET_RATE_PARENT, 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_rcg2 pcie1_axi_s_clk_src = { 1371 .cmd_rcgr = 0x29020, 1372 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1373 .hid_width = 5, 1374 .parent_map = gcc_xo_gpll0_gpll4_map, 1375 .clkr.hw.init = &(const struct clk_init_data) { 1376 .name = "pcie1_axi_s_clk_src", 1377 .parent_data = gcc_xo_gpll0_gpll4, 1378 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1379 .ops = &clk_rcg2_ops, 1380 }, 1381 }; 1382 1383 static struct clk_branch gcc_pcie1_axi_s_clk = { 1384 .halt_reg = 0x2903c, 1385 .clkr = { 1386 .enable_reg = 0x2903c, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(const struct clk_init_data) { 1389 .name = "gcc_pcie1_axi_s_clk", 1390 .parent_hws = (const struct clk_hw *[]) { 1391 &pcie1_axi_s_clk_src.clkr.hw 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { 1401 .halt_reg = 0x29040, 1402 .clkr = { 1403 .enable_reg = 0x29040, 1404 .enable_mask = BIT(0), 1405 .hw.init = &(const struct clk_init_data) { 1406 .name = "gcc_pcie1_axi_s_bridge_clk", 1407 .parent_hws = (const struct clk_hw *[]) { 1408 &pcie1_axi_s_clk_src.clkr.hw 1409 }, 1410 .num_parents = 1, 1411 .flags = CLK_SET_RATE_PARENT, 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415 }; 1416 1417 static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = { 1418 .halt_reg = 0x2e04c, 1419 .clkr = { 1420 .enable_reg = 0x2e04c, 1421 .enable_mask = BIT(0), 1422 .hw.init = &(const struct clk_init_data) { 1423 .name = "gcc_snoc_pcie1_1lane_s_clk", 1424 .parent_hws = (const struct clk_hw *[]) { 1425 &pcie1_axi_s_clk_src.clkr.hw 1426 }, 1427 .num_parents = 1, 1428 .flags = CLK_SET_RATE_PARENT, 1429 .ops = &clk_branch2_ops, 1430 }, 1431 }, 1432 }; 1433 1434 static struct clk_rcg2 pcie2_axi_s_clk_src = { 1435 .cmd_rcgr = 0x2a020, 1436 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1437 .hid_width = 5, 1438 .parent_map = gcc_xo_gpll0_gpll4_map, 1439 .clkr.hw.init = &(const struct clk_init_data) { 1440 .name = "pcie2_axi_s_clk_src", 1441 .parent_data = gcc_xo_gpll0_gpll4, 1442 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1443 .ops = &clk_rcg2_ops, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_pcie2_axi_s_clk = { 1448 .halt_reg = 0x2a03c, 1449 .clkr = { 1450 .enable_reg = 0x2a03c, 1451 .enable_mask = BIT(0), 1452 .hw.init = &(const struct clk_init_data) { 1453 .name = "gcc_pcie2_axi_s_clk", 1454 .parent_hws = (const struct clk_hw *[]) { 1455 &pcie2_axi_s_clk_src.clkr.hw 1456 }, 1457 .num_parents = 1, 1458 .flags = CLK_SET_RATE_PARENT, 1459 .ops = &clk_branch2_ops, 1460 }, 1461 }, 1462 }; 1463 1464 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = { 1465 .halt_reg = 0x2a040, 1466 .clkr = { 1467 .enable_reg = 0x2a040, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "gcc_pcie2_axi_s_bridge_clk", 1471 .parent_hws = (const struct clk_hw *[]) { 1472 &pcie2_axi_s_clk_src.clkr.hw 1473 }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = { 1482 .halt_reg = 0x2e050, 1483 .clkr = { 1484 .enable_reg = 0x2e050, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(const struct clk_init_data) { 1487 .name = "gcc_snoc_pcie2_2lane_s_clk", 1488 .parent_hws = (const struct clk_hw *[]) { 1489 &pcie2_axi_s_clk_src.clkr.hw 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_rcg2 pcie3_axi_s_clk_src = { 1499 .cmd_rcgr = 0x2b020, 1500 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1501 .hid_width = 5, 1502 .parent_map = gcc_xo_gpll0_gpll4_map, 1503 .clkr.hw.init = &(const struct clk_init_data) { 1504 .name = "pcie3_axi_s_clk_src", 1505 .parent_data = gcc_xo_gpll0_gpll4, 1506 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1507 .ops = &clk_rcg2_ops, 1508 }, 1509 }; 1510 1511 static struct clk_branch gcc_pcie3_axi_s_clk = { 1512 .halt_reg = 0x2b03c, 1513 .clkr = { 1514 .enable_reg = 0x2b03c, 1515 .enable_mask = BIT(0), 1516 .hw.init = &(const struct clk_init_data) { 1517 .name = "gcc_pcie3_axi_s_clk", 1518 .parent_hws = (const struct clk_hw *[]) { 1519 &pcie3_axi_s_clk_src.clkr.hw 1520 }, 1521 .num_parents = 1, 1522 .flags = CLK_SET_RATE_PARENT, 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526 }; 1527 1528 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = { 1529 .halt_reg = 0x2b040, 1530 .clkr = { 1531 .enable_reg = 0x2b040, 1532 .enable_mask = BIT(0), 1533 .hw.init = &(const struct clk_init_data) { 1534 .name = "gcc_pcie3_axi_s_bridge_clk", 1535 .parent_hws = (const struct clk_hw *[]) { 1536 &pcie3_axi_s_clk_src.clkr.hw 1537 }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { 1546 .halt_reg = 0x2e054, 1547 .clkr = { 1548 .enable_reg = 0x2e054, 1549 .enable_mask = BIT(0), 1550 .hw.init = &(const struct clk_init_data) { 1551 .name = "gcc_snoc_pcie3_2lane_s_clk", 1552 .parent_hws = (const struct clk_hw *[]) { 1553 &pcie3_axi_s_clk_src.clkr.hw 1554 }, 1555 .num_parents = 1, 1556 .flags = CLK_SET_RATE_PARENT, 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { 1563 .reg = 0x28064, 1564 .clkr = { 1565 .hw.init = &(const struct clk_init_data) { 1566 .name = "pcie0_pipe_clk_src", 1567 .parent_data = &(const struct clk_parent_data) { 1568 .index = DT_PCIE30_PHY0_PIPE_CLK, 1569 }, 1570 .num_parents = 1, 1571 .ops = &clk_regmap_phy_mux_ops, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { 1577 .reg = 0x29064, 1578 .clkr = { 1579 .hw.init = &(const struct clk_init_data) { 1580 .name = "pcie1_pipe_clk_src", 1581 .parent_data = &(const struct clk_parent_data) { 1582 .index = DT_PCIE30_PHY1_PIPE_CLK, 1583 }, 1584 .num_parents = 1, 1585 .ops = &clk_regmap_phy_mux_ops, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { 1591 .reg = 0x2a064, 1592 .clkr = { 1593 .hw.init = &(const struct clk_init_data) { 1594 .name = "pcie2_pipe_clk_src", 1595 .parent_data = &(const struct clk_parent_data) { 1596 .index = DT_PCIE30_PHY2_PIPE_CLK, 1597 }, 1598 .num_parents = 1, 1599 .ops = &clk_regmap_phy_mux_ops, 1600 }, 1601 }, 1602 }; 1603 1604 static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { 1605 .reg = 0x2b064, 1606 .clkr = { 1607 .hw.init = &(const struct clk_init_data) { 1608 .name = "pcie3_pipe_clk_src", 1609 .parent_data = &(const struct clk_parent_data) { 1610 .index = DT_PCIE30_PHY3_PIPE_CLK, 1611 }, 1612 .num_parents = 1, 1613 .ops = &clk_regmap_phy_mux_ops, 1614 }, 1615 }, 1616 }; 1617 1618 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { 1619 F(24000000, P_XO, 1, 0, 0), 1620 F(100000000, P_GPLL0, 8, 0, 0), 1621 { } 1622 }; 1623 1624 static struct clk_rcg2 pcie0_rchng_clk_src = { 1625 .cmd_rcgr = 0x28028, 1626 .freq_tbl = ftbl_pcie_rchng_clk_src, 1627 .hid_width = 5, 1628 .parent_map = gcc_xo_gpll0_map, 1629 .clkr.hw.init = &(const struct clk_init_data) { 1630 .name = "pcie0_rchng_clk_src", 1631 .parent_data = gcc_xo_gpll0, 1632 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1633 .ops = &clk_rcg2_ops, 1634 }, 1635 }; 1636 1637 static struct clk_branch gcc_pcie0_rchng_clk = { 1638 .halt_reg = 0x28028, 1639 .clkr = { 1640 .enable_reg = 0x28028, 1641 .enable_mask = BIT(1), 1642 .hw.init = &(const struct clk_init_data) { 1643 .name = "gcc_pcie0_rchng_clk", 1644 .parent_hws = (const struct clk_hw *[]) { 1645 &pcie0_rchng_clk_src.clkr.hw 1646 1647 }, 1648 .num_parents = 1, 1649 .flags = CLK_SET_RATE_PARENT, 1650 .ops = &clk_branch2_ops, 1651 }, 1652 }, 1653 }; 1654 1655 static struct clk_rcg2 pcie1_rchng_clk_src = { 1656 .cmd_rcgr = 0x29028, 1657 .freq_tbl = ftbl_pcie_rchng_clk_src, 1658 .hid_width = 5, 1659 .parent_map = gcc_xo_gpll0_map, 1660 .clkr.hw.init = &(const struct clk_init_data) { 1661 .name = "pcie1_rchng_clk_src", 1662 .parent_data = gcc_xo_gpll0, 1663 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1664 .ops = &clk_rcg2_ops, 1665 }, 1666 }; 1667 1668 static struct clk_branch gcc_pcie1_rchng_clk = { 1669 .halt_reg = 0x29028, 1670 .clkr = { 1671 .enable_reg = 0x29028, 1672 .enable_mask = BIT(1), 1673 .hw.init = &(const struct clk_init_data) { 1674 .name = "gcc_pcie1_rchng_clk", 1675 .parent_hws = (const struct clk_hw *[]) { 1676 &pcie1_rchng_clk_src.clkr.hw 1677 }, 1678 .num_parents = 1, 1679 .flags = CLK_SET_RATE_PARENT, 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_rcg2 pcie2_rchng_clk_src = { 1686 .cmd_rcgr = 0x2a028, 1687 .freq_tbl = ftbl_pcie_rchng_clk_src, 1688 .hid_width = 5, 1689 .parent_map = gcc_xo_gpll0_map, 1690 .clkr.hw.init = &(const struct clk_init_data) { 1691 .name = "pcie2_rchng_clk_src", 1692 .parent_data = gcc_xo_gpll0, 1693 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1694 .ops = &clk_rcg2_ops, 1695 }, 1696 }; 1697 1698 static struct clk_branch gcc_pcie2_rchng_clk = { 1699 .halt_reg = 0x2a028, 1700 .clkr = { 1701 .enable_reg = 0x2a028, 1702 .enable_mask = BIT(1), 1703 .hw.init = &(const struct clk_init_data) { 1704 .name = "gcc_pcie2_rchng_clk", 1705 .parent_hws = (const struct clk_hw *[]) { 1706 &pcie2_rchng_clk_src.clkr.hw 1707 }, 1708 .num_parents = 1, 1709 .flags = CLK_SET_RATE_PARENT, 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_rcg2 pcie3_rchng_clk_src = { 1716 .cmd_rcgr = 0x2b028, 1717 .freq_tbl = ftbl_pcie_rchng_clk_src, 1718 .hid_width = 5, 1719 .parent_map = gcc_xo_gpll0_map, 1720 .clkr.hw.init = &(const struct clk_init_data) { 1721 .name = "pcie3_rchng_clk_src", 1722 .parent_data = gcc_xo_gpll0, 1723 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1724 .ops = &clk_rcg2_ops, 1725 }, 1726 }; 1727 1728 static struct clk_branch gcc_pcie3_rchng_clk = { 1729 .halt_reg = 0x2b028, 1730 .clkr = { 1731 .enable_reg = 0x2b028, 1732 .enable_mask = BIT(1), 1733 .hw.init = &(const struct clk_init_data) { 1734 .name = "gcc_pcie3_rchng_clk", 1735 .parent_hws = (const struct clk_hw *[]) { 1736 &pcie3_rchng_clk_src.clkr.hw 1737 }, 1738 .num_parents = 1, 1739 .flags = CLK_SET_RATE_PARENT, 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 1746 F(20000000, P_GPLL0, 10, 1, 4), 1747 { } 1748 }; 1749 1750 static struct clk_rcg2 pcie_aux_clk_src = { 1751 .cmd_rcgr = 0x28004, 1752 .freq_tbl = ftbl_pcie_aux_clk_src, 1753 .mnd_width = 16, 1754 .hid_width = 5, 1755 .parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map, 1756 .clkr.hw.init = &(const struct clk_init_data) { 1757 .name = "pcie_aux_clk_src", 1758 .parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk, 1759 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk), 1760 .ops = &clk_rcg2_ops, 1761 }, 1762 }; 1763 1764 static struct clk_branch gcc_pcie0_aux_clk = { 1765 .halt_reg = 0x28034, 1766 .clkr = { 1767 .enable_reg = 0x28034, 1768 .enable_mask = BIT(0), 1769 .hw.init = &(const struct clk_init_data) { 1770 .name = "gcc_pcie0_aux_clk", 1771 .parent_hws = (const struct clk_hw *[]) { 1772 &pcie_aux_clk_src.clkr.hw 1773 }, 1774 .num_parents = 1, 1775 .flags = CLK_SET_RATE_PARENT, 1776 .ops = &clk_branch2_ops, 1777 }, 1778 }, 1779 }; 1780 1781 static struct clk_branch gcc_pcie1_aux_clk = { 1782 .halt_reg = 0x29034, 1783 .clkr = { 1784 .enable_reg = 0x29034, 1785 .enable_mask = BIT(0), 1786 .hw.init = &(const struct clk_init_data) { 1787 .name = "gcc_pcie1_aux_clk", 1788 .parent_hws = (const struct clk_hw *[]) { 1789 &pcie_aux_clk_src.clkr.hw 1790 }, 1791 .num_parents = 1, 1792 .flags = CLK_SET_RATE_PARENT, 1793 .ops = &clk_branch2_ops, 1794 }, 1795 }, 1796 }; 1797 1798 static struct clk_branch gcc_pcie2_aux_clk = { 1799 .halt_reg = 0x2a034, 1800 .clkr = { 1801 .enable_reg = 0x2a034, 1802 .enable_mask = BIT(0), 1803 .hw.init = &(const struct clk_init_data) { 1804 .name = "gcc_pcie2_aux_clk", 1805 .parent_hws = (const struct clk_hw *[]) { 1806 &pcie_aux_clk_src.clkr.hw 1807 }, 1808 .num_parents = 1, 1809 .flags = CLK_SET_RATE_PARENT, 1810 .ops = &clk_branch2_ops, 1811 }, 1812 }, 1813 }; 1814 1815 static struct clk_branch gcc_pcie3_aux_clk = { 1816 .halt_reg = 0x2b034, 1817 .clkr = { 1818 .enable_reg = 0x2b034, 1819 .enable_mask = BIT(0), 1820 .hw.init = &(const struct clk_init_data) { 1821 .name = "gcc_pcie3_aux_clk", 1822 .parent_hws = (const struct clk_hw *[]) { 1823 &pcie_aux_clk_src.clkr.hw 1824 }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT, 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static const struct freq_tbl ftbl_usb_aux_clk_src[] = { 1833 F(24000000, P_XO, 1, 0, 0), 1834 { } 1835 }; 1836 1837 static struct clk_rcg2 usb0_aux_clk_src = { 1838 .cmd_rcgr = 0x2c018, 1839 .freq_tbl = ftbl_usb_aux_clk_src, 1840 .mnd_width = 16, 1841 .hid_width = 5, 1842 .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, 1843 .clkr.hw.init = &(const struct clk_init_data) { 1844 .name = "usb0_aux_clk_src", 1845 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, 1846 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), 1847 .ops = &clk_rcg2_ops, 1848 }, 1849 }; 1850 1851 static struct clk_branch gcc_usb0_aux_clk = { 1852 .halt_reg = 0x2c048, 1853 .clkr = { 1854 .enable_reg = 0x2c048, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(const struct clk_init_data) { 1857 .name = "gcc_usb0_aux_clk", 1858 .parent_hws = (const struct clk_hw *[]) { 1859 &usb0_aux_clk_src.clkr.hw 1860 }, 1861 .num_parents = 1, 1862 .flags = CLK_SET_RATE_PARENT, 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static const struct freq_tbl ftbl_usb0_master_clk_src[] = { 1869 F(100000000, P_GPLL0, 8, 0, 0), 1870 F(200000000, P_GPLL0, 4, 0, 0), 1871 { } 1872 }; 1873 1874 static struct clk_rcg2 usb0_master_clk_src = { 1875 .cmd_rcgr = 0x2c004, 1876 .freq_tbl = ftbl_usb0_master_clk_src, 1877 .mnd_width = 8, 1878 .hid_width = 5, 1879 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, 1880 .clkr.hw.init = &(const struct clk_init_data) { 1881 .name = "usb0_master_clk_src", 1882 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, 1883 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), 1884 .ops = &clk_rcg2_ops, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_usb0_master_clk = { 1889 .halt_reg = 0x2c044, 1890 .clkr = { 1891 .enable_reg = 0x2c044, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(const struct clk_init_data) { 1894 .name = "gcc_usb0_master_clk", 1895 .parent_hws = (const struct clk_hw *[]) { 1896 &usb0_master_clk_src.clkr.hw 1897 }, 1898 .num_parents = 1, 1899 .flags = CLK_SET_RATE_PARENT, 1900 .ops = &clk_branch2_ops, 1901 }, 1902 }, 1903 }; 1904 1905 static struct clk_branch gcc_snoc_usb_clk = { 1906 .halt_reg = 0x2e058, 1907 .clkr = { 1908 .enable_reg = 0x2e058, 1909 .enable_mask = BIT(0), 1910 .hw.init = &(const struct clk_init_data) { 1911 .name = "gcc_snoc_usb_clk", 1912 .parent_hws = (const struct clk_hw *[]) { 1913 &usb0_master_clk_src.clkr.hw 1914 }, 1915 .num_parents = 1, 1916 .flags = CLK_SET_RATE_PARENT, 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch gcc_anoc_usb_axi_clk = { 1923 .halt_reg = 0x2e084, 1924 .clkr = { 1925 .enable_reg = 0x2e084, 1926 .enable_mask = BIT(0), 1927 .hw.init = &(const struct clk_init_data) { 1928 .name = "gcc_anoc_usb_axi_clk", 1929 .parent_hws = (const struct clk_hw *[]) { 1930 &usb0_master_clk_src.clkr.hw 1931 }, 1932 .num_parents = 1, 1933 .flags = CLK_SET_RATE_PARENT, 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = { 1940 F(24000000, P_XO, 1, 0, 0), 1941 F(60000000, P_GPLL4, 10, 1, 2), 1942 { } 1943 }; 1944 1945 static struct clk_rcg2 usb0_mock_utmi_clk_src = { 1946 .cmd_rcgr = 0x2c02c, 1947 .freq_tbl = ftbl_usb0_mock_utmi_clk_src, 1948 .mnd_width = 8, 1949 .hid_width = 5, 1950 .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map, 1951 .clkr.hw.init = &(const struct clk_init_data) { 1952 .name = "usb0_mock_utmi_clk_src", 1953 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, 1954 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), 1955 .ops = &clk_rcg2_ops, 1956 }, 1957 }; 1958 1959 static struct clk_regmap_div usb0_mock_utmi_div_clk_src = { 1960 .reg = 0x2c040, 1961 .shift = 0, 1962 .width = 2, 1963 .clkr.hw.init = &(const struct clk_init_data) { 1964 .name = "usb0_mock_utmi_div_clk_src", 1965 .parent_data = &(const struct clk_parent_data) { 1966 .hw = &usb0_mock_utmi_clk_src.clkr.hw, 1967 }, 1968 .num_parents = 1, 1969 .flags = CLK_SET_RATE_PARENT, 1970 .ops = &clk_regmap_div_ro_ops, 1971 }, 1972 }; 1973 1974 static struct clk_branch gcc_usb0_mock_utmi_clk = { 1975 .halt_reg = 0x2c04c, 1976 .clkr = { 1977 .enable_reg = 0x2c04c, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(const struct clk_init_data) { 1980 .name = "gcc_usb0_mock_utmi_clk", 1981 .parent_hws = (const struct clk_hw *[]) { 1982 &usb0_mock_utmi_div_clk_src.clkr.hw 1983 }, 1984 .num_parents = 1, 1985 .flags = CLK_SET_RATE_PARENT, 1986 .ops = &clk_branch2_ops, 1987 }, 1988 }, 1989 }; 1990 1991 static struct clk_regmap_mux usb0_pipe_clk_src = { 1992 .reg = 0x2C074, 1993 .shift = 8, 1994 .width = 2, 1995 .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, 1996 .clkr = { 1997 .hw.init = &(const struct clk_init_data) { 1998 .name = "usb0_pipe_clk_src", 1999 .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, 2000 .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo), 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_regmap_mux_closest_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_usb0_pipe_clk = { 2008 .halt_reg = 0x2c054, 2009 .halt_check = BRANCH_HALT_DELAY, 2010 .clkr = { 2011 .enable_reg = 0x2c054, 2012 .enable_mask = BIT(0), 2013 .hw.init = &(const struct clk_init_data){ 2014 .name = "gcc_usb0_pipe_clk", 2015 .parent_hws = (const struct clk_hw *[]) { 2016 &usb0_pipe_clk_src.clkr.hw 2017 }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT, 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_usb0_sleep_clk = { 2026 .halt_reg = 0x2c058, 2027 .clkr = { 2028 .enable_reg = 0x2c058, 2029 .enable_mask = BIT(0), 2030 .hw.init = &(const struct clk_init_data){ 2031 .name = "gcc_usb0_sleep_clk", 2032 .parent_hws = (const struct clk_hw *[]) { 2033 &gcc_sleep_clk_src.clkr.hw 2034 }, 2035 .num_parents = 1, 2036 .flags = CLK_SET_RATE_PARENT, 2037 .ops = &clk_branch2_ops, 2038 }, 2039 }, 2040 }; 2041 2042 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { 2043 F(144000, P_XO, 16, 12, 125), 2044 F(400000, P_XO, 12, 1, 5), 2045 F(24000000, P_GPLL2, 12, 1, 4), 2046 F(48000000, P_GPLL2, 12, 1, 2), 2047 F(96000000, P_GPLL2, 12, 0, 0), 2048 F(177777778, P_GPLL0, 4.5, 0, 0), 2049 F(192000000, P_GPLL2, 6, 0, 0), 2050 F(384000000, P_GPLL2, 3, 0, 0), 2051 F(400000000, P_GPLL0, 2, 0, 0), 2052 { } 2053 }; 2054 2055 static struct clk_rcg2 sdcc1_apps_clk_src = { 2056 .cmd_rcgr = 0x33004, 2057 .freq_tbl = ftbl_sdcc_apps_clk_src, 2058 .mnd_width = 8, 2059 .hid_width = 5, 2060 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, 2061 .clkr.hw.init = &(const struct clk_init_data) { 2062 .name = "sdcc1_apps_clk_src", 2063 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, 2064 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), 2065 .ops = &clk_rcg2_floor_ops, 2066 }, 2067 }; 2068 2069 static struct clk_branch gcc_sdcc1_apps_clk = { 2070 .halt_reg = 0x3302c, 2071 .clkr = { 2072 .enable_reg = 0x3302c, 2073 .enable_mask = BIT(0), 2074 .hw.init = &(const struct clk_init_data) { 2075 .name = "gcc_sdcc1_apps_clk", 2076 .parent_hws = (const struct clk_hw *[]) { 2077 &sdcc1_apps_clk_src.clkr.hw 2078 }, 2079 .num_parents = 1, 2080 .flags = CLK_SET_RATE_PARENT, 2081 .ops = &clk_branch2_ops, 2082 }, 2083 }, 2084 }; 2085 2086 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = { 2087 F(150000000, P_GPLL4, 8, 0, 0), 2088 F(300000000, P_GPLL4, 4, 0, 0), 2089 }; 2090 2091 static struct clk_rcg2 sdcc1_ice_core_clk_src = { 2092 .cmd_rcgr = 0x33018, 2093 .freq_tbl = ftbl_sdcc_ice_core_clk_src, 2094 .mnd_width = 8, 2095 .hid_width = 5, 2096 .parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map, 2097 .clkr.hw.init = &(const struct clk_init_data) { 2098 .name = "sdcc1_ice_core_clk_src", 2099 .parent_data = gcc_xo_gpll0_gpll4_gpll0_div2, 2100 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2), 2101 .ops = &clk_rcg2_ops, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2106 .halt_reg = 0x33030, 2107 .clkr = { 2108 .enable_reg = 0x33030, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(const struct clk_init_data) { 2111 .name = "gcc_sdcc1_ice_core_clk", 2112 .parent_hws = (const struct clk_hw *[]) { 2113 &sdcc1_ice_core_clk_src.clkr.hw 2114 }, 2115 .num_parents = 1, 2116 .flags = CLK_SET_RATE_PARENT, 2117 .ops = &clk_branch2_ops, 2118 }, 2119 }, 2120 }; 2121 2122 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { 2123 F(24000000, P_XO, 1, 0, 0), 2124 F(50000000, P_GPLL0, 16, 0, 0), 2125 F(80000000, P_GPLL0, 10, 0, 0), 2126 F(100000000, P_GPLL0, 8, 0, 0), 2127 { } 2128 }; 2129 2130 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 2131 .cmd_rcgr = 0x31004, 2132 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, 2133 .hid_width = 5, 2134 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 2135 .clkr.hw.init = &(const struct clk_init_data) { 2136 .name = "pcnoc_bfdcd_clk_src", 2137 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 2138 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 2139 .flags = CLK_IS_CRITICAL, 2140 .ops = &clk_rcg2_ops, 2141 }, 2142 }; 2143 2144 static struct clk_branch gcc_crypto_axi_clk = { 2145 .halt_reg = 0x16010, 2146 .clkr = { 2147 .enable_reg = 0x16010, 2148 .enable_mask = BIT(0), 2149 .hw.init = &(const struct clk_init_data) { 2150 .name = "gcc_crypto_axi_clk", 2151 .parent_hws = (const struct clk_hw *[]) { 2152 &pcnoc_bfdcd_clk_src.clkr.hw }, 2153 .num_parents = 1, 2154 .flags = CLK_SET_RATE_PARENT, 2155 .ops = &clk_branch2_ops, 2156 }, 2157 }, 2158 }; 2159 2160 static struct clk_branch gcc_crypto_ahb_clk = { 2161 .halt_reg = 0x16014, 2162 .clkr = { 2163 .enable_reg = 0x16014, 2164 .enable_mask = BIT(0), 2165 .hw.init = &(const struct clk_init_data) { 2166 .name = "gcc_crypto_ahb_clk", 2167 .parent_hws = (const struct clk_hw *[]) { 2168 &pcnoc_bfdcd_clk_src.clkr.hw }, 2169 .num_parents = 1, 2170 .flags = CLK_SET_RATE_PARENT, 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_branch gcc_nsscfg_clk = { 2177 .halt_reg = 0x1702c, 2178 .clkr = { 2179 .enable_reg = 0x1702c, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(const struct clk_init_data) { 2182 .name = "gcc_nsscfg_clk", 2183 .parent_hws = (const struct clk_hw *[]) { 2184 &pcnoc_bfdcd_clk_src.clkr.hw 2185 }, 2186 .num_parents = 1, 2187 .flags = CLK_SET_RATE_PARENT, 2188 .ops = &clk_branch2_ops, 2189 }, 2190 }, 2191 }; 2192 2193 static struct clk_branch gcc_nssnoc_nsscc_clk = { 2194 .halt_reg = 0x17030, 2195 .clkr = { 2196 .enable_reg = 0x17030, 2197 .enable_mask = BIT(0), 2198 .hw.init = &(const struct clk_init_data) { 2199 .name = "gcc_nssnoc_nsscc_clk", 2200 .parent_hws = (const struct clk_hw *[]) { 2201 &pcnoc_bfdcd_clk_src.clkr.hw 2202 }, 2203 .num_parents = 1, 2204 .flags = CLK_SET_RATE_PARENT, 2205 .ops = &clk_branch2_ops, 2206 }, 2207 }, 2208 }; 2209 2210 static struct clk_branch gcc_nsscc_clk = { 2211 .halt_reg = 0x17034, 2212 .clkr = { 2213 .enable_reg = 0x17034, 2214 .enable_mask = BIT(0), 2215 .hw.init = &(const struct clk_init_data) { 2216 .name = "gcc_nsscc_clk", 2217 .parent_hws = (const struct clk_hw *[]) { 2218 &pcnoc_bfdcd_clk_src.clkr.hw 2219 }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { 2228 .halt_reg = 0x17080, 2229 .clkr = { 2230 .enable_reg = 0x17080, 2231 .enable_mask = BIT(0), 2232 .hw.init = &(const struct clk_init_data) { 2233 .name = "gcc_nssnoc_pcnoc_1_clk", 2234 .parent_hws = (const struct clk_hw *[]) { 2235 &pcnoc_bfdcd_clk_src.clkr.hw 2236 }, 2237 .num_parents = 1, 2238 .flags = CLK_SET_RATE_PARENT, 2239 .ops = &clk_branch2_ops, 2240 }, 2241 }, 2242 }; 2243 2244 static struct clk_branch gcc_qdss_dap_ahb_clk = { 2245 .halt_reg = 0x2d064, 2246 .clkr = { 2247 .enable_reg = 0x2d064, 2248 .enable_mask = BIT(0), 2249 .hw.init = &(const struct clk_init_data) { 2250 .name = "gcc_qdss_dap_ahb_clk", 2251 .parent_hws = (const struct clk_hw *[]) { 2252 &pcnoc_bfdcd_clk_src.clkr.hw 2253 }, 2254 .num_parents = 1, 2255 .flags = CLK_SET_RATE_PARENT, 2256 .ops = &clk_branch2_ops, 2257 }, 2258 }, 2259 }; 2260 2261 static struct clk_branch gcc_qdss_cfg_ahb_clk = { 2262 .halt_reg = 0x2d068, 2263 .clkr = { 2264 .enable_reg = 0x2d068, 2265 .enable_mask = BIT(0), 2266 .hw.init = &(const struct clk_init_data) { 2267 .name = "gcc_qdss_cfg_ahb_clk", 2268 .parent_hws = (const struct clk_hw *[]) { 2269 &pcnoc_bfdcd_clk_src.clkr.hw 2270 }, 2271 .num_parents = 1, 2272 .flags = CLK_SET_RATE_PARENT, 2273 .ops = &clk_branch2_ops, 2274 }, 2275 }, 2276 }; 2277 2278 static struct clk_branch gcc_qpic_ahb_clk = { 2279 .halt_reg = 0x32010, 2280 .clkr = { 2281 .enable_reg = 0x32010, 2282 .enable_mask = BIT(0), 2283 .hw.init = &(const struct clk_init_data) { 2284 .name = "gcc_qpic_ahb_clk", 2285 .parent_hws = (const struct clk_hw *[]) { 2286 &pcnoc_bfdcd_clk_src.clkr.hw 2287 }, 2288 .num_parents = 1, 2289 .flags = CLK_SET_RATE_PARENT, 2290 .ops = &clk_branch2_ops, 2291 }, 2292 }, 2293 }; 2294 2295 static struct clk_branch gcc_qpic_clk = { 2296 .halt_reg = 0x32014, 2297 .clkr = { 2298 .enable_reg = 0x32014, 2299 .enable_mask = BIT(0), 2300 .hw.init = &(const struct clk_init_data) { 2301 .name = "gcc_qpic_clk", 2302 .parent_hws = (const struct clk_hw *[]) { 2303 &pcnoc_bfdcd_clk_src.clkr.hw 2304 }, 2305 .num_parents = 1, 2306 .flags = CLK_SET_RATE_PARENT, 2307 .ops = &clk_branch2_ops, 2308 }, 2309 }, 2310 }; 2311 2312 static struct clk_branch gcc_blsp1_ahb_clk = { 2313 .halt_reg = 0x01004, 2314 .halt_check = BRANCH_HALT_VOTED, 2315 .clkr = { 2316 .enable_reg = 0x0b004, 2317 .enable_mask = BIT(4), 2318 .hw.init = &(const struct clk_init_data) { 2319 .name = "gcc_blsp1_ahb_clk", 2320 .parent_hws = (const struct clk_hw *[]) { 2321 &pcnoc_bfdcd_clk_src.clkr.hw 2322 }, 2323 .num_parents = 1, 2324 .flags = CLK_SET_RATE_PARENT, 2325 .ops = &clk_branch2_ops, 2326 }, 2327 }, 2328 }; 2329 2330 static struct clk_branch gcc_mdio_ahb_clk = { 2331 .halt_reg = 0x17040, 2332 .clkr = { 2333 .enable_reg = 0x17040, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(const struct clk_init_data) { 2336 .name = "gcc_mdio_ahb_clk", 2337 .parent_hws = (const struct clk_hw *[]) { 2338 &pcnoc_bfdcd_clk_src.clkr.hw 2339 }, 2340 .num_parents = 1, 2341 .flags = CLK_SET_RATE_PARENT, 2342 .ops = &clk_branch2_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch gcc_prng_ahb_clk = { 2348 .halt_reg = 0x13024, 2349 .halt_check = BRANCH_HALT_VOTED, 2350 .clkr = { 2351 .enable_reg = 0x0b004, 2352 .enable_mask = BIT(10), 2353 .hw.init = &(const struct clk_init_data) { 2354 .name = "gcc_prng_ahb_clk", 2355 .parent_hws = (const struct clk_hw *[]) { 2356 &pcnoc_bfdcd_clk_src.clkr.hw 2357 }, 2358 .num_parents = 1, 2359 .flags = CLK_SET_RATE_PARENT, 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363 }; 2364 2365 static struct clk_branch gcc_uniphy0_ahb_clk = { 2366 .halt_reg = 0x1704c, 2367 .clkr = { 2368 .enable_reg = 0x1704c, 2369 .enable_mask = BIT(0), 2370 .hw.init = &(const struct clk_init_data) { 2371 .name = "gcc_uniphy0_ahb_clk", 2372 .parent_hws = (const struct clk_hw *[]) { 2373 &pcnoc_bfdcd_clk_src.clkr.hw 2374 }, 2375 .num_parents = 1, 2376 .flags = CLK_SET_RATE_PARENT, 2377 .ops = &clk_branch2_ops, 2378 }, 2379 }, 2380 }; 2381 2382 static struct clk_branch gcc_uniphy1_ahb_clk = { 2383 .halt_reg = 0x1705c, 2384 .clkr = { 2385 .enable_reg = 0x1705c, 2386 .enable_mask = BIT(0), 2387 .hw.init = &(const struct clk_init_data) { 2388 .name = "gcc_uniphy1_ahb_clk", 2389 .parent_hws = (const struct clk_hw *[]) { 2390 &pcnoc_bfdcd_clk_src.clkr.hw 2391 }, 2392 .num_parents = 1, 2393 .flags = CLK_SET_RATE_PARENT, 2394 .ops = &clk_branch2_ops, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch gcc_uniphy2_ahb_clk = { 2400 .halt_reg = 0x1706c, 2401 .clkr = { 2402 .enable_reg = 0x1706c, 2403 .enable_mask = BIT(0), 2404 .hw.init = &(const struct clk_init_data) { 2405 .name = "gcc_uniphy2_ahb_clk", 2406 .parent_hws = (const struct clk_hw *[]) { 2407 &pcnoc_bfdcd_clk_src.clkr.hw 2408 }, 2409 .num_parents = 1, 2410 .flags = CLK_SET_RATE_PARENT, 2411 .ops = &clk_branch2_ops, 2412 }, 2413 }, 2414 }; 2415 2416 static struct clk_branch gcc_cmn_12gpll_ahb_clk = { 2417 .halt_reg = 0x3a004, 2418 .clkr = { 2419 .enable_reg = 0x3a004, 2420 .enable_mask = BIT(0), 2421 .hw.init = &(const struct clk_init_data) { 2422 .name = "gcc_cmn_12gpll_ahb_clk", 2423 .parent_hws = (const struct clk_hw *[]) { 2424 &pcnoc_bfdcd_clk_src.clkr.hw 2425 }, 2426 .num_parents = 1, 2427 .flags = CLK_SET_RATE_PARENT, 2428 .ops = &clk_branch2_ops, 2429 }, 2430 }, 2431 }; 2432 2433 static struct clk_branch gcc_cmn_12gpll_apu_clk = { 2434 .halt_reg = 0x3a00c, 2435 .clkr = { 2436 .enable_reg = 0x3a00c, 2437 .enable_mask = BIT(0), 2438 .hw.init = &(const struct clk_init_data) { 2439 .name = "gcc_cmn_12gpll_apu_clk", 2440 .parent_hws = (const struct clk_hw *[]) { 2441 &pcnoc_bfdcd_clk_src.clkr.hw 2442 }, 2443 .num_parents = 1, 2444 .flags = CLK_SET_RATE_PARENT, 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_pcie0_ahb_clk = { 2451 .halt_reg = 0x28030, 2452 .clkr = { 2453 .enable_reg = 0x28030, 2454 .enable_mask = BIT(0), 2455 .hw.init = &(const struct clk_init_data) { 2456 .name = "gcc_pcie0_ahb_clk", 2457 .parent_hws = (const struct clk_hw *[]) { 2458 &pcnoc_bfdcd_clk_src.clkr.hw 2459 }, 2460 .num_parents = 1, 2461 .flags = CLK_SET_RATE_PARENT, 2462 .ops = &clk_branch2_ops, 2463 }, 2464 }, 2465 }; 2466 2467 static struct clk_branch gcc_pcie1_ahb_clk = { 2468 .halt_reg = 0x29030, 2469 .clkr = { 2470 .enable_reg = 0x29030, 2471 .enable_mask = BIT(0), 2472 .hw.init = &(const struct clk_init_data) { 2473 .name = "gcc_pcie1_ahb_clk", 2474 .parent_hws = (const struct clk_hw *[]) { 2475 &pcnoc_bfdcd_clk_src.clkr.hw 2476 }, 2477 .num_parents = 1, 2478 .flags = CLK_SET_RATE_PARENT, 2479 .ops = &clk_branch2_ops, 2480 }, 2481 }, 2482 }; 2483 2484 static struct clk_branch gcc_pcie2_ahb_clk = { 2485 .halt_reg = 0x2a030, 2486 .clkr = { 2487 .enable_reg = 0x2a030, 2488 .enable_mask = BIT(0), 2489 .hw.init = &(const struct clk_init_data) { 2490 .name = "gcc_pcie2_ahb_clk", 2491 .parent_hws = (const struct clk_hw *[]) { 2492 &pcnoc_bfdcd_clk_src.clkr.hw 2493 }, 2494 .num_parents = 1, 2495 .flags = CLK_SET_RATE_PARENT, 2496 .ops = &clk_branch2_ops, 2497 }, 2498 }, 2499 }; 2500 2501 static struct clk_branch gcc_pcie3_ahb_clk = { 2502 .halt_reg = 0x2b030, 2503 .clkr = { 2504 .enable_reg = 0x2b030, 2505 .enable_mask = BIT(0), 2506 .hw.init = &(const struct clk_init_data) { 2507 .name = "gcc_pcie3_ahb_clk", 2508 .parent_hws = (const struct clk_hw *[]) { 2509 &pcnoc_bfdcd_clk_src.clkr.hw 2510 }, 2511 .num_parents = 1, 2512 .flags = CLK_SET_RATE_PARENT, 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516 }; 2517 2518 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 2519 .halt_reg = 0x2c05c, 2520 .clkr = { 2521 .enable_reg = 0x2c05c, 2522 .enable_mask = BIT(0), 2523 .hw.init = &(const struct clk_init_data) { 2524 .name = "gcc_usb0_phy_cfg_ahb_clk", 2525 .parent_hws = (const struct clk_hw *[]) { 2526 &pcnoc_bfdcd_clk_src.clkr.hw 2527 }, 2528 .num_parents = 1, 2529 .flags = CLK_SET_RATE_PARENT, 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_sdcc1_ahb_clk = { 2536 .halt_reg = 0x33034, 2537 .clkr = { 2538 .enable_reg = 0x33034, 2539 .enable_mask = BIT(0), 2540 .hw.init = &(const struct clk_init_data) { 2541 .name = "gcc_sdcc1_ahb_clk", 2542 .parent_hws = (const struct clk_hw *[]) { 2543 &pcnoc_bfdcd_clk_src.clkr.hw 2544 }, 2545 .num_parents = 1, 2546 .flags = CLK_SET_RATE_PARENT, 2547 .ops = &clk_branch2_ops, 2548 }, 2549 }, 2550 }; 2551 2552 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { 2553 F(24000000, P_XO, 1, 0, 0), 2554 F(133333333, P_GPLL0, 6, 0, 0), 2555 F(200000000, P_GPLL0, 4, 0, 0), 2556 F(342850000, P_GPLL4, 3.5, 0, 0), 2557 { } 2558 }; 2559 2560 static struct clk_rcg2 system_noc_bfdcd_clk_src = { 2561 .cmd_rcgr = 0x2e004, 2562 .freq_tbl = ftbl_system_noc_bfdcd_clk_src, 2563 .hid_width = 5, 2564 .parent_map = gcc_xo_gpll0_gpll4_map, 2565 .clkr.hw.init = &(const struct clk_init_data) { 2566 .name = "system_noc_bfdcd_clk_src", 2567 .parent_data = gcc_xo_gpll0_gpll4, 2568 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 2569 .flags = CLK_IS_CRITICAL, 2570 .ops = &clk_rcg2_ops, 2571 }, 2572 }; 2573 2574 static struct clk_branch gcc_q6ss_boot_clk = { 2575 .halt_reg = 0x25080, 2576 .halt_check = BRANCH_HALT_SKIP, 2577 .clkr = { 2578 .enable_reg = 0x25080, 2579 .enable_mask = BIT(0), 2580 .hw.init = &(const struct clk_init_data) { 2581 .name = "gcc_q6ss_boot_clk", 2582 .parent_hws = (const struct clk_hw *[]) { 2583 &system_noc_bfdcd_clk_src.clkr.hw 2584 }, 2585 .num_parents = 1, 2586 .flags = CLK_SET_RATE_PARENT, 2587 .ops = &clk_branch2_ops, 2588 }, 2589 }, 2590 }; 2591 2592 static struct clk_branch gcc_nssnoc_snoc_clk = { 2593 .halt_reg = 0x17028, 2594 .clkr = { 2595 .enable_reg = 0x17028, 2596 .enable_mask = BIT(0), 2597 .hw.init = &(const struct clk_init_data) { 2598 .name = "gcc_nssnoc_snoc_clk", 2599 .parent_hws = (const struct clk_hw *[]) { 2600 &system_noc_bfdcd_clk_src.clkr.hw 2601 }, 2602 .num_parents = 1, 2603 .flags = CLK_SET_RATE_PARENT, 2604 .ops = &clk_branch2_ops, 2605 }, 2606 }, 2607 }; 2608 2609 static struct clk_branch gcc_nssnoc_snoc_1_clk = { 2610 .halt_reg = 0x1707c, 2611 .clkr = { 2612 .enable_reg = 0x1707c, 2613 .enable_mask = BIT(0), 2614 .hw.init = &(const struct clk_init_data) { 2615 .name = "gcc_nssnoc_snoc_1_clk", 2616 .parent_hws = (const struct clk_hw *[]) { 2617 &system_noc_bfdcd_clk_src.clkr.hw 2618 }, 2619 .num_parents = 1, 2620 .flags = CLK_SET_RATE_PARENT, 2621 .ops = &clk_branch2_ops, 2622 }, 2623 }, 2624 }; 2625 2626 static struct clk_branch gcc_qdss_etr_usb_clk = { 2627 .halt_reg = 0x2d060, 2628 .clkr = { 2629 .enable_reg = 0x2d060, 2630 .enable_mask = BIT(0), 2631 .hw.init = &(const struct clk_init_data) { 2632 .name = "gcc_qdss_etr_usb_clk", 2633 .parent_hws = (const struct clk_hw *[]) { 2634 &system_noc_bfdcd_clk_src.clkr.hw 2635 }, 2636 .num_parents = 1, 2637 .flags = CLK_SET_RATE_PARENT, 2638 .ops = &clk_branch2_ops, 2639 }, 2640 }, 2641 }; 2642 2643 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = { 2644 F(24000000, P_XO, 1, 0, 0), 2645 F(133333333, P_GPLL0, 6, 0, 0), 2646 { } 2647 }; 2648 2649 static struct clk_rcg2 wcss_ahb_clk_src = { 2650 .cmd_rcgr = 0x25030, 2651 .freq_tbl = ftbl_wcss_ahb_clk_src, 2652 .hid_width = 5, 2653 .parent_map = gcc_xo_gpll0_map, 2654 .clkr.hw.init = &(const struct clk_init_data) { 2655 .name = "wcss_ahb_clk_src", 2656 .parent_data = gcc_xo_gpll0, 2657 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 2658 .ops = &clk_rcg2_ops, 2659 }, 2660 }; 2661 2662 static struct clk_branch gcc_q6_ahb_clk = { 2663 .halt_reg = 0x25014, 2664 .clkr = { 2665 .enable_reg = 0x25014, 2666 .enable_mask = BIT(0), 2667 .hw.init = &(const struct clk_init_data) { 2668 .name = "gcc_q6_ahb_clk", 2669 .parent_hws = (const struct clk_hw *[]) { 2670 &wcss_ahb_clk_src.clkr.hw 2671 }, 2672 .num_parents = 1, 2673 .flags = CLK_SET_RATE_PARENT, 2674 .ops = &clk_branch2_ops, 2675 }, 2676 }, 2677 }; 2678 2679 static struct clk_branch gcc_q6_ahb_s_clk = { 2680 .halt_reg = 0x25018, 2681 .clkr = { 2682 .enable_reg = 0x25018, 2683 .enable_mask = BIT(0), 2684 .hw.init = &(const struct clk_init_data) { 2685 .name = "gcc_q6_ahb_s_clk", 2686 .parent_hws = (const struct clk_hw *[]) { 2687 &wcss_ahb_clk_src.clkr.hw 2688 }, 2689 .num_parents = 1, 2690 .flags = CLK_SET_RATE_PARENT, 2691 .ops = &clk_branch2_ops, 2692 }, 2693 }, 2694 }; 2695 2696 static struct clk_branch gcc_wcss_ecahb_clk = { 2697 .halt_reg = 0x25058, 2698 .clkr = { 2699 .enable_reg = 0x25058, 2700 .enable_mask = BIT(0), 2701 .hw.init = &(const struct clk_init_data) { 2702 .name = "gcc_wcss_ecahb_clk", 2703 .parent_hws = (const struct clk_hw *[]) { 2704 &wcss_ahb_clk_src.clkr.hw 2705 }, 2706 .num_parents = 1, 2707 .flags = CLK_SET_RATE_PARENT, 2708 .ops = &clk_branch2_ops, 2709 }, 2710 }, 2711 }; 2712 2713 static struct clk_branch gcc_wcss_acmt_clk = { 2714 .halt_reg = 0x2505c, 2715 .clkr = { 2716 .enable_reg = 0x2505c, 2717 .enable_mask = BIT(0), 2718 .hw.init = &(const struct clk_init_data) { 2719 .name = "gcc_wcss_acmt_clk", 2720 .parent_hws = (const struct clk_hw *[]) { 2721 &wcss_ahb_clk_src.clkr.hw 2722 }, 2723 .num_parents = 1, 2724 .flags = CLK_SET_RATE_PARENT, 2725 .ops = &clk_branch2_ops, 2726 }, 2727 }, 2728 }; 2729 2730 static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { 2731 .halt_reg = 0x2e030, 2732 .clkr = { 2733 .enable_reg = 0x2e030, 2734 .enable_mask = BIT(0), 2735 .hw.init = &(const struct clk_init_data) { 2736 .name = "gcc_sys_noc_wcss_ahb_clk", 2737 .parent_hws = (const struct clk_hw *[]) { 2738 &wcss_ahb_clk_src.clkr.hw 2739 }, 2740 .num_parents = 1, 2741 .flags = CLK_SET_RATE_PARENT, 2742 .ops = &clk_branch2_ops, 2743 }, 2744 }, 2745 }; 2746 2747 static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = { 2748 F(24000000, P_XO, 1, 0, 0), 2749 F(133333333, P_GPLL0, 6, 0, 0), 2750 F(266666667, P_GPLL0, 3, 0, 0), 2751 { } 2752 }; 2753 2754 static struct clk_rcg2 wcss_axi_m_clk_src = { 2755 .cmd_rcgr = 0x25078, 2756 .freq_tbl = ftbl_wcss_axi_m_clk_src, 2757 .hid_width = 5, 2758 .parent_map = gcc_xo_gpll0_map, 2759 .clkr.hw.init = &(const struct clk_init_data) { 2760 .name = "wcss_axi_m_clk_src", 2761 .parent_data = gcc_xo_gpll0, 2762 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 2763 .ops = &clk_rcg2_ops, 2764 }, 2765 }; 2766 2767 static struct clk_branch gcc_anoc_wcss_axi_m_clk = { 2768 .halt_reg = 0x2e0a8, 2769 .clkr = { 2770 .enable_reg = 0x2e0a8, 2771 .enable_mask = BIT(0), 2772 .hw.init = &(const struct clk_init_data) { 2773 .name = "gcc_anoc_wcss_axi_m_clk", 2774 .parent_hws = (const struct clk_hw *[]) { 2775 &wcss_axi_m_clk_src.clkr.hw 2776 }, 2777 .num_parents = 1, 2778 .flags = CLK_SET_RATE_PARENT, 2779 .ops = &clk_branch2_ops, 2780 }, 2781 }, 2782 }; 2783 2784 static const struct freq_tbl ftbl_qdss_at_clk_src[] = { 2785 F(240000000, P_GPLL4, 5, 0, 0), 2786 { } 2787 }; 2788 2789 static struct clk_rcg2 qdss_at_clk_src = { 2790 .cmd_rcgr = 0x2d004, 2791 .freq_tbl = ftbl_qdss_at_clk_src, 2792 .hid_width = 5, 2793 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, 2794 .clkr.hw.init = &(const struct clk_init_data) { 2795 .name = "qdss_at_clk_src", 2796 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, 2797 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), 2798 .ops = &clk_rcg2_ops, 2799 }, 2800 }; 2801 2802 static struct clk_branch gcc_q6ss_atbm_clk = { 2803 .halt_reg = 0x2501c, 2804 .clkr = { 2805 .enable_reg = 0x2501c, 2806 .enable_mask = BIT(0), 2807 .hw.init = &(const struct clk_init_data) { 2808 .name = "gcc_q6ss_atbm_clk", 2809 .parent_hws = (const struct clk_hw *[]) { 2810 &qdss_at_clk_src.clkr.hw 2811 }, 2812 .num_parents = 1, 2813 .flags = CLK_SET_RATE_PARENT, 2814 .ops = &clk_branch2_ops, 2815 }, 2816 }, 2817 }; 2818 2819 static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { 2820 .halt_reg = 0x2503c, 2821 .clkr = { 2822 .enable_reg = 0x2503c, 2823 .enable_mask = BIT(0), 2824 .hw.init = &(const struct clk_init_data) { 2825 .name = "gcc_wcss_dbg_ifc_atb_clk", 2826 .parent_hws = (const struct clk_hw *[]) { 2827 &qdss_at_clk_src.clkr.hw 2828 }, 2829 .num_parents = 1, 2830 .flags = CLK_SET_RATE_PARENT, 2831 .ops = &clk_branch2_ops, 2832 }, 2833 }, 2834 }; 2835 2836 static struct clk_branch gcc_nssnoc_atb_clk = { 2837 .halt_reg = 0x17014, 2838 .clkr = { 2839 .enable_reg = 0x17014, 2840 .enable_mask = BIT(0), 2841 .hw.init = &(const struct clk_init_data) { 2842 .name = "gcc_nssnoc_atb_clk", 2843 .parent_hws = (const struct clk_hw *[]) { 2844 &qdss_at_clk_src.clkr.hw 2845 }, 2846 .num_parents = 1, 2847 .flags = CLK_SET_RATE_PARENT, 2848 .ops = &clk_branch2_ops, 2849 }, 2850 }, 2851 }; 2852 2853 static struct clk_branch gcc_qdss_at_clk = { 2854 .halt_reg = 0x2d038, 2855 .clkr = { 2856 .enable_reg = 0x2d038, 2857 .enable_mask = BIT(0), 2858 .hw.init = &(const struct clk_init_data) { 2859 .name = "gcc_qdss_at_clk", 2860 .parent_hws = (const struct clk_hw *[]) { 2861 &qdss_at_clk_src.clkr.hw 2862 }, 2863 .num_parents = 1, 2864 .flags = CLK_SET_RATE_PARENT, 2865 .ops = &clk_branch2_ops, 2866 }, 2867 }, 2868 }; 2869 2870 static struct clk_branch gcc_sys_noc_at_clk = { 2871 .halt_reg = 0x2e038, 2872 .clkr = { 2873 .enable_reg = 0x2e038, 2874 .enable_mask = BIT(0), 2875 .hw.init = &(const struct clk_init_data) { 2876 .name = "gcc_sys_noc_at_clk", 2877 .parent_hws = (const struct clk_hw *[]) { 2878 &qdss_at_clk_src.clkr.hw 2879 }, 2880 .num_parents = 1, 2881 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 2882 .ops = &clk_branch2_ops, 2883 }, 2884 }, 2885 }; 2886 2887 static struct clk_branch gcc_pcnoc_at_clk = { 2888 .halt_reg = 0x31024, 2889 .clkr = { 2890 .enable_reg = 0x31024, 2891 .enable_mask = BIT(0), 2892 .hw.init = &(const struct clk_init_data) { 2893 .name = "gcc_pcnoc_at_clk", 2894 .parent_hws = (const struct clk_hw *[]) { 2895 &qdss_at_clk_src.clkr.hw 2896 }, 2897 .num_parents = 1, 2898 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 2899 .ops = &clk_branch2_ops, 2900 }, 2901 }, 2902 }; 2903 2904 static struct clk_fixed_factor gcc_eud_at_div_clk_src = { 2905 .mult = 1, 2906 .div = 6, 2907 .hw.init = &(const struct clk_init_data) { 2908 .name = "gcc_eud_at_div_clk_src", 2909 .parent_hws = (const struct clk_hw *[]) { 2910 &qdss_at_clk_src.clkr.hw 2911 }, 2912 .num_parents = 1, 2913 .flags = CLK_SET_RATE_PARENT, 2914 .ops = &clk_fixed_factor_ops, 2915 }, 2916 }; 2917 2918 static struct clk_branch gcc_usb0_eud_at_clk = { 2919 .halt_reg = 0x30004, 2920 .clkr = { 2921 .enable_reg = 0x30004, 2922 .enable_mask = BIT(0), 2923 .hw.init = &(const struct clk_init_data) { 2924 .name = "gcc_usb0_eud_at_clk", 2925 .parent_hws = (const struct clk_hw *[]) { 2926 &gcc_eud_at_div_clk_src.hw 2927 }, 2928 .num_parents = 1, 2929 .flags = CLK_SET_RATE_PARENT, 2930 .ops = &clk_branch2_ops, 2931 }, 2932 }, 2933 }; 2934 2935 static struct clk_branch gcc_qdss_eud_at_clk = { 2936 .halt_reg = 0x2d06c, 2937 .clkr = { 2938 .enable_reg = 0x2d06c, 2939 .enable_mask = BIT(0), 2940 .hw.init = &(const struct clk_init_data) { 2941 .name = "gcc_qdss_eud_at_clk", 2942 .parent_hws = (const struct clk_hw *[]) { 2943 &gcc_eud_at_div_clk_src.hw 2944 }, 2945 .num_parents = 1, 2946 .flags = CLK_SET_RATE_PARENT, 2947 .ops = &clk_branch2_ops, 2948 }, 2949 }, 2950 }; 2951 2952 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = { 2953 F(24000000, P_XO, 1, 0, 0), 2954 F(200000000, P_GPLL0, 4, 0, 0), 2955 { } 2956 }; 2957 2958 static struct clk_rcg2 qdss_stm_clk_src = { 2959 .cmd_rcgr = 0x2d00c, 2960 .freq_tbl = ftbl_qdss_stm_clk_src, 2961 .hid_width = 5, 2962 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 2963 .clkr.hw.init = &(const struct clk_init_data) { 2964 .name = "qdss_stm_clk_src", 2965 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 2966 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 2967 .ops = &clk_rcg2_ops, 2968 }, 2969 }; 2970 2971 static struct clk_branch gcc_qdss_stm_clk = { 2972 .halt_reg = 0x2d03c, 2973 .clkr = { 2974 .enable_reg = 0x2d03c, 2975 .enable_mask = BIT(0), 2976 .hw.init = &(const struct clk_init_data) { 2977 .name = "gcc_qdss_stm_clk", 2978 .parent_hws = (const struct clk_hw *[]) { 2979 &qdss_stm_clk_src.clkr.hw 2980 }, 2981 .num_parents = 1, 2982 .flags = CLK_SET_RATE_PARENT, 2983 .ops = &clk_branch2_ops, 2984 }, 2985 }, 2986 }; 2987 2988 static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = { 2989 .halt_reg = 0x2e034, 2990 .clkr = { 2991 .enable_reg = 0x2e034, 2992 .enable_mask = BIT(0), 2993 .hw.init = &(const struct clk_init_data) { 2994 .name = "gcc_sys_noc_qdss_stm_axi_clk", 2995 .parent_hws = (const struct clk_hw *[]) { 2996 &qdss_stm_clk_src.clkr.hw 2997 }, 2998 .num_parents = 1, 2999 .flags = CLK_SET_RATE_PARENT, 3000 .ops = &clk_branch2_ops, 3001 }, 3002 }, 3003 }; 3004 3005 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = { 3006 F(300000000, P_GPLL4, 4, 0, 0), 3007 { } 3008 }; 3009 3010 static struct clk_rcg2 qdss_traceclkin_clk_src = { 3011 .cmd_rcgr = 0x2d014, 3012 .freq_tbl = ftbl_qdss_traceclkin_clk_src, 3013 .hid_width = 5, 3014 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, 3015 .clkr.hw.init = &(const struct clk_init_data) { 3016 .name = "qdss_traceclkin_clk_src", 3017 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, 3018 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), 3019 .ops = &clk_rcg2_ops, 3020 }, 3021 }; 3022 3023 static struct clk_branch gcc_qdss_traceclkin_clk = { 3024 .halt_reg = 0x2d040, 3025 .clkr = { 3026 .enable_reg = 0x2d040, 3027 .enable_mask = BIT(0), 3028 .hw.init = &(const struct clk_init_data) { 3029 .name = "gcc_qdss_traceclkin_clk", 3030 .parent_hws = (const struct clk_hw *[]) { 3031 &qdss_traceclkin_clk_src.clkr.hw 3032 }, 3033 .num_parents = 1, 3034 .flags = CLK_SET_RATE_PARENT, 3035 .ops = &clk_branch2_ops, 3036 }, 3037 }, 3038 }; 3039 3040 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { 3041 F(600000000, P_GPLL4, 2, 0, 0), 3042 { } 3043 }; 3044 3045 static struct clk_rcg2 qdss_tsctr_clk_src = { 3046 .cmd_rcgr = 0x2d01c, 3047 .freq_tbl = ftbl_qdss_tsctr_clk_src, 3048 .hid_width = 5, 3049 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, 3050 .clkr.hw.init = &(const struct clk_init_data) { 3051 .name = "qdss_tsctr_clk_src", 3052 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, 3053 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), 3054 .ops = &clk_rcg2_ops, 3055 }, 3056 }; 3057 3058 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { 3059 .mult = 1, 3060 .div = 2, 3061 .hw.init = &(const struct clk_init_data) { 3062 .name = "qdss_tsctr_div2_clk_src", 3063 .parent_hws = (const struct clk_hw *[]) { 3064 &qdss_tsctr_clk_src.clkr.hw 3065 }, 3066 .num_parents = 1, 3067 .flags = CLK_SET_RATE_PARENT, 3068 .ops = &clk_fixed_factor_ops, 3069 }, 3070 }; 3071 3072 static struct clk_branch gcc_q6_tsctr_1to2_clk = { 3073 .halt_reg = 0x25020, 3074 .clkr = { 3075 .enable_reg = 0x25020, 3076 .enable_mask = BIT(0), 3077 .hw.init = &(const struct clk_init_data) { 3078 .name = "gcc_q6_tsctr_1to2_clk", 3079 .parent_hws = (const struct clk_hw *[]) { 3080 &qdss_tsctr_div2_clk_src.hw 3081 }, 3082 .num_parents = 1, 3083 .flags = CLK_SET_RATE_PARENT, 3084 .ops = &clk_branch2_ops, 3085 }, 3086 }, 3087 }; 3088 3089 static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { 3090 .halt_reg = 0x25040, 3091 .clkr = { 3092 .enable_reg = 0x25040, 3093 .enable_mask = BIT(0), 3094 .hw.init = &(const struct clk_init_data) { 3095 .name = "gcc_wcss_dbg_ifc_nts_clk", 3096 .parent_hws = (const struct clk_hw *[]) { 3097 &qdss_tsctr_div2_clk_src.hw 3098 }, 3099 .num_parents = 1, 3100 .flags = CLK_SET_RATE_PARENT, 3101 .ops = &clk_branch2_ops, 3102 }, 3103 }, 3104 }; 3105 3106 static struct clk_branch gcc_qdss_tsctr_div2_clk = { 3107 .halt_reg = 0x2d044, 3108 .clkr = { 3109 .enable_reg = 0x2d044, 3110 .enable_mask = BIT(0), 3111 .hw.init = &(const struct clk_init_data) { 3112 .name = "gcc_qdss_tsctr_div2_clk", 3113 .parent_hws = (const struct clk_hw *[]) { 3114 &qdss_tsctr_div2_clk_src.hw 3115 }, 3116 .num_parents = 1, 3117 .flags = CLK_SET_RATE_PARENT, 3118 .ops = &clk_branch2_ops, 3119 }, 3120 }, 3121 }; 3122 3123 static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = { 3124 F(24000000, P_XO, 1, 0, 0), 3125 { } 3126 }; 3127 3128 static struct clk_rcg2 uniphy_sys_clk_src = { 3129 .cmd_rcgr = 0x17090, 3130 .freq_tbl = ftbl_uniphy_sys_clk_src, 3131 .mnd_width = 8, 3132 .hid_width = 5, 3133 .parent_map = gcc_xo_map, 3134 .clkr.hw.init = &(const struct clk_init_data) { 3135 .name = "uniphy_sys_clk_src", 3136 .parent_data = gcc_xo_data, 3137 .num_parents = ARRAY_SIZE(gcc_xo_data), 3138 .ops = &clk_rcg2_ops, 3139 }, 3140 }; 3141 3142 static struct clk_rcg2 nss_ts_clk_src = { 3143 .cmd_rcgr = 0x17088, 3144 .freq_tbl = ftbl_uniphy_sys_clk_src, 3145 .mnd_width = 8, 3146 .hid_width = 5, 3147 .parent_map = gcc_xo_map, 3148 .clkr.hw.init = &(const struct clk_init_data) { 3149 .name = "nss_ts_clk_src", 3150 .parent_data = gcc_xo_data, 3151 .num_parents = ARRAY_SIZE(gcc_xo_data), 3152 .ops = &clk_rcg2_ops, 3153 }, 3154 }; 3155 3156 static struct clk_branch gcc_qdss_ts_clk = { 3157 .halt_reg = 0x2d078, 3158 .clkr = { 3159 .enable_reg = 0x2d078, 3160 .enable_mask = BIT(0), 3161 .hw.init = &(const struct clk_init_data) { 3162 .name = "gcc_qdss_ts_clk", 3163 .parent_hws = (const struct clk_hw *[]) { 3164 &nss_ts_clk_src.clkr.hw 3165 }, 3166 .num_parents = 1, 3167 .flags = CLK_SET_RATE_PARENT, 3168 .ops = &clk_branch2_ops, 3169 }, 3170 }, 3171 }; 3172 3173 static struct clk_fixed_factor qdss_dap_sync_clk_src = { 3174 .mult = 1, 3175 .div = 4, 3176 .hw.init = &(const struct clk_init_data) { 3177 .name = "qdss_dap_sync_clk_src", 3178 .parent_hws = (const struct clk_hw *[]) { 3179 &qdss_tsctr_clk_src.clkr.hw 3180 }, 3181 .num_parents = 1, 3182 .ops = &clk_fixed_factor_ops, 3183 }, 3184 }; 3185 3186 static struct clk_branch gcc_qdss_tsctr_div4_clk = { 3187 .halt_reg = 0x2d04c, 3188 .clkr = { 3189 .enable_reg = 0x2d04c, 3190 .enable_mask = BIT(0), 3191 .hw.init = &(const struct clk_init_data) { 3192 .name = "gcc_qdss_tsctr_div4_clk", 3193 .parent_hws = (const struct clk_hw *[]) { 3194 &qdss_dap_sync_clk_src.hw 3195 }, 3196 .num_parents = 1, 3197 .flags = CLK_SET_RATE_PARENT, 3198 .ops = &clk_branch2_ops, 3199 }, 3200 }, 3201 }; 3202 3203 static struct clk_fixed_factor qdss_tsctr_div8_clk_src = { 3204 .mult = 1, 3205 .div = 8, 3206 .hw.init = &(const struct clk_init_data) { 3207 .name = "qdss_tsctr_div8_clk_src", 3208 .parent_hws = (const struct clk_hw *[]) { 3209 &qdss_tsctr_clk_src.clkr.hw 3210 }, 3211 .num_parents = 1, 3212 .ops = &clk_fixed_factor_ops, 3213 }, 3214 }; 3215 3216 static struct clk_branch gcc_nss_ts_clk = { 3217 .halt_reg = 0x17018, 3218 .clkr = { 3219 .enable_reg = 0x17018, 3220 .enable_mask = BIT(0), 3221 .hw.init = &(const struct clk_init_data) { 3222 .name = "gcc_nss_ts_clk", 3223 .parent_hws = (const struct clk_hw *[]) { 3224 &nss_ts_clk_src.clkr.hw 3225 }, 3226 .num_parents = 1, 3227 .flags = CLK_SET_RATE_PARENT, 3228 .ops = &clk_branch2_ops, 3229 }, 3230 }, 3231 }; 3232 3233 static struct clk_branch gcc_qdss_tsctr_div8_clk = { 3234 .halt_reg = 0x2d050, 3235 .clkr = { 3236 .enable_reg = 0x2d050, 3237 .enable_mask = BIT(0), 3238 .hw.init = &(const struct clk_init_data) { 3239 .name = "gcc_qdss_tsctr_div8_clk", 3240 .parent_hws = (const struct clk_hw *[]) { 3241 &qdss_tsctr_div8_clk_src.hw 3242 }, 3243 .num_parents = 1, 3244 .flags = CLK_SET_RATE_PARENT, 3245 .ops = &clk_branch2_ops, 3246 }, 3247 }, 3248 }; 3249 3250 static struct clk_fixed_factor qdss_tsctr_div16_clk_src = { 3251 .mult = 1, 3252 .div = 16, 3253 .hw.init = &(const struct clk_init_data) { 3254 .name = "qdss_tsctr_div16_clk_src", 3255 .parent_hws = (const struct clk_hw *[]) { 3256 &qdss_tsctr_clk_src.clkr.hw 3257 }, 3258 .num_parents = 1, 3259 .ops = &clk_fixed_factor_ops, 3260 }, 3261 }; 3262 3263 static struct clk_branch gcc_qdss_tsctr_div16_clk = { 3264 .halt_reg = 0x2d054, 3265 .clkr = { 3266 .enable_reg = 0x2d054, 3267 .enable_mask = BIT(0), 3268 .hw.init = &(const struct clk_init_data) { 3269 .name = "gcc_qdss_tsctr_div16_clk", 3270 .parent_hws = (const struct clk_hw *[]) { 3271 &qdss_tsctr_div16_clk_src.hw 3272 }, 3273 .num_parents = 1, 3274 .flags = CLK_SET_RATE_PARENT, 3275 .ops = &clk_branch2_ops, 3276 }, 3277 }, 3278 }; 3279 3280 static struct clk_branch gcc_q6ss_pclkdbg_clk = { 3281 .halt_reg = 0x25024, 3282 .clkr = { 3283 .enable_reg = 0x25024, 3284 .enable_mask = BIT(0), 3285 .hw.init = &(const struct clk_init_data) { 3286 .name = "gcc_q6ss_pclkdbg_clk", 3287 .parent_hws = (const struct clk_hw *[]) { 3288 &qdss_dap_sync_clk_src.hw 3289 }, 3290 .num_parents = 1, 3291 .flags = CLK_SET_RATE_PARENT, 3292 .ops = &clk_branch2_ops, 3293 }, 3294 }, 3295 }; 3296 3297 static struct clk_branch gcc_q6ss_trig_clk = { 3298 .halt_reg = 0x25068, 3299 .clkr = { 3300 .enable_reg = 0x25068, 3301 .enable_mask = BIT(0), 3302 .hw.init = &(const struct clk_init_data) { 3303 .name = "gcc_q6ss_trig_clk", 3304 .parent_hws = (const struct clk_hw *[]) { 3305 &qdss_dap_sync_clk_src.hw 3306 }, 3307 .num_parents = 1, 3308 .flags = CLK_SET_RATE_PARENT, 3309 .ops = &clk_branch2_ops, 3310 }, 3311 }, 3312 }; 3313 3314 static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { 3315 .halt_reg = 0x25038, 3316 .clkr = { 3317 .enable_reg = 0x25038, 3318 .enable_mask = BIT(0), 3319 .hw.init = &(const struct clk_init_data) { 3320 .name = "gcc_wcss_dbg_ifc_apb_clk", 3321 .parent_hws = (const struct clk_hw *[]) { 3322 &qdss_dap_sync_clk_src.hw 3323 }, 3324 .num_parents = 1, 3325 .flags = CLK_SET_RATE_PARENT, 3326 .ops = &clk_branch2_ops, 3327 }, 3328 }, 3329 }; 3330 3331 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { 3332 .halt_reg = 0x25044, 3333 .clkr = { 3334 .enable_reg = 0x25044, 3335 .enable_mask = BIT(0), 3336 .hw.init = &(const struct clk_init_data) { 3337 .name = "gcc_wcss_dbg_ifc_dapbus_clk", 3338 .parent_hws = (const struct clk_hw *[]) { 3339 &qdss_dap_sync_clk_src.hw 3340 }, 3341 .num_parents = 1, 3342 .flags = CLK_SET_RATE_PARENT, 3343 .ops = &clk_branch2_ops, 3344 }, 3345 }, 3346 }; 3347 3348 static struct clk_branch gcc_qdss_dap_clk = { 3349 .halt_reg = 0x2d058, 3350 .clkr = { 3351 .enable_reg = 0x2d058, 3352 .enable_mask = BIT(0), 3353 .hw.init = &(const struct clk_init_data) { 3354 .name = "gcc_qdss_dap_clk", 3355 .parent_hws = (const struct clk_hw *[]) { 3356 &qdss_dap_sync_clk_src.hw 3357 }, 3358 .num_parents = 1, 3359 .flags = CLK_SET_RATE_PARENT, 3360 .ops = &clk_branch2_ops, 3361 }, 3362 }, 3363 }; 3364 3365 static struct clk_branch gcc_qdss_apb2jtag_clk = { 3366 .halt_reg = 0x2d05c, 3367 .clkr = { 3368 .enable_reg = 0x2d05c, 3369 .enable_mask = BIT(0), 3370 .hw.init = &(const struct clk_init_data) { 3371 .name = "gcc_qdss_apb2jtag_clk", 3372 .parent_hws = (const struct clk_hw *[]) { 3373 &qdss_dap_sync_clk_src.hw 3374 }, 3375 .num_parents = 1, 3376 .flags = CLK_SET_RATE_PARENT, 3377 .ops = &clk_branch2_ops, 3378 }, 3379 }, 3380 }; 3381 3382 static struct clk_fixed_factor qdss_tsctr_div3_clk_src = { 3383 .mult = 1, 3384 .div = 3, 3385 .hw.init = &(const struct clk_init_data) { 3386 .name = "qdss_tsctr_div3_clk_src", 3387 .parent_hws = (const struct clk_hw *[]) { 3388 &qdss_tsctr_clk_src.clkr.hw 3389 }, 3390 .num_parents = 1, 3391 .ops = &clk_fixed_factor_ops, 3392 }, 3393 }; 3394 3395 static struct clk_branch gcc_qdss_tsctr_div3_clk = { 3396 .halt_reg = 0x2d048, 3397 .clkr = { 3398 .enable_reg = 0x2d048, 3399 .enable_mask = BIT(0), 3400 .hw.init = &(const struct clk_init_data) { 3401 .name = "gcc_qdss_tsctr_div3_clk", 3402 .parent_hws = (const struct clk_hw *[]) { 3403 &qdss_tsctr_div3_clk_src.hw 3404 }, 3405 .num_parents = 1, 3406 .flags = CLK_SET_RATE_PARENT, 3407 .ops = &clk_branch2_ops, 3408 }, 3409 }, 3410 }; 3411 3412 static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = { 3413 F(24000000, P_XO, 1, 0, 0), 3414 F(100000000, P_GPLL0, 8, 0, 0), 3415 F(200000000, P_GPLL0, 4, 0, 0), 3416 F(320000000, P_GPLL0, 2.5, 0, 0), 3417 F(400000000, P_GPLL0, 2, 0, 0), 3418 { } 3419 }; 3420 3421 static struct clk_rcg2 qpic_io_macro_clk_src = { 3422 .cmd_rcgr = 0x32004, 3423 .freq_tbl = ftbl_qpic_io_macro_clk_src, 3424 .hid_width = 5, 3425 .parent_map = gcc_xo_gpll0_gpll2_map, 3426 .clkr.hw.init = &(const struct clk_init_data) { 3427 .name = "qpic_io_macro_clk_src", 3428 .parent_data = gcc_xo_gpll0_gpll2, 3429 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 3430 .ops = &clk_rcg2_ops, 3431 }, 3432 }; 3433 3434 static struct clk_branch gcc_qpic_io_macro_clk = { 3435 .halt_reg = 0x3200c, 3436 .clkr = { 3437 .enable_reg = 0x3200c, 3438 .enable_mask = BIT(0), 3439 .hw.init = &(const struct clk_init_data){ 3440 .name = "gcc_qpic_io_macro_clk", 3441 .parent_hws = (const struct clk_hw *[]){ 3442 &qpic_io_macro_clk_src.clkr.hw 3443 }, 3444 .num_parents = 1, 3445 .flags = CLK_SET_RATE_PARENT, 3446 .ops = &clk_branch2_ops, 3447 }, 3448 }, 3449 }; 3450 3451 static const struct freq_tbl ftbl_q6_axi_clk_src[] = { 3452 F(533333333, P_GPLL0, 1.5, 0, 0), 3453 { } 3454 }; 3455 3456 static struct clk_rcg2 q6_axi_clk_src = { 3457 .cmd_rcgr = 0x25004, 3458 .freq_tbl = ftbl_q6_axi_clk_src, 3459 .hid_width = 5, 3460 .parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map, 3461 .clkr.hw.init = &(const struct clk_init_data) { 3462 .name = "q6_axi_clk_src", 3463 .parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep, 3464 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep), 3465 .ops = &clk_rcg2_ops, 3466 }, 3467 }; 3468 3469 static struct clk_branch gcc_q6_axim_clk = { 3470 .halt_reg = 0x2500c, 3471 .clkr = { 3472 .enable_reg = 0x2500c, 3473 .enable_mask = BIT(0), 3474 .hw.init = &(const struct clk_init_data) { 3475 .name = "gcc_q6_axim_clk", 3476 .parent_hws = (const struct clk_hw *[]) { 3477 &q6_axi_clk_src.clkr.hw 3478 }, 3479 .num_parents = 1, 3480 .flags = CLK_SET_RATE_PARENT, 3481 .ops = &clk_branch2_ops, 3482 }, 3483 }, 3484 }; 3485 3486 static struct clk_branch gcc_wcss_q6_tbu_clk = { 3487 .halt_reg = 0x12050, 3488 .halt_check = BRANCH_HALT_DELAY, 3489 .clkr = { 3490 .enable_reg = 0xb00c, 3491 .enable_mask = BIT(6), 3492 .hw.init = &(const struct clk_init_data) { 3493 .name = "gcc_wcss_q6_tbu_clk", 3494 .parent_hws = (const struct clk_hw *[]) { 3495 &q6_axi_clk_src.clkr.hw 3496 }, 3497 .num_parents = 1, 3498 .flags = CLK_SET_RATE_PARENT, 3499 .ops = &clk_branch2_ops, 3500 }, 3501 }, 3502 }; 3503 3504 static struct clk_branch gcc_mem_noc_q6_axi_clk = { 3505 .halt_reg = 0x19010, 3506 .clkr = { 3507 .enable_reg = 0x19010, 3508 .enable_mask = BIT(0), 3509 .hw.init = &(const struct clk_init_data) { 3510 .name = "gcc_mem_noc_q6_axi_clk", 3511 .parent_hws = (const struct clk_hw *[]) { 3512 &q6_axi_clk_src.clkr.hw 3513 }, 3514 .num_parents = 1, 3515 .flags = CLK_SET_RATE_PARENT, 3516 .ops = &clk_branch2_ops, 3517 }, 3518 }, 3519 }; 3520 3521 static const struct freq_tbl ftbl_q6_axim2_clk_src[] = { 3522 F(342857143, P_GPLL4, 3.5, 0, 0), 3523 { } 3524 }; 3525 3526 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = { 3527 { P_XO, 0 }, 3528 { P_GPLL0, 1 }, 3529 { P_GPLL4, 2 }, 3530 { P_BIAS_PLL_UBI_NC_CLK, 4 }, 3531 }; 3532 3533 static struct clk_rcg2 q6_axim2_clk_src = { 3534 .cmd_rcgr = 0x25028, 3535 .freq_tbl = ftbl_q6_axim2_clk_src, 3536 .hid_width = 5, 3537 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map, 3538 .clkr.hw.init = &(const struct clk_init_data) { 3539 .name = "q6_axim2_clk_src", 3540 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, 3541 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), 3542 .ops = &clk_rcg2_ops, 3543 }, 3544 }; 3545 3546 static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = { 3547 F(533333333, P_GPLL0, 1.5, 0, 0), 3548 { } 3549 }; 3550 3551 static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = { 3552 .cmd_rcgr = 0x17004, 3553 .freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src, 3554 .hid_width = 5, 3555 .parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map, 3556 .clkr.hw.init = &(const struct clk_init_data) { 3557 .name = "nssnoc_memnoc_bfdcd_clk_src", 3558 .parent_data = gcc_xo_gpll0_gpll0_aux_gpll2, 3559 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2), 3560 .ops = &clk_rcg2_ops, 3561 }, 3562 }; 3563 3564 static struct clk_branch gcc_nssnoc_memnoc_clk = { 3565 .halt_reg = 0x17024, 3566 .clkr = { 3567 .enable_reg = 0x17024, 3568 .enable_mask = BIT(0), 3569 .hw.init = &(const struct clk_init_data) { 3570 .name = "gcc_nssnoc_memnoc_clk", 3571 .parent_hws = (const struct clk_hw *[]) { 3572 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3573 }, 3574 .num_parents = 1, 3575 .flags = CLK_SET_RATE_PARENT, 3576 .ops = &clk_branch2_ops, 3577 }, 3578 }, 3579 }; 3580 3581 static struct clk_branch gcc_nssnoc_mem_noc_1_clk = { 3582 .halt_reg = 0x17084, 3583 .clkr = { 3584 .enable_reg = 0x17084, 3585 .enable_mask = BIT(0), 3586 .hw.init = &(const struct clk_init_data) { 3587 .name = "gcc_nssnoc_mem_noc_1_clk", 3588 .parent_hws = (const struct clk_hw *[]) { 3589 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3590 }, 3591 .num_parents = 1, 3592 .flags = CLK_SET_RATE_PARENT, 3593 .ops = &clk_branch2_ops, 3594 }, 3595 }, 3596 }; 3597 3598 static struct clk_branch gcc_nss_tbu_clk = { 3599 .halt_reg = 0x12040, 3600 .clkr = { 3601 .enable_reg = 0xb00c, 3602 .enable_mask = BIT(4), 3603 .hw.init = &(const struct clk_init_data) { 3604 .name = "gcc_nss_tbu_clk", 3605 .parent_hws = (const struct clk_hw *[]) { 3606 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3607 }, 3608 .num_parents = 1, 3609 .flags = CLK_SET_RATE_PARENT, 3610 .ops = &clk_branch2_ops, 3611 }, 3612 }, 3613 }; 3614 3615 static struct clk_branch gcc_mem_noc_nssnoc_clk = { 3616 .halt_reg = 0x19014, 3617 .clkr = { 3618 .enable_reg = 0x19014, 3619 .enable_mask = BIT(0), 3620 .hw.init = &(const struct clk_init_data) { 3621 .name = "gcc_mem_noc_nssnoc_clk", 3622 .parent_hws = (const struct clk_hw *[]) { 3623 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3624 }, 3625 .num_parents = 1, 3626 .flags = CLK_SET_RATE_PARENT, 3627 .ops = &clk_branch2_ops, 3628 }, 3629 }, 3630 }; 3631 3632 static const struct freq_tbl ftbl_lpass_axim_clk_src[] = { 3633 F(133333333, P_GPLL0, 6, 0, 0), 3634 { } 3635 }; 3636 3637 static struct clk_rcg2 lpass_axim_clk_src = { 3638 .cmd_rcgr = 0x2700c, 3639 .freq_tbl = ftbl_lpass_axim_clk_src, 3640 .hid_width = 5, 3641 .parent_map = gcc_xo_gpll0_map, 3642 .clkr.hw.init = &(const struct clk_init_data) { 3643 .name = "lpass_axim_clk_src", 3644 .parent_data = gcc_xo_gpll0, 3645 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 3646 .ops = &clk_rcg2_ops, 3647 }, 3648 }; 3649 3650 static struct clk_rcg2 lpass_sway_clk_src = { 3651 .cmd_rcgr = 0x27004, 3652 .freq_tbl = ftbl_lpass_axim_clk_src, 3653 .hid_width = 5, 3654 .parent_map = gcc_xo_gpll0_map, 3655 .clkr.hw.init = &(const struct clk_init_data) { 3656 .name = "lpass_sway_clk_src", 3657 .parent_data = gcc_xo_gpll0, 3658 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 3659 .ops = &clk_rcg2_ops, 3660 }, 3661 }; 3662 3663 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = { 3664 F(24000000, P_XO, 1, 0, 0), 3665 F(100000000, P_GPLL0, 8, 0, 0), 3666 { } 3667 }; 3668 3669 static struct clk_rcg2 adss_pwm_clk_src = { 3670 .cmd_rcgr = 0x1c004, 3671 .freq_tbl = ftbl_adss_pwm_clk_src, 3672 .hid_width = 5, 3673 .parent_map = gcc_xo_gpll0_map, 3674 .clkr.hw.init = &(const struct clk_init_data) { 3675 .name = "adss_pwm_clk_src", 3676 .parent_data = gcc_xo_gpll0, 3677 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 3678 .ops = &clk_rcg2_ops, 3679 }, 3680 }; 3681 3682 static struct clk_branch gcc_adss_pwm_clk = { 3683 .halt_reg = 0x1c00c, 3684 .clkr = { 3685 .enable_reg = 0x1c00c, 3686 .enable_mask = BIT(0), 3687 .hw.init = &(const struct clk_init_data) { 3688 .name = "gcc_adss_pwm_clk", 3689 .parent_hws = (const struct clk_hw *[]) { 3690 &adss_pwm_clk_src.clkr.hw 3691 }, 3692 .num_parents = 1, 3693 .flags = CLK_SET_RATE_PARENT, 3694 .ops = &clk_branch2_ops, 3695 }, 3696 }, 3697 }; 3698 3699 static const struct freq_tbl ftbl_gp1_clk_src[] = { 3700 F(24000000, P_XO, 1, 0, 0), 3701 F(200000000, P_GPLL0, 4, 0, 0), 3702 { } 3703 }; 3704 3705 static struct clk_rcg2 gp1_clk_src = { 3706 .cmd_rcgr = 0x8004, 3707 .freq_tbl = ftbl_gp1_clk_src, 3708 .hid_width = 5, 3709 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, 3710 .clkr.hw.init = &(const struct clk_init_data) { 3711 .name = "gp1_clk_src", 3712 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, 3713 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), 3714 .ops = &clk_rcg2_ops, 3715 }, 3716 }; 3717 3718 static struct clk_rcg2 gp2_clk_src = { 3719 .cmd_rcgr = 0x9004, 3720 .freq_tbl = ftbl_gp1_clk_src, 3721 .hid_width = 5, 3722 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, 3723 .clkr.hw.init = &(const struct clk_init_data) { 3724 .name = "gp2_clk_src", 3725 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, 3726 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), 3727 .ops = &clk_rcg2_ops, 3728 }, 3729 }; 3730 3731 static struct clk_rcg2 gp3_clk_src = { 3732 .cmd_rcgr = 0xa004, 3733 .freq_tbl = ftbl_gp1_clk_src, 3734 .hid_width = 5, 3735 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, 3736 .clkr.hw.init = &(const struct clk_init_data) { 3737 .name = "gp3_clk_src", 3738 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, 3739 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), 3740 .ops = &clk_rcg2_ops, 3741 }, 3742 }; 3743 3744 static struct clk_branch gcc_xo_clk_src = { 3745 .halt_reg = 0x34004, 3746 .clkr = { 3747 .enable_reg = 0x34004, 3748 .enable_mask = BIT(1), 3749 .hw.init = &(const struct clk_init_data) { 3750 .name = "gcc_xo_clk_src", 3751 .parent_data = gcc_xo_data, 3752 .num_parents = ARRAY_SIZE(gcc_xo_data), 3753 .flags = CLK_SET_RATE_PARENT, 3754 .ops = &clk_branch2_ops, 3755 }, 3756 }, 3757 }; 3758 3759 static struct clk_branch gcc_nssnoc_xo_dcd_clk = { 3760 .halt_reg = 0x17074, 3761 .clkr = { 3762 .enable_reg = 0x17074, 3763 .enable_mask = BIT(0), 3764 .hw.init = &(const struct clk_init_data) { 3765 .name = "gcc_nssnoc_xo_dcd_clk", 3766 .parent_hws = (const struct clk_hw *[]) { 3767 &gcc_xo_clk_src.clkr.hw 3768 }, 3769 .num_parents = 1, 3770 .flags = CLK_SET_RATE_PARENT, 3771 .ops = &clk_branch2_ops, 3772 }, 3773 }, 3774 }; 3775 3776 static struct clk_branch gcc_xo_clk = { 3777 .halt_reg = 0x34018, 3778 .clkr = { 3779 .enable_reg = 0x34018, 3780 .enable_mask = BIT(0), 3781 .hw.init = &(const struct clk_init_data) { 3782 .name = "gcc_xo_clk", 3783 .parent_hws = (const struct clk_hw *[]) { 3784 &gcc_xo_clk_src.clkr.hw 3785 }, 3786 .num_parents = 1, 3787 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3788 .ops = &clk_branch2_ops, 3789 }, 3790 }, 3791 }; 3792 3793 static struct clk_branch gcc_uniphy0_sys_clk = { 3794 .halt_reg = 0x17048, 3795 .clkr = { 3796 .enable_reg = 0x17048, 3797 .enable_mask = BIT(0), 3798 .hw.init = &(const struct clk_init_data) { 3799 .name = "gcc_uniphy0_sys_clk", 3800 .parent_hws = (const struct clk_hw *[]) { 3801 &uniphy_sys_clk_src.clkr.hw 3802 }, 3803 .num_parents = 1, 3804 .flags = CLK_SET_RATE_PARENT, 3805 .ops = &clk_branch2_ops, 3806 }, 3807 }, 3808 }; 3809 3810 static struct clk_branch gcc_uniphy1_sys_clk = { 3811 .halt_reg = 0x17058, 3812 .clkr = { 3813 .enable_reg = 0x17058, 3814 .enable_mask = BIT(0), 3815 .hw.init = &(const struct clk_init_data) { 3816 .name = "gcc_uniphy1_sys_clk", 3817 .parent_hws = (const struct clk_hw *[]) { 3818 &uniphy_sys_clk_src.clkr.hw 3819 }, 3820 .num_parents = 1, 3821 .flags = CLK_SET_RATE_PARENT, 3822 .ops = &clk_branch2_ops, 3823 }, 3824 }, 3825 }; 3826 3827 static struct clk_branch gcc_uniphy2_sys_clk = { 3828 .halt_reg = 0x17068, 3829 .clkr = { 3830 .enable_reg = 0x17068, 3831 .enable_mask = BIT(0), 3832 .hw.init = &(const struct clk_init_data) { 3833 .name = "gcc_uniphy2_sys_clk", 3834 .parent_hws = (const struct clk_hw *[]) { 3835 &uniphy_sys_clk_src.clkr.hw 3836 }, 3837 .num_parents = 1, 3838 .flags = CLK_SET_RATE_PARENT, 3839 .ops = &clk_branch2_ops, 3840 }, 3841 }, 3842 }; 3843 3844 static struct clk_branch gcc_cmn_12gpll_sys_clk = { 3845 .halt_reg = 0x3a008, 3846 .clkr = { 3847 .enable_reg = 0x3a008, 3848 .enable_mask = BIT(0), 3849 .hw.init = &(const struct clk_init_data) { 3850 .name = "gcc_cmn_12gpll_sys_clk", 3851 .parent_hws = (const struct clk_hw *[]) { 3852 &uniphy_sys_clk_src.clkr.hw 3853 }, 3854 .num_parents = 1, 3855 .flags = CLK_SET_RATE_PARENT, 3856 .ops = &clk_branch2_ops, 3857 }, 3858 }, 3859 }; 3860 3861 static struct clk_fixed_factor gcc_xo_div4_clk_src = { 3862 .mult = 1, 3863 .div = 4, 3864 .hw.init = &(const struct clk_init_data) { 3865 .name = "gcc_xo_div4_clk_src", 3866 .parent_hws = (const struct clk_hw *[]) { 3867 &gcc_xo_clk_src.clkr.hw 3868 }, 3869 .num_parents = 1, 3870 .flags = CLK_SET_RATE_PARENT, 3871 .ops = &clk_fixed_factor_ops, 3872 }, 3873 }; 3874 3875 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { 3876 .halt_reg = 0x1701c, 3877 .clkr = { 3878 .enable_reg = 0x1701c, 3879 .enable_mask = BIT(0), 3880 .hw.init = &(const struct clk_init_data) { 3881 .name = "gcc_nssnoc_qosgen_ref_clk", 3882 .parent_hws = (const struct clk_hw *[]) { 3883 &gcc_xo_div4_clk_src.hw 3884 }, 3885 .num_parents = 1, 3886 .flags = CLK_SET_RATE_PARENT, 3887 .ops = &clk_branch2_ops, 3888 }, 3889 }, 3890 }; 3891 3892 static struct clk_branch gcc_nssnoc_timeout_ref_clk = { 3893 .halt_reg = 0x17020, 3894 .clkr = { 3895 .enable_reg = 0x17020, 3896 .enable_mask = BIT(0), 3897 .hw.init = &(const struct clk_init_data) { 3898 .name = "gcc_nssnoc_timeout_ref_clk", 3899 .parent_hws = (const struct clk_hw *[]) { 3900 &gcc_xo_div4_clk_src.hw 3901 }, 3902 .num_parents = 1, 3903 .flags = CLK_SET_RATE_PARENT, 3904 .ops = &clk_branch2_ops, 3905 }, 3906 }, 3907 }; 3908 3909 static struct clk_branch gcc_xo_div4_clk = { 3910 .halt_reg = 0x3401c, 3911 .clkr = { 3912 .enable_reg = 0x3401c, 3913 .enable_mask = BIT(0), 3914 .hw.init = &(const struct clk_init_data) { 3915 .name = "gcc_xo_div4_clk", 3916 .parent_hws = (const struct clk_hw *[]) { 3917 &gcc_xo_div4_clk_src.hw 3918 }, 3919 .num_parents = 1, 3920 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3921 .ops = &clk_branch2_ops, 3922 }, 3923 }, 3924 }; 3925 3926 static struct clk_hw *gcc_ipq9574_hws[] = { 3927 &gpll0_out_main_div2.hw, 3928 &gcc_xo_div4_clk_src.hw, 3929 &qdss_dap_sync_clk_src.hw, 3930 &qdss_tsctr_div2_clk_src.hw, 3931 &qdss_tsctr_div8_clk_src.hw, 3932 &qdss_tsctr_div16_clk_src.hw, 3933 &qdss_tsctr_div3_clk_src.hw, 3934 &gcc_eud_at_div_clk_src.hw, 3935 }; 3936 3937 static struct clk_regmap *gcc_ipq9574_clks[] = { 3938 [GPLL0_MAIN] = &gpll0_main.clkr, 3939 [GPLL0] = &gpll0.clkr, 3940 [GPLL4_MAIN] = &gpll4_main.clkr, 3941 [GPLL4] = &gpll4.clkr, 3942 [GPLL2_MAIN] = &gpll2_main.clkr, 3943 [GPLL2] = &gpll2.clkr, 3944 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 3945 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3946 [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr, 3947 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3948 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3949 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3950 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3951 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3952 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3953 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3954 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3955 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3956 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3957 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3958 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3959 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3960 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3961 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 3962 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 3963 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 3964 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 3965 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, 3966 [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, 3967 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3968 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3969 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3970 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3971 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3972 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3973 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3974 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3975 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3976 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3977 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3978 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3979 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3980 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3981 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 3982 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 3983 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 3984 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 3985 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3986 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3987 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3988 [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr, 3989 [PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr, 3990 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, 3991 [PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr, 3992 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, 3993 [PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr, 3994 [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr, 3995 [PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr, 3996 [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr, 3997 [PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr, 3998 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, 3999 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, 4000 [PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr, 4001 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, 4002 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, 4003 [PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr, 4004 [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr, 4005 [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr, 4006 [PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr, 4007 [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, 4008 [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, 4009 [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, 4010 [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, 4011 [PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr, 4012 [PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr, 4013 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, 4014 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, 4015 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, 4016 [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr, 4017 [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr, 4018 [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, 4019 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, 4020 [PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr, 4021 [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr, 4022 [PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr, 4023 [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr, 4024 [PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr, 4025 [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr, 4026 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, 4027 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, 4028 [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr, 4029 [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr, 4030 [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr, 4031 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 4032 [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr, 4033 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 4034 [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr, 4035 [GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr, 4036 [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr, 4037 [USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr, 4038 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 4039 [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, 4040 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 4041 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 4042 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 4043 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 4044 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 4045 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, 4046 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 4047 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 4048 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 4049 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, 4050 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, 4051 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, 4052 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 4053 [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, 4054 [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, 4055 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 4056 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 4057 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 4058 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 4059 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 4060 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, 4061 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, 4062 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr, 4063 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, 4064 [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr, 4065 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 4066 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, 4067 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 4068 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, 4069 [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, 4070 [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, 4071 [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, 4072 [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, 4073 [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, 4074 [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, 4075 [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, 4076 [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, 4077 [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, 4078 [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, 4079 [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, 4080 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 4081 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 4082 [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, 4083 [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr, 4084 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, 4085 [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, 4086 [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, 4087 [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr, 4088 [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, 4089 [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, 4090 [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, 4091 [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, 4092 [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, 4093 [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, 4094 [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, 4095 [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, 4096 [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, 4097 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 4098 [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, 4099 [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr, 4100 [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, 4101 [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, 4102 [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, 4103 [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, 4104 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 4105 [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, 4106 [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, 4107 [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, 4108 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 4109 [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, 4110 [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, 4111 [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, 4112 [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, 4113 [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, 4114 [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr, 4115 [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, 4116 [GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr, 4117 [GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr, 4118 [GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr, 4119 [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr, 4120 [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr, 4121 [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, 4122 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 4123 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 4124 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 4125 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 4126 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 4127 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, 4128 [GCC_XO_CLK] = &gcc_xo_clk.clkr, 4129 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, 4130 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, 4131 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr, 4132 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, 4133 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 4134 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, 4135 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 4136 [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr, 4137 [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr, 4138 [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr, 4139 [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, 4140 [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr, 4141 [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr, 4142 [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr, 4143 [GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr, 4144 [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, 4145 [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, 4146 [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, 4147 }; 4148 4149 static const struct qcom_reset_map gcc_ipq9574_resets[] = { 4150 [GCC_ADSS_BCR] = { 0x1c000, 0 }, 4151 [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 }, 4152 [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 }, 4153 [GCC_ANOC_BCR] = { 0x2e074, 0 }, 4154 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 }, 4155 [GCC_APSS_TCU_BCR] = { 0x12014, 0 }, 4156 [GCC_BLSP1_BCR] = { 0x01000, 0 }, 4157 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 }, 4158 [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 }, 4159 [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 }, 4160 [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 }, 4161 [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 }, 4162 [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 }, 4163 [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 }, 4164 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 }, 4165 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 }, 4166 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 }, 4167 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 }, 4168 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 }, 4169 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 }, 4170 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 }, 4171 [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 }, 4172 [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 }, 4173 [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 }, 4174 [GCC_CRYPTO_BCR] = { 0x16000, 0 }, 4175 [GCC_DCC_BCR] = { 0x35000, 0 }, 4176 [GCC_DDRSS_BCR] = { 0x11000, 0 }, 4177 [GCC_IMEM_BCR] = { 0x0e000, 0 }, 4178 [GCC_LPASS_BCR] = { 0x27000, 0 }, 4179 [GCC_MDIO_BCR] = { 0x1703c, 0 }, 4180 [GCC_MPM_BCR] = { 0x37000, 0 }, 4181 [GCC_MSG_RAM_BCR] = { 0x26000, 0 }, 4182 [GCC_NSS_BCR] = { 0x17000, 0 }, 4183 [GCC_NSS_TBU_BCR] = { 0x12044, 0 }, 4184 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 }, 4185 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 }, 4186 [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 }, 4187 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 }, 4188 [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 }, 4189 [GCC_NSSCC_ARES] = { 0x17038, 8 }, 4190 [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 }, 4191 [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 }, 4192 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 }, 4193 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 }, 4194 [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 }, 4195 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 }, 4196 [GCC_NSS_CFG_ARES] = { 0x17038, 1 }, 4197 [GCC_UBI0_DBG_ARES] = { 0x17038, 0 }, 4198 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 }, 4199 [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 }, 4200 [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 }, 4201 [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 }, 4202 [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 }, 4203 [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 }, 4204 [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 }, 4205 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 }, 4206 [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 }, 4207 [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 }, 4208 [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 }, 4209 [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 }, 4210 [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 }, 4211 [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 }, 4212 [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 }, 4213 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 }, 4214 [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 }, 4215 [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 }, 4216 [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 }, 4217 [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 }, 4218 [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 }, 4219 [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 }, 4220 [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 }, 4221 [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 }, 4222 [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 }, 4223 [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 }, 4224 [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 }, 4225 [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 }, 4226 [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 }, 4227 [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 }, 4228 [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 }, 4229 [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 }, 4230 [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 }, 4231 [GCC_PCIE0_BCR] = { 0x28000, 0 }, 4232 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 }, 4233 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 }, 4234 [GCC_PCIE1_BCR] = { 0x29000, 0 }, 4235 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 }, 4236 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 }, 4237 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 }, 4238 [GCC_PCIE2_BCR] = { 0x2a000, 0 }, 4239 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 }, 4240 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 }, 4241 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 }, 4242 [GCC_PCIE3_BCR] = { 0x2b000, 0 }, 4243 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 }, 4244 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 }, 4245 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 }, 4246 [GCC_PCNOC_BCR] = { 0x31000, 0 }, 4247 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 }, 4248 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 }, 4249 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 }, 4250 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 }, 4251 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 }, 4252 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 }, 4253 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 }, 4254 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 }, 4255 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 }, 4256 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 }, 4257 [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 }, 4258 [GCC_PRNG_BCR] = { 0x13020, 0 }, 4259 [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 }, 4260 [GCC_Q6_AHB_ARES] = { 0x2506c, 3 }, 4261 [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 }, 4262 [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 }, 4263 [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 }, 4264 [GCC_QDSS_BCR] = { 0x2d000, 0 }, 4265 [GCC_QPIC_BCR] = { 0x32000, 0 }, 4266 [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 }, 4267 [GCC_QPIC_ARES] = { 0x3201c, 0 }, 4268 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 }, 4269 [GCC_RBCPR_BCR] = { 0x39000, 0 }, 4270 [GCC_RBCPR_MX_BCR] = { 0x39014, 0 }, 4271 [GCC_SDCC_BCR] = { 0x33000, 0 }, 4272 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, 4273 [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 }, 4274 [GCC_SNOC_BCR] = { 0x2e000, 0 }, 4275 [GCC_SPDM_BCR] = { 0x36000, 0 }, 4276 [GCC_TCSR_BCR] = { 0x3d000, 0 }, 4277 [GCC_TLMM_BCR] = { 0x3e000, 0 }, 4278 [GCC_TME_BCR] = { 0x10000, 0 }, 4279 [GCC_UNIPHY0_BCR] = { 0x17044, 0 }, 4280 [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 }, 4281 [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 }, 4282 [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 }, 4283 [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 }, 4284 [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 }, 4285 [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 }, 4286 [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 }, 4287 [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 }, 4288 [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 }, 4289 [GCC_UNIPHY1_BCR] = { 0x17054, 0 }, 4290 [GCC_UNIPHY2_BCR] = { 0x17064, 0 }, 4291 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 }, 4292 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 }, 4293 [GCC_USB_BCR] = { 0x2c000, 0 }, 4294 [GCC_USB_MISC_RESET] = { 0x2c064, 0 }, 4295 [GCC_WCSSAON_RESET] = { 0x25074, 0 }, 4296 [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 }, 4297 [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 }, 4298 [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 }, 4299 [GCC_WCSS_BCR] = { 0x18004, 0 }, 4300 [GCC_WCSS_DBG_ARES] = { 0x25070, 2 }, 4301 [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 }, 4302 [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 }, 4303 [GCC_WCSS_Q6_BCR] = { 0x18000, 0 }, 4304 [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, 4305 }; 4306 4307 static const struct of_device_id gcc_ipq9574_match_table[] = { 4308 { .compatible = "qcom,ipq9574-gcc" }, 4309 { } 4310 }; 4311 MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table); 4312 4313 static const struct regmap_config gcc_ipq9574_regmap_config = { 4314 .reg_bits = 32, 4315 .reg_stride = 4, 4316 .val_bits = 32, 4317 .max_register = 0x7fffc, 4318 .fast_io = true, 4319 }; 4320 4321 static const struct qcom_cc_desc gcc_ipq9574_desc = { 4322 .config = &gcc_ipq9574_regmap_config, 4323 .clks = gcc_ipq9574_clks, 4324 .num_clks = ARRAY_SIZE(gcc_ipq9574_clks), 4325 .resets = gcc_ipq9574_resets, 4326 .num_resets = ARRAY_SIZE(gcc_ipq9574_resets), 4327 .clk_hws = gcc_ipq9574_hws, 4328 .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws), 4329 }; 4330 4331 static int gcc_ipq9574_probe(struct platform_device *pdev) 4332 { 4333 return qcom_cc_probe(pdev, &gcc_ipq9574_desc); 4334 } 4335 4336 static struct platform_driver gcc_ipq9574_driver = { 4337 .probe = gcc_ipq9574_probe, 4338 .driver = { 4339 .name = "qcom,gcc-ipq9574", 4340 .of_match_table = gcc_ipq9574_match_table, 4341 }, 4342 }; 4343 4344 static int __init gcc_ipq9574_init(void) 4345 { 4346 return platform_driver_register(&gcc_ipq9574_driver); 4347 } 4348 core_initcall(gcc_ipq9574_init); 4349 4350 static void __exit gcc_ipq9574_exit(void) 4351 { 4352 platform_driver_unregister(&gcc_ipq9574_driver); 4353 } 4354 module_exit(gcc_ipq9574_exit); 4355 4356 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver"); 4357 MODULE_LICENSE("GPL"); 4358