1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 7 * AD7175-8/AD7176-2/AD7177-2 8 * 9 * Copyright (C) 2015, 2024 Analog Devices, Inc. 10 */ 11 12 #include <linux/array_size.h> 13 #include <linux/bitfield.h> 14 #include <linux/bitmap.h> 15 #include <linux/container_of.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/err.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/gpio/regmap.h> 23 #include <linux/idr.h> 24 #include <linux/interrupt.h> 25 #include <linux/math64.h> 26 #include <linux/module.h> 27 #include <linux/mod_devicetable.h> 28 #include <linux/property.h> 29 #include <linux/regmap.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 #include <linux/spi/spi.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 36 #include <linux/iio/buffer.h> 37 #include <linux/iio/iio.h> 38 #include <linux/iio/trigger_consumer.h> 39 #include <linux/iio/triggered_buffer.h> 40 41 #include <linux/iio/adc/ad_sigma_delta.h> 42 43 #define AD7173_REG_COMMS 0x00 44 #define AD7173_REG_ADC_MODE 0x01 45 #define AD7173_REG_INTERFACE_MODE 0x02 46 #define AD7173_REG_CRC 0x03 47 #define AD7173_REG_DATA 0x04 48 #define AD7173_REG_GPIO 0x06 49 #define AD7173_REG_ID 0x07 50 #define AD7173_REG_CH(x) (0x10 + (x)) 51 #define AD7173_REG_SETUP(x) (0x20 + (x)) 52 #define AD7173_REG_FILTER(x) (0x28 + (x)) 53 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 54 #define AD7173_REG_GAIN(x) (0x38 + (x)) 55 56 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 57 58 #define AD7173_CH_ENABLE BIT(15) 59 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 60 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 61 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 62 63 #define AD7173_CH_ADDRESS(pos, neg) \ 64 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 65 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 66 #define AD7173_AIN_TEMP_POS 17 67 #define AD7173_AIN_TEMP_NEG 18 68 69 #define AD7172_2_ID 0x00d0 70 #define AD7175_ID 0x0cd0 71 #define AD7176_ID 0x0c90 72 #define AD7175_2_ID 0x0cd0 73 #define AD7172_4_ID 0x2050 74 #define AD7173_ID 0x30d0 75 #define AD7175_8_ID 0x3cd0 76 #define AD7177_ID 0x4fd0 77 #define AD7173_ID_MASK GENMASK(15, 4) 78 79 #define AD7173_ADC_MODE_REF_EN BIT(15) 80 #define AD7173_ADC_MODE_SING_CYC BIT(13) 81 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 82 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 83 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 84 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 85 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 86 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 87 88 #define AD7173_GPIO_PDSW BIT(14) 89 #define AD7173_GPIO_OP_EN2_3 BIT(13) 90 #define AD7173_GPIO_MUX_IO BIT(12) 91 #define AD7173_GPIO_SYNC_EN BIT(11) 92 #define AD7173_GPIO_ERR_EN BIT(10) 93 #define AD7173_GPIO_ERR_DAT BIT(9) 94 #define AD7173_GPIO_GP_DATA3 BIT(7) 95 #define AD7173_GPIO_GP_DATA2 BIT(6) 96 #define AD7173_GPIO_IP_EN1 BIT(5) 97 #define AD7173_GPIO_IP_EN0 BIT(4) 98 #define AD7173_GPIO_OP_EN1 BIT(3) 99 #define AD7173_GPIO_OP_EN0 BIT(2) 100 #define AD7173_GPIO_GP_DATA1 BIT(1) 101 #define AD7173_GPIO_GP_DATA0 BIT(0) 102 103 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 104 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 105 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 106 107 #define AD7173_INTERFACE_DATA_STAT BIT(6) 108 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 109 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 110 111 #define AD7173_SETUP_BIPOLAR BIT(12) 112 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 113 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 114 115 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 116 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 117 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 118 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 119 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 120 #define AD7173_VOLTAGE_INT_REF_uV 2500000 121 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 122 #define AD7177_ODR_START_VALUE 0x07 123 124 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 125 #define AD7173_MAX_CONFIGS 8 126 127 enum ad7173_ids { 128 ID_AD7172_2, 129 ID_AD7172_4, 130 ID_AD7173_8, 131 ID_AD7175_2, 132 ID_AD7175_8, 133 ID_AD7176_2, 134 ID_AD7177_2, 135 }; 136 137 struct ad7173_device_info { 138 const unsigned int *sinc5_data_rates; 139 unsigned int num_sinc5_data_rates; 140 unsigned int odr_start_value; 141 unsigned int num_channels; 142 unsigned int num_configs; 143 unsigned int num_inputs; 144 unsigned int clock; 145 unsigned int id; 146 char *name; 147 bool has_temp; 148 bool has_int_ref; 149 bool has_ref2; 150 u8 num_gpios; 151 }; 152 153 struct ad7173_channel_config { 154 u8 cfg_slot; 155 bool live; 156 157 /* Following fields are used to compare equality. */ 158 struct_group(config_props, 159 bool bipolar; 160 bool input_buf; 161 u8 odr; 162 u8 ref_sel; 163 ); 164 }; 165 166 struct ad7173_channel { 167 unsigned int chan_reg; 168 unsigned int ain; 169 struct ad7173_channel_config cfg; 170 }; 171 172 struct ad7173_state { 173 struct ad_sigma_delta sd; 174 const struct ad7173_device_info *info; 175 struct ad7173_channel *channels; 176 struct regulator_bulk_data regulators[3]; 177 unsigned int adc_mode; 178 unsigned int interface_mode; 179 unsigned int num_channels; 180 struct ida cfg_slots_status; 181 unsigned long long config_usage_counter; 182 unsigned long long *config_cnts; 183 struct clk *ext_clk; 184 struct clk_hw int_clk_hw; 185 #if IS_ENABLED(CONFIG_GPIOLIB) 186 struct regmap *reg_gpiocon_regmap; 187 struct gpio_regmap *gpio_regmap; 188 #endif 189 }; 190 191 static const unsigned int ad7173_sinc5_data_rates[] = { 192 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 193 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 194 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 195 }; 196 197 static const unsigned int ad7175_sinc5_data_rates[] = { 198 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 199 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 200 5000000, 2500000, 1000000, 500000, /* 8-11 */ 201 397500, 200000, 100000, 59920, /* 12-15 */ 202 49960, 20000, 16666, 10000, /* 16-19 */ 203 5000, /* 20 */ 204 }; 205 206 static const struct ad7173_device_info ad7173_device_info[] = { 207 [ID_AD7172_2] = { 208 .name = "ad7172-2", 209 .id = AD7172_2_ID, 210 .num_inputs = 5, 211 .num_channels = 4, 212 .num_configs = 4, 213 .num_gpios = 2, 214 .has_temp = true, 215 .has_int_ref = true, 216 .clock = 2 * HZ_PER_MHZ, 217 .sinc5_data_rates = ad7173_sinc5_data_rates, 218 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 219 }, 220 [ID_AD7172_4] = { 221 .id = AD7172_4_ID, 222 .num_inputs = 9, 223 .num_channels = 8, 224 .num_configs = 8, 225 .num_gpios = 4, 226 .has_temp = false, 227 .has_ref2 = true, 228 .clock = 2 * HZ_PER_MHZ, 229 .sinc5_data_rates = ad7173_sinc5_data_rates, 230 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 231 }, 232 [ID_AD7173_8] = { 233 .name = "ad7173-8", 234 .id = AD7173_ID, 235 .num_inputs = 17, 236 .num_channels = 16, 237 .num_configs = 8, 238 .num_gpios = 4, 239 .has_temp = true, 240 .has_int_ref = true, 241 .has_ref2 = true, 242 .clock = 2 * HZ_PER_MHZ, 243 .sinc5_data_rates = ad7173_sinc5_data_rates, 244 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 245 }, 246 [ID_AD7175_2] = { 247 .name = "ad7175-2", 248 .id = AD7175_2_ID, 249 .num_inputs = 5, 250 .num_channels = 4, 251 .num_configs = 4, 252 .num_gpios = 2, 253 .has_temp = true, 254 .has_int_ref = true, 255 .clock = 16 * HZ_PER_MHZ, 256 .sinc5_data_rates = ad7175_sinc5_data_rates, 257 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 258 }, 259 [ID_AD7175_8] = { 260 .id = AD7175_8_ID, 261 .num_inputs = 17, 262 .num_channels = 16, 263 .num_configs = 8, 264 .num_gpios = 4, 265 .has_temp = true, 266 .has_int_ref = true, 267 .has_ref2 = true, 268 .clock = 16 * HZ_PER_MHZ, 269 .sinc5_data_rates = ad7175_sinc5_data_rates, 270 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 271 }, 272 [ID_AD7176_2] = { 273 .name = "ad7176-2", 274 .id = AD7176_ID, 275 .num_inputs = 5, 276 .num_channels = 4, 277 .num_configs = 4, 278 .num_gpios = 2, 279 .has_temp = false, 280 .has_int_ref = true, 281 .clock = 16 * HZ_PER_MHZ, 282 .sinc5_data_rates = ad7175_sinc5_data_rates, 283 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 284 }, 285 [ID_AD7177_2] = { 286 .id = AD7177_ID, 287 .num_inputs = 5, 288 .num_channels = 4, 289 .num_configs = 4, 290 .num_gpios = 2, 291 .has_temp = true, 292 .has_int_ref = true, 293 .clock = 16 * HZ_PER_MHZ, 294 .odr_start_value = AD7177_ODR_START_VALUE, 295 .sinc5_data_rates = ad7175_sinc5_data_rates, 296 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 297 }, 298 }; 299 300 static const char *const ad7173_ref_sel_str[] = { 301 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 302 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 303 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 304 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 305 }; 306 307 static const char *const ad7173_clk_sel[] = { 308 "ext-clk", "xtal" 309 }; 310 311 #if IS_ENABLED(CONFIG_GPIOLIB) 312 313 static const struct regmap_range ad7173_range_gpio[] = { 314 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 315 }; 316 317 static const struct regmap_access_table ad7173_access_table = { 318 .yes_ranges = ad7173_range_gpio, 319 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 320 }; 321 322 static const struct regmap_config ad7173_regmap_config = { 323 .reg_bits = 8, 324 .val_bits = 16, 325 .rd_table = &ad7173_access_table, 326 .wr_table = &ad7173_access_table, 327 .read_flag_mask = BIT(6), 328 }; 329 330 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 331 unsigned int offset, unsigned int *reg, 332 unsigned int *mask) 333 { 334 *mask = AD7173_GPO_DATA(offset); 335 *reg = base; 336 return 0; 337 } 338 339 static void ad7173_gpio_disable(void *data) 340 { 341 struct ad7173_state *st = data; 342 unsigned int mask; 343 344 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 345 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 346 } 347 348 static int ad7173_gpio_init(struct ad7173_state *st) 349 { 350 struct gpio_regmap_config gpio_regmap = {}; 351 struct device *dev = &st->sd.spi->dev; 352 unsigned int mask; 353 int ret; 354 355 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 356 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 357 if (ret) 358 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 359 360 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 361 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 362 363 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 364 if (ret) 365 return ret; 366 367 gpio_regmap.parent = dev; 368 gpio_regmap.regmap = st->reg_gpiocon_regmap; 369 gpio_regmap.ngpio = st->info->num_gpios; 370 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 371 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 372 373 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 374 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 375 if (ret) 376 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 377 378 return 0; 379 } 380 #else 381 static int ad7173_gpio_init(struct ad7173_state *st) 382 { 383 return 0; 384 } 385 #endif /* CONFIG_GPIOLIB */ 386 387 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 388 { 389 return container_of(sd, struct ad7173_state, sd); 390 } 391 392 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 393 { 394 return container_of(hw, struct ad7173_state, int_clk_hw); 395 } 396 397 static void ad7173_ida_destroy(void *data) 398 { 399 struct ad7173_state *st = data; 400 401 ida_destroy(&st->cfg_slots_status); 402 } 403 404 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 405 { 406 memset64(st->config_cnts, 0, st->info->num_configs); 407 st->config_usage_counter = 0; 408 } 409 410 static struct ad7173_channel_config * 411 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 412 { 413 struct ad7173_channel_config *cfg_aux; 414 ptrdiff_t cmp_size; 415 int i; 416 417 cmp_size = sizeof_field(struct ad7173_channel_config, config_props); 418 for (i = 0; i < st->num_channels; i++) { 419 cfg_aux = &st->channels[i].cfg; 420 421 if (cfg_aux->live && 422 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size)) 423 return cfg_aux; 424 } 425 return NULL; 426 } 427 428 /* Could be replaced with a generic LRU implementation */ 429 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 430 { 431 int i, lru_position = 0; 432 433 for (i = 1; i < st->info->num_configs; i++) 434 if (st->config_cnts[i] < st->config_cnts[lru_position]) 435 lru_position = i; 436 437 for (i = 0; i < st->num_channels; i++) 438 if (st->channels[i].cfg.cfg_slot == lru_position) 439 st->channels[i].cfg.live = false; 440 441 ida_free(&st->cfg_slots_status, lru_position); 442 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 443 } 444 445 /* Could be replaced with a generic LRU implementation */ 446 static int ad7173_load_config(struct ad7173_state *st, 447 struct ad7173_channel_config *cfg) 448 { 449 unsigned int config; 450 int free_cfg_slot, ret; 451 452 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 453 st->info->num_configs - 1, GFP_KERNEL); 454 if (free_cfg_slot < 0) 455 free_cfg_slot = ad7173_free_config_slot_lru(st); 456 457 cfg->cfg_slot = free_cfg_slot; 458 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 459 460 if (cfg->bipolar) 461 config |= AD7173_SETUP_BIPOLAR; 462 463 if (cfg->input_buf) 464 config |= AD7173_SETUP_AIN_BUF_MASK; 465 466 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 467 if (ret) 468 return ret; 469 470 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 471 AD7173_FILTER_ODR0_MASK & cfg->odr); 472 } 473 474 static int ad7173_config_channel(struct ad7173_state *st, int addr) 475 { 476 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 477 struct ad7173_channel_config *live_cfg; 478 int ret; 479 480 if (!cfg->live) { 481 live_cfg = ad7173_find_live_config(st, cfg); 482 if (live_cfg) { 483 cfg->cfg_slot = live_cfg->cfg_slot; 484 } else { 485 ret = ad7173_load_config(st, cfg); 486 if (ret) 487 return ret; 488 cfg->live = true; 489 } 490 } 491 492 if (st->config_usage_counter == U64_MAX) 493 ad7173_reset_usage_cnts(st); 494 495 st->config_usage_counter++; 496 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 497 498 return 0; 499 } 500 501 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 502 { 503 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 504 unsigned int val; 505 int ret; 506 507 ret = ad7173_config_channel(st, channel); 508 if (ret) 509 return ret; 510 511 val = AD7173_CH_ENABLE | 512 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 513 st->channels[channel].ain; 514 515 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 516 } 517 518 static int ad7173_set_mode(struct ad_sigma_delta *sd, 519 enum ad_sigma_delta_mode mode) 520 { 521 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 522 523 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 524 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 525 526 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 527 } 528 529 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 530 { 531 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 532 unsigned int interface_mode = st->interface_mode; 533 int ret; 534 535 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 536 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 537 if (ret) 538 return ret; 539 540 st->interface_mode = interface_mode; 541 542 return 0; 543 } 544 545 static int ad7173_disable_all(struct ad_sigma_delta *sd) 546 { 547 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 548 int ret; 549 int i; 550 551 for (i = 0; i < st->num_channels; i++) { 552 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 553 if (ret < 0) 554 return ret; 555 } 556 557 return 0; 558 } 559 560 static struct ad_sigma_delta_info ad7173_sigma_delta_info = { 561 .set_channel = ad7173_set_channel, 562 .append_status = ad7173_append_status, 563 .disable_all = ad7173_disable_all, 564 .set_mode = ad7173_set_mode, 565 .has_registers = true, 566 .addr_shift = 0, 567 .read_mask = BIT(6), 568 .status_ch_mask = GENMASK(3, 0), 569 .data_reg = AD7173_REG_DATA, 570 }; 571 572 static int ad7173_setup(struct iio_dev *indio_dev) 573 { 574 struct ad7173_state *st = iio_priv(indio_dev); 575 struct device *dev = &st->sd.spi->dev; 576 u8 buf[AD7173_RESET_LENGTH]; 577 unsigned int id; 578 int ret; 579 580 /* reset the serial interface */ 581 memset(buf, 0xff, AD7173_RESET_LENGTH); 582 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 583 if (ret < 0) 584 return ret; 585 586 /* datasheet recommends a delay of at least 500us after reset */ 587 fsleep(500); 588 589 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 590 if (ret) 591 return ret; 592 593 id &= AD7173_ID_MASK; 594 if (id != st->info->id) 595 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 596 id, st->info->id); 597 598 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 599 st->interface_mode = 0x0; 600 601 st->config_usage_counter = 0; 602 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 603 sizeof(*st->config_cnts), GFP_KERNEL); 604 if (!st->config_cnts) 605 return -ENOMEM; 606 607 /* All channels are enabled by default after a reset */ 608 return ad7173_disable_all(&st->sd); 609 } 610 611 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 612 u8 reference_select) 613 { 614 int vref; 615 616 switch (reference_select) { 617 case AD7173_SETUP_REF_SEL_EXT_REF: 618 vref = regulator_get_voltage(st->regulators[0].consumer); 619 break; 620 621 case AD7173_SETUP_REF_SEL_EXT_REF2: 622 vref = regulator_get_voltage(st->regulators[1].consumer); 623 break; 624 625 case AD7173_SETUP_REF_SEL_INT_REF: 626 vref = AD7173_VOLTAGE_INT_REF_uV; 627 break; 628 629 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 630 vref = regulator_get_voltage(st->regulators[2].consumer); 631 break; 632 633 default: 634 return -EINVAL; 635 } 636 637 if (vref < 0) 638 return vref; 639 640 return vref / (MICRO / MILLI); 641 } 642 643 static int ad7173_read_raw(struct iio_dev *indio_dev, 644 struct iio_chan_spec const *chan, 645 int *val, int *val2, long info) 646 { 647 struct ad7173_state *st = iio_priv(indio_dev); 648 struct ad7173_channel *ch = &st->channels[chan->address]; 649 unsigned int reg; 650 u64 temp; 651 int ret; 652 653 switch (info) { 654 case IIO_CHAN_INFO_RAW: 655 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 656 if (ret < 0) 657 return ret; 658 659 /* disable channel after single conversion */ 660 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(chan->address), 2, 0); 661 if (ret < 0) 662 return ret; 663 664 return IIO_VAL_INT; 665 case IIO_CHAN_INFO_SCALE: 666 if (chan->type == IIO_TEMP) { 667 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 668 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 669 *val = temp; 670 *val2 = chan->scan_type.realbits; 671 } else { 672 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 673 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 674 } 675 return IIO_VAL_FRACTIONAL_LOG2; 676 case IIO_CHAN_INFO_OFFSET: 677 if (chan->type == IIO_TEMP) { 678 /* 0 Kelvin -> raw sample */ 679 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 680 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 681 temp <<= chan->scan_type.realbits; 682 temp = DIV_U64_ROUND_CLOSEST(temp, 683 AD7173_VOLTAGE_INT_REF_uV * 684 MILLI); 685 *val = -temp; 686 } else { 687 *val = -BIT(chan->scan_type.realbits - 1); 688 } 689 return IIO_VAL_INT; 690 case IIO_CHAN_INFO_SAMP_FREQ: 691 reg = st->channels[chan->address].cfg.odr; 692 693 *val = st->info->sinc5_data_rates[reg] / MILLI; 694 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 695 696 return IIO_VAL_INT_PLUS_MICRO; 697 default: 698 return -EINVAL; 699 } 700 } 701 702 static int ad7173_write_raw(struct iio_dev *indio_dev, 703 struct iio_chan_spec const *chan, 704 int val, int val2, long info) 705 { 706 struct ad7173_state *st = iio_priv(indio_dev); 707 struct ad7173_channel_config *cfg; 708 unsigned int freq, i, reg; 709 int ret; 710 711 ret = iio_device_claim_direct_mode(indio_dev); 712 if (ret) 713 return ret; 714 715 switch (info) { 716 case IIO_CHAN_INFO_SAMP_FREQ: 717 freq = val * MILLI + val2 / MILLI; 718 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 719 if (freq >= st->info->sinc5_data_rates[i]) 720 break; 721 722 cfg = &st->channels[chan->address].cfg; 723 cfg->odr = i; 724 725 if (!cfg->live) 726 break; 727 728 ret = ad_sd_read_reg(&st->sd, AD7173_REG_FILTER(cfg->cfg_slot), 2, ®); 729 if (ret) 730 break; 731 reg &= ~AD7173_FILTER_ODR0_MASK; 732 reg |= FIELD_PREP(AD7173_FILTER_ODR0_MASK, i); 733 ret = ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(cfg->cfg_slot), 2, reg); 734 break; 735 736 default: 737 ret = -EINVAL; 738 break; 739 } 740 741 iio_device_release_direct_mode(indio_dev); 742 return ret; 743 } 744 745 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 746 const unsigned long *scan_mask) 747 { 748 struct ad7173_state *st = iio_priv(indio_dev); 749 int i, ret; 750 751 for (i = 0; i < indio_dev->num_channels; i++) { 752 if (test_bit(i, scan_mask)) 753 ret = ad7173_set_channel(&st->sd, i); 754 else 755 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 756 if (ret < 0) 757 return ret; 758 } 759 760 return 0; 761 } 762 763 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 764 unsigned int writeval, unsigned int *readval) 765 { 766 struct ad7173_state *st = iio_priv(indio_dev); 767 u8 reg_size; 768 769 if (reg == AD7173_REG_COMMS) 770 reg_size = 1; 771 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 772 reg >= AD7173_REG_OFFSET(0)) 773 reg_size = 3; 774 else 775 reg_size = 2; 776 777 if (readval) 778 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 779 780 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 781 } 782 783 static const struct iio_info ad7173_info = { 784 .read_raw = &ad7173_read_raw, 785 .write_raw = &ad7173_write_raw, 786 .debugfs_reg_access = &ad7173_debug_reg_access, 787 .validate_trigger = ad_sd_validate_trigger, 788 .update_scan_mode = ad7173_update_scan_mode, 789 }; 790 791 static const struct iio_chan_spec ad7173_channel_template = { 792 .type = IIO_VOLTAGE, 793 .indexed = 1, 794 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 795 BIT(IIO_CHAN_INFO_SCALE), 796 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 797 .scan_type = { 798 .sign = 'u', 799 .realbits = 24, 800 .storagebits = 32, 801 .endianness = IIO_BE, 802 }, 803 }; 804 805 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 806 .type = IIO_TEMP, 807 .indexed = 1, 808 .channel = AD7173_AIN_TEMP_POS, 809 .channel2 = AD7173_AIN_TEMP_NEG, 810 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 811 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), 812 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 813 .scan_type = { 814 .sign = 'u', 815 .realbits = 24, 816 .storagebits = 32, 817 .endianness = IIO_BE, 818 }, 819 }; 820 821 static void ad7173_disable_regulators(void *data) 822 { 823 struct ad7173_state *st = data; 824 825 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 826 } 827 828 static void ad7173_clk_disable_unprepare(void *clk) 829 { 830 clk_disable_unprepare(clk); 831 } 832 833 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 834 unsigned int clk_sel) 835 { 836 int ret; 837 838 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 839 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 840 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 841 842 return ret; 843 } 844 845 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 846 unsigned long parent_rate) 847 { 848 struct ad7173_state *st = clk_hw_to_ad7173(hw); 849 850 return st->info->clock / HZ_PER_KHZ; 851 } 852 853 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 854 { 855 struct ad7173_state *st = clk_hw_to_ad7173(hw); 856 u32 clk_sel; 857 858 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 859 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 860 } 861 862 static int ad7173_clk_output_prepare(struct clk_hw *hw) 863 { 864 struct ad7173_state *st = clk_hw_to_ad7173(hw); 865 866 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 867 } 868 869 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 870 { 871 struct ad7173_state *st = clk_hw_to_ad7173(hw); 872 873 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 874 } 875 876 static const struct clk_ops ad7173_int_clk_ops = { 877 .recalc_rate = ad7173_clk_recalc_rate, 878 .is_enabled = ad7173_clk_output_is_enabled, 879 .prepare = ad7173_clk_output_prepare, 880 .unprepare = ad7173_clk_output_unprepare, 881 }; 882 883 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 884 { 885 struct ad7173_state *st = iio_priv(indio_dev); 886 struct device *dev = indio_dev->dev.parent; 887 struct fwnode_handle *fwnode = dev_fwnode(dev); 888 struct clk_init_data init = {}; 889 int ret; 890 891 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 892 return 0; 893 894 init.name = fwnode_get_name(fwnode); 895 init.ops = &ad7173_int_clk_ops; 896 897 st->int_clk_hw.init = &init; 898 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 899 if (ret) 900 return ret; 901 902 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 903 &st->int_clk_hw); 904 } 905 906 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 907 { 908 struct ad7173_channel *chans_st_arr, *chan_st_priv; 909 struct ad7173_state *st = iio_priv(indio_dev); 910 struct device *dev = indio_dev->dev.parent; 911 struct iio_chan_spec *chan_arr, *chan; 912 unsigned int ain[2], chan_index = 0; 913 int ref_sel, ret; 914 915 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 916 st->num_channels, GFP_KERNEL); 917 if (!chan_arr) 918 return -ENOMEM; 919 920 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 921 GFP_KERNEL); 922 if (!chans_st_arr) 923 return -ENOMEM; 924 925 indio_dev->channels = chan_arr; 926 st->channels = chans_st_arr; 927 928 if (st->info->has_temp) { 929 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 930 chan_st_priv = &chans_st_arr[chan_index]; 931 chan_st_priv->ain = 932 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 933 chan_arr[chan_index].channel2); 934 chan_st_priv->cfg.bipolar = false; 935 chan_st_priv->cfg.input_buf = true; 936 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 937 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 938 939 chan_index++; 940 } 941 942 device_for_each_child_node_scoped(dev, child) { 943 chan = &chan_arr[chan_index]; 944 chan_st_priv = &chans_st_arr[chan_index]; 945 ret = fwnode_property_read_u32_array(child, "diff-channels", 946 ain, ARRAY_SIZE(ain)); 947 if (ret) 948 return ret; 949 950 if (ain[0] >= st->info->num_inputs || 951 ain[1] >= st->info->num_inputs) 952 return dev_err_probe(dev, -EINVAL, 953 "Input pin number out of range for pair (%d %d).\n", 954 ain[0], ain[1]); 955 956 ret = fwnode_property_match_property_string(child, 957 "adi,reference-select", 958 ad7173_ref_sel_str, 959 ARRAY_SIZE(ad7173_ref_sel_str)); 960 if (ret < 0) 961 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 962 else 963 ref_sel = ret; 964 965 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && 966 !st->info->has_int_ref) 967 return dev_err_probe(dev, -EINVAL, 968 "Internal reference is not available on current model.\n"); 969 970 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 971 return dev_err_probe(dev, -EINVAL, 972 "External reference 2 is not available on current model.\n"); 973 974 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 975 if (ret < 0) 976 return dev_err_probe(dev, ret, 977 "Cannot use reference %u\n", ref_sel); 978 979 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 980 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 981 chan_st_priv->cfg.ref_sel = ref_sel; 982 983 *chan = ad7173_channel_template; 984 chan->address = chan_index; 985 chan->scan_index = chan_index; 986 chan->channel = ain[0]; 987 chan->channel2 = ain[1]; 988 chan->differential = true; 989 990 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 991 chan_st_priv->chan_reg = chan_index; 992 chan_st_priv->cfg.input_buf = true; 993 chan_st_priv->cfg.odr = 0; 994 995 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 996 if (chan_st_priv->cfg.bipolar) 997 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 998 999 chan_index++; 1000 } 1001 return 0; 1002 } 1003 1004 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1005 { 1006 struct ad7173_state *st = iio_priv(indio_dev); 1007 struct device *dev = indio_dev->dev.parent; 1008 unsigned int num_channels; 1009 int ret; 1010 1011 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1012 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1013 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1014 1015 /* 1016 * If a regulator is not available, it will be set to a dummy regulator. 1017 * Each channel reference is checked with regulator_get_voltage() before 1018 * setting attributes so if any channel uses a dummy supply the driver 1019 * probe will fail. 1020 */ 1021 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1022 st->regulators); 1023 if (ret) 1024 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1025 1026 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1027 if (ret) 1028 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1029 1030 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1031 if (ret) 1032 return dev_err_probe(dev, ret, 1033 "Failed to add regulators disable action\n"); 1034 1035 ret = device_property_match_property_string(dev, "clock-names", 1036 ad7173_clk_sel, 1037 ARRAY_SIZE(ad7173_clk_sel)); 1038 if (ret < 0) { 1039 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1040 AD7173_ADC_MODE_CLOCKSEL_INT); 1041 ad7173_register_clk_provider(indio_dev); 1042 } else { 1043 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1044 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1045 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]); 1046 if (IS_ERR(st->ext_clk)) 1047 return dev_err_probe(dev, PTR_ERR(st->ext_clk), 1048 "Failed to get external clock\n"); 1049 1050 ret = clk_prepare_enable(st->ext_clk); 1051 if (ret) 1052 return dev_err_probe(dev, ret, 1053 "Failed to enable external clock\n"); 1054 1055 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare, 1056 st->ext_clk); 1057 if (ret) 1058 return ret; 1059 } 1060 1061 ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy"); 1062 if (ret < 0) 1063 return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n"); 1064 1065 ad7173_sigma_delta_info.irq_line = ret; 1066 1067 num_channels = device_get_child_node_count(dev); 1068 1069 if (st->info->has_temp) 1070 num_channels++; 1071 1072 if (num_channels == 0) 1073 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1074 indio_dev->num_channels = num_channels; 1075 st->num_channels = num_channels; 1076 1077 return ad7173_fw_parse_channel_config(indio_dev); 1078 } 1079 1080 static int ad7173_probe(struct spi_device *spi) 1081 { 1082 struct device *dev = &spi->dev; 1083 struct ad7173_state *st; 1084 struct iio_dev *indio_dev; 1085 int ret; 1086 1087 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1088 if (!indio_dev) 1089 return -ENOMEM; 1090 1091 st = iio_priv(indio_dev); 1092 st->info = spi_get_device_match_data(spi); 1093 if (!st->info) 1094 return -ENODEV; 1095 1096 ida_init(&st->cfg_slots_status); 1097 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1098 if (ret) 1099 return ret; 1100 1101 indio_dev->name = st->info->name; 1102 indio_dev->modes = INDIO_DIRECT_MODE; 1103 indio_dev->info = &ad7173_info; 1104 1105 spi->mode = SPI_MODE_3; 1106 spi_setup(spi); 1107 1108 ad7173_sigma_delta_info.num_slots = st->info->num_configs; 1109 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7173_sigma_delta_info); 1110 if (ret) 1111 return ret; 1112 1113 ret = ad7173_fw_parse_device_config(indio_dev); 1114 if (ret) 1115 return ret; 1116 1117 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1118 if (ret) 1119 return ret; 1120 1121 ret = ad7173_setup(indio_dev); 1122 if (ret) 1123 return ret; 1124 1125 ret = devm_iio_device_register(dev, indio_dev); 1126 if (ret) 1127 return ret; 1128 1129 if (IS_ENABLED(CONFIG_GPIOLIB)) 1130 return ad7173_gpio_init(st); 1131 1132 return 0; 1133 } 1134 1135 static const struct of_device_id ad7173_of_match[] = { 1136 { .compatible = "adi,ad7172-2", 1137 .data = &ad7173_device_info[ID_AD7172_2]}, 1138 { .compatible = "adi,ad7172-4", 1139 .data = &ad7173_device_info[ID_AD7172_4]}, 1140 { .compatible = "adi,ad7173-8", 1141 .data = &ad7173_device_info[ID_AD7173_8]}, 1142 { .compatible = "adi,ad7175-2", 1143 .data = &ad7173_device_info[ID_AD7175_2]}, 1144 { .compatible = "adi,ad7175-8", 1145 .data = &ad7173_device_info[ID_AD7175_8]}, 1146 { .compatible = "adi,ad7176-2", 1147 .data = &ad7173_device_info[ID_AD7176_2]}, 1148 { .compatible = "adi,ad7177-2", 1149 .data = &ad7173_device_info[ID_AD7177_2]}, 1150 { } 1151 }; 1152 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1153 1154 static const struct spi_device_id ad7173_id_table[] = { 1155 { "ad7172-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7172_2]}, 1156 { "ad7172-4", (kernel_ulong_t)&ad7173_device_info[ID_AD7172_4]}, 1157 { "ad7173-8", (kernel_ulong_t)&ad7173_device_info[ID_AD7173_8]}, 1158 { "ad7175-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7175_2]}, 1159 { "ad7175-8", (kernel_ulong_t)&ad7173_device_info[ID_AD7175_8]}, 1160 { "ad7176-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7176_2]}, 1161 { "ad7177-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7177_2]}, 1162 { } 1163 }; 1164 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1165 1166 static struct spi_driver ad7173_driver = { 1167 .driver = { 1168 .name = "ad7173", 1169 .of_match_table = ad7173_of_match, 1170 }, 1171 .probe = ad7173_probe, 1172 .id_table = ad7173_id_table, 1173 }; 1174 module_spi_driver(ad7173_driver); 1175 1176 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1177 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1178 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1179 MODULE_DESCRIPTION("Analog Devices AD7172/AD7173/AD7175/AD7176 ADC driver"); 1180 MODULE_LICENSE("GPL"); 1181