1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4 5$id: http://devicetree.org/schemas/display/msm/gpu.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Adreno or Snapdragon GPUs 9 10maintainers: 11 - Rob Clark <robdclark@gmail.com> 12 13properties: 14 compatible: 15 oneOf: 16 - description: | 17 The driver is parsing the compat string for Adreno to 18 figure out the chip-id. 19 items: 20 - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' 21 - const: qcom,adreno 22 - description: | 23 The driver is parsing the compat string for Adreno to 24 figure out the gpu-id and patch level. 25 items: 26 - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' 27 - const: qcom,adreno 28 - description: | 29 The driver is parsing the compat string for Imageon to 30 figure out the gpu-id and patch level. 31 items: 32 - pattern: '^amd,imageon-200\.[0-1]$' 33 - const: amd,imageon 34 35 clocks: true 36 37 clock-names: true 38 39 reg: 40 minItems: 1 41 maxItems: 3 42 43 reg-names: 44 minItems: 1 45 maxItems: 3 46 47 interrupts: 48 maxItems: 1 49 50 interrupt-names: 51 maxItems: 1 52 53 interconnects: 54 minItems: 1 55 maxItems: 2 56 57 interconnect-names: 58 minItems: 1 59 items: 60 - const: gfx-mem 61 - const: ocmem 62 63 iommus: 64 minItems: 1 65 maxItems: 64 66 67 sram: 68 $ref: /schemas/types.yaml#/definitions/phandle-array 69 minItems: 1 70 maxItems: 4 71 items: 72 maxItems: 1 73 description: | 74 phandles to one or more reserved on-chip SRAM regions. 75 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 76 a4xx Snapdragon SoCs. See 77 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml 78 79 operating-points-v2: true 80 opp-table: 81 type: object 82 83 power-domains: 84 maxItems: 1 85 86 zap-shader: 87 type: object 88 additionalProperties: false 89 description: | 90 For a5xx and a6xx devices this node contains a memory-region that 91 points to reserved memory to store the zap shader that can be used to 92 help bring the GPU out of secure mode. 93 properties: 94 memory-region: 95 maxItems: 1 96 97 firmware-name: 98 description: | 99 Default name of the firmware to load to the remote processor. 100 101 "#cooling-cells": 102 const: 2 103 104 nvmem-cell-names: 105 maxItems: 1 106 107 nvmem-cells: 108 description: efuse registers 109 maxItems: 1 110 111 qcom,gmu: 112 $ref: /schemas/types.yaml#/definitions/phandle 113 description: | 114 For GMU attached devices a phandle to the GMU device that will 115 control the power for the GPU. 116 117 118required: 119 - compatible 120 - reg 121 - interrupts 122 123additionalProperties: false 124 125allOf: 126 - if: 127 properties: 128 compatible: 129 contains: 130 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' 131 132 then: 133 properties: 134 clocks: 135 minItems: 2 136 maxItems: 7 137 138 clock-names: 139 items: 140 anyOf: 141 - const: core 142 description: GPU Core clock 143 - const: iface 144 description: GPU Interface clock 145 - const: mem 146 description: GPU Memory clock 147 - const: mem_iface 148 description: GPU Memory Interface clock 149 - const: alt_mem_iface 150 description: GPU Alternative Memory Interface clock 151 - const: gfx3d 152 description: GPU 3D engine clock 153 - const: rbbmtimer 154 description: GPU RBBM Timer for Adreno 5xx series 155 - const: rbcpr 156 description: GPU RB Core Power Reduction clock 157 minItems: 2 158 maxItems: 7 159 160 required: 161 - clocks 162 - clock-names 163 164 - if: 165 properties: 166 compatible: 167 contains: 168 enum: 169 - qcom,adreno-610.0 170 - qcom,adreno-619.1 171 then: 172 properties: 173 clocks: 174 minItems: 6 175 maxItems: 6 176 177 clock-names: 178 items: 179 - const: core 180 description: GPU Core clock 181 - const: iface 182 description: GPU Interface clock 183 - const: mem_iface 184 description: GPU Memory Interface clock 185 - const: alt_mem_iface 186 description: GPU Alternative Memory Interface clock 187 - const: gmu 188 description: CX GMU clock 189 - const: xo 190 description: GPUCC clocksource clock 191 192 reg-names: 193 minItems: 1 194 items: 195 - const: kgsl_3d0_reg_memory 196 - const: cx_dbgc 197 198 required: 199 - clocks 200 - clock-names 201 else: 202 if: 203 properties: 204 compatible: 205 contains: 206 pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' 207 208 then: # Starting with A6xx, the clocks are usually defined in the GMU node 209 properties: 210 clocks: false 211 clock-names: false 212 213 reg-names: 214 minItems: 1 215 items: 216 - const: kgsl_3d0_reg_memory 217 - const: cx_mem 218 - const: cx_dbgc 219 220examples: 221 - | 222 223 // Example a3xx/4xx: 224 225 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 226 #include <dt-bindings/clock/qcom,rpmcc.h> 227 #include <dt-bindings/interrupt-controller/irq.h> 228 #include <dt-bindings/interrupt-controller/arm-gic.h> 229 230 gpu: gpu@fdb00000 { 231 compatible = "qcom,adreno-330.2", "qcom,adreno"; 232 233 reg = <0xfdb00000 0x10000>; 234 reg-names = "kgsl_3d0_reg_memory"; 235 236 clock-names = "core", "iface", "mem_iface"; 237 clocks = <&mmcc OXILI_GFX3D_CLK>, 238 <&mmcc OXILICX_AHB_CLK>, 239 <&mmcc OXILICX_AXI_CLK>; 240 241 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 242 interrupt-names = "kgsl_3d0_irq"; 243 244 sram = <&gpu_sram>; 245 power-domains = <&mmcc OXILICX_GDSC>; 246 operating-points-v2 = <&gpu_opp_table>; 247 iommus = <&gpu_iommu 0>; 248 #cooling-cells = <2>; 249 }; 250 251 ocmem@fdd00000 { 252 compatible = "qcom,msm8974-ocmem"; 253 254 reg = <0xfdd00000 0x2000>, 255 <0xfec00000 0x180000>; 256 reg-names = "ctrl", "mem"; 257 258 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 259 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 260 clock-names = "core", "iface"; 261 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges = <0 0xfec00000 0x100000>; 265 266 gpu_sram: gpu-sram@0 { 267 reg = <0x0 0x100000>; 268 }; 269 }; 270 - | 271 272 // Example a6xx (with GMU): 273 274 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 275 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 276 #include <dt-bindings/power/qcom-rpmpd.h> 277 #include <dt-bindings/interrupt-controller/irq.h> 278 #include <dt-bindings/interrupt-controller/arm-gic.h> 279 #include <dt-bindings/interconnect/qcom,sdm845.h> 280 281 reserved-memory { 282 #address-cells = <2>; 283 #size-cells = <2>; 284 285 zap_shader_region: gpu@8f200000 { 286 compatible = "shared-dma-pool"; 287 reg = <0x0 0x90b00000 0x0 0xa00000>; 288 no-map; 289 }; 290 }; 291 292 gpu@5000000 { 293 compatible = "qcom,adreno-630.2", "qcom,adreno"; 294 295 reg = <0x5000000 0x40000>, <0x509e000 0x10>; 296 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 297 298 #cooling-cells = <2>; 299 300 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 301 302 iommus = <&adreno_smmu 0>; 303 304 operating-points-v2 = <&gpu_opp_table>; 305 306 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; 307 interconnect-names = "gfx-mem"; 308 309 qcom,gmu = <&gmu>; 310 311 gpu_opp_table: opp-table { 312 compatible = "operating-points-v2"; 313 314 opp-430000000 { 315 opp-hz = /bits/ 64 <430000000>; 316 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 317 opp-peak-kBps = <5412000>; 318 }; 319 320 opp-355000000 { 321 opp-hz = /bits/ 64 <355000000>; 322 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 323 opp-peak-kBps = <3072000>; 324 }; 325 326 opp-267000000 { 327 opp-hz = /bits/ 64 <267000000>; 328 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 329 opp-peak-kBps = <3072000>; 330 }; 331 332 opp-180000000 { 333 opp-hz = /bits/ 64 <180000000>; 334 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 335 opp-peak-kBps = <1804000>; 336 }; 337 }; 338 339 zap-shader { 340 memory-region = <&zap_shader_region>; 341 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; 342 }; 343 }; 344