1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * SM8450 interconnect IDs 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2021, Linaro Limited 7 */ 8 9 #ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H 10 #define __DRIVERS_INTERCONNECT_QCOM_SM8450_H 11 12 #define SM8550_MASTER_A1NOC_SNOC 0 13 #define SM8550_MASTER_A2NOC_SNOC 1 14 #define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2 15 #define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 3 16 #define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 4 17 #define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 5 18 #define SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP 6 19 #define SM8550_MASTER_APPSS_PROC 7 20 #define SM8550_MASTER_CAMNOC_HF 8 21 #define SM8550_MASTER_CAMNOC_HF_CAM_IFE_0 9 22 #define SM8550_MASTER_CAMNOC_HF_CAM_IFE_1 10 23 #define SM8550_MASTER_CAMNOC_HF_CAM_IFE_2 11 24 #define SM8550_MASTER_CAMNOC_ICP 12 25 #define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0 13 26 #define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1 14 27 #define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2 15 28 #define SM8550_MASTER_CAMNOC_SF 16 29 #define SM8550_MASTER_CAMNOC_SF_CAM_IFE_0 17 30 #define SM8550_MASTER_CAMNOC_SF_CAM_IFE_1 18 31 #define SM8550_MASTER_CAMNOC_SF_CAM_IFE_2 19 32 #define SM8550_MASTER_CDSP_HCP 20 33 #define SM8550_MASTER_CDSP_PROC 21 34 #define SM8550_MASTER_CNOC_CFG 22 35 #define SM8550_MASTER_CNOC_MNOC_CFG 23 36 #define SM8550_MASTER_COMPUTE_NOC 24 37 #define SM8550_MASTER_CRYPTO 25 38 #define SM8550_MASTER_GEM_NOC_CNOC 26 39 #define SM8550_MASTER_GEM_NOC_PCIE_SNOC 27 40 #define SM8550_MASTER_GFX3D 28 41 #define SM8550_MASTER_GIC 29 42 #define SM8550_MASTER_GIC_AHB 30 43 #define SM8550_MASTER_GPU_TCU 31 44 #define SM8550_MASTER_IPA 32 45 #define SM8550_MASTER_LLCC 33 46 #define SM8550_MASTER_LLCC_CAM_IFE_0 34 47 #define SM8550_MASTER_LLCC_CAM_IFE_1 35 48 #define SM8550_MASTER_LLCC_CAM_IFE_2 36 49 #define SM8550_MASTER_LLCC_DISP 37 50 #define SM8550_MASTER_LPASS_GEM_NOC 38 51 #define SM8550_MASTER_LPASS_LPINOC 39 52 #define SM8550_MASTER_LPASS_PROC 40 53 #define SM8550_MASTER_LPIAON_NOC 41 54 #define SM8550_MASTER_MDP 42 55 #define SM8550_MASTER_MDP_DISP 43 56 #define SM8550_MASTER_MNOC_HF_MEM_NOC 44 57 #define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 45 58 #define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 46 59 #define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 47 60 #define SM8550_MASTER_MNOC_HF_MEM_NOC_DISP 48 61 #define SM8550_MASTER_MNOC_SF_MEM_NOC 49 62 #define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 50 63 #define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 51 64 #define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 52 65 #define SM8550_MASTER_MSS_PROC 53 66 #define SM8550_MASTER_PCIE_0 54 67 #define SM8550_MASTER_PCIE_1 55 68 #define SM8550_MASTER_PCIE_ANOC_CFG 56 69 #define SM8550_MASTER_QDSS_BAM 57 70 #define SM8550_MASTER_QDSS_ETR 58 71 #define SM8550_MASTER_QDSS_ETR_1 59 72 #define SM8550_MASTER_QSPI_0 60 73 #define SM8550_MASTER_QUP_1 61 74 #define SM8550_MASTER_QUP_2 62 75 #define SM8550_MASTER_QUP_CORE_0 63 76 #define SM8550_MASTER_QUP_CORE_1 64 77 #define SM8550_MASTER_QUP_CORE_2 65 78 #define SM8550_MASTER_SDCC_2 66 79 #define SM8550_MASTER_SDCC_4 67 80 #define SM8550_MASTER_SNOC_GC_MEM_NOC 68 81 #define SM8550_MASTER_SNOC_SF_MEM_NOC 69 82 #define SM8550_MASTER_SP 70 83 #define SM8550_MASTER_SYS_TCU 71 84 #define SM8550_MASTER_UFS_MEM 72 85 #define SM8550_MASTER_USB3_0 73 86 #define SM8550_MASTER_VIDEO 74 87 #define SM8550_MASTER_VIDEO_CV_PROC 75 88 #define SM8550_MASTER_VIDEO_PROC 76 89 #define SM8550_MASTER_VIDEO_V_PROC 77 90 #define SM8550_SLAVE_A1NOC_SNOC 78 91 #define SM8550_SLAVE_A2NOC_SNOC 79 92 #define SM8550_SLAVE_AHB2PHY_NORTH 80 93 #define SM8550_SLAVE_AHB2PHY_SOUTH 81 94 #define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 82 95 #define SM8550_SLAVE_AOSS 83 96 #define SM8550_SLAVE_APPSS 84 97 #define SM8550_SLAVE_BOOT_IMEM 85 98 #define SM8550_SLAVE_CAMERA_CFG 86 99 #define SM8550_SLAVE_CDSP_MEM_NOC 87 100 #define SM8550_SLAVE_CLK_CTL 88 101 #define SM8550_SLAVE_CNOC_CFG 89 102 #define SM8550_SLAVE_CNOC_MNOC_CFG 90 103 #define SM8550_SLAVE_CNOC_MSS 91 104 #define SM8550_SLAVE_CPR_NSPCX 92 105 #define SM8550_SLAVE_CRYPTO_0_CFG 93 106 #define SM8550_SLAVE_CX_RDPM 94 107 #define SM8550_SLAVE_DDRSS_CFG 95 108 #define SM8550_SLAVE_DISPLAY_CFG 96 109 #define SM8550_SLAVE_EBI1 97 110 #define SM8550_SLAVE_EBI1_CAM_IFE_0 98 111 #define SM8550_SLAVE_EBI1_CAM_IFE_1 99 112 #define SM8550_SLAVE_EBI1_CAM_IFE_2 100 113 #define SM8550_SLAVE_EBI1_DISP 101 114 #define SM8550_SLAVE_GEM_NOC_CNOC 102 115 #define SM8550_SLAVE_GFX3D_CFG 103 116 #define SM8550_SLAVE_I2C 104 117 #define SM8550_SLAVE_IMEM 105 118 #define SM8550_SLAVE_IMEM_CFG 106 119 #define SM8550_SLAVE_IPA_CFG 107 120 #define SM8550_SLAVE_IPC_ROUTER_CFG 108 121 #define SM8550_SLAVE_LLCC 109 122 #define SM8550_SLAVE_LLCC_CAM_IFE_0 110 123 #define SM8550_SLAVE_LLCC_CAM_IFE_1 111 124 #define SM8550_SLAVE_LLCC_CAM_IFE_2 112 125 #define SM8550_SLAVE_LLCC_DISP 113 126 #define SM8550_SLAVE_LPASS_GEM_NOC 114 127 #define SM8550_SLAVE_LPASS_QTB_CFG 115 128 #define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 116 129 #define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 117 130 #define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 118 131 #define SM8550_SLAVE_MNOC_HF_MEM_NOC 119 132 #define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 120 133 #define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 121 134 #define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 122 135 #define SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP 123 136 #define SM8550_SLAVE_MNOC_SF_MEM_NOC 124 137 #define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 125 138 #define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 126 139 #define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 127 140 #define SM8550_SLAVE_MX_RDPM 128 141 #define SM8550_SLAVE_NSP_QTB_CFG 129 142 #define SM8550_SLAVE_PCIE_0 130 143 #define SM8550_SLAVE_PCIE_0_CFG 131 144 #define SM8550_SLAVE_PCIE_1 132 145 #define SM8550_SLAVE_PCIE_1_CFG 133 146 #define SM8550_SLAVE_PCIE_ANOC_CFG 134 147 #define SM8550_SLAVE_PDM 135 148 #define SM8550_SLAVE_PIMEM_CFG 136 149 #define SM8550_SLAVE_PRNG 137 150 #define SM8550_SLAVE_QDSS_CFG 138 151 #define SM8550_SLAVE_QDSS_STM 139 152 #define SM8550_SLAVE_QSPI_0 140 153 #define SM8550_SLAVE_QUP_1 141 154 #define SM8550_SLAVE_QUP_2 142 155 #define SM8550_SLAVE_QUP_CORE_0 143 156 #define SM8550_SLAVE_QUP_CORE_1 144 157 #define SM8550_SLAVE_QUP_CORE_2 145 158 #define SM8550_SLAVE_RBCPR_CX_CFG 146 159 #define SM8550_SLAVE_RBCPR_MMCX_CFG 147 160 #define SM8550_SLAVE_RBCPR_MXA_CFG 148 161 #define SM8550_SLAVE_RBCPR_MXC_CFG 149 162 #define SM8550_SLAVE_SDCC_2 150 163 #define SM8550_SLAVE_SDCC_4 151 164 #define SM8550_SLAVE_SERVICE_MNOC 152 165 #define SM8550_SLAVE_SERVICE_PCIE_ANOC 153 166 #define SM8550_SLAVE_SNOC_GEM_NOC_GC 154 167 #define SM8550_SLAVE_SNOC_GEM_NOC_SF 155 168 #define SM8550_SLAVE_SPSS_CFG 156 169 #define SM8550_SLAVE_TCSR 157 170 #define SM8550_SLAVE_TCU 158 171 #define SM8550_SLAVE_TLMM 159 172 #define SM8550_SLAVE_TME_CFG 160 173 #define SM8550_SLAVE_UFS_MEM_CFG 161 174 #define SM8550_SLAVE_USB3_0 162 175 #define SM8550_SLAVE_VENUS_CFG 163 176 #define SM8550_SLAVE_VSENSE_CTRL_CFG 164 177 178 #endif 179