1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2011 Jamie Iles 4 * 5 * All enquiries to support@picochip.com 6 */ 7 #include <linux/acpi.h> 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 24 #include "gpiolib-acpi.h" 25 26 #define GPIO_SWPORTA_DR 0x00 27 #define GPIO_SWPORTA_DDR 0x04 28 #define GPIO_SWPORTB_DR 0x0c 29 #define GPIO_SWPORTB_DDR 0x10 30 #define GPIO_SWPORTC_DR 0x18 31 #define GPIO_SWPORTC_DDR 0x1c 32 #define GPIO_SWPORTD_DR 0x24 33 #define GPIO_SWPORTD_DDR 0x28 34 #define GPIO_INTEN 0x30 35 #define GPIO_INTMASK 0x34 36 #define GPIO_INTTYPE_LEVEL 0x38 37 #define GPIO_INT_POLARITY 0x3c 38 #define GPIO_INTSTATUS 0x40 39 #define GPIO_PORTA_DEBOUNCE 0x48 40 #define GPIO_PORTA_EOI 0x4c 41 #define GPIO_EXT_PORTA 0x50 42 #define GPIO_EXT_PORTB 0x54 43 #define GPIO_EXT_PORTC 0x58 44 #define GPIO_EXT_PORTD 0x5c 45 46 #define DWAPB_DRIVER_NAME "gpio-dwapb" 47 #define DWAPB_MAX_PORTS 4 48 #define DWAPB_MAX_GPIOS 32 49 50 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ 51 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ 52 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ 53 54 #define GPIO_REG_OFFSET_V1 0 55 #define GPIO_REG_OFFSET_V2 1 56 #define GPIO_REG_OFFSET_MASK BIT(0) 57 58 #define GPIO_INTMASK_V2 0x44 59 #define GPIO_INTTYPE_LEVEL_V2 0x34 60 #define GPIO_INT_POLARITY_V2 0x38 61 #define GPIO_INTSTATUS_V2 0x3c 62 #define GPIO_PORTA_EOI_V2 0x40 63 64 #define DWAPB_NR_CLOCKS 2 65 66 struct dwapb_gpio; 67 68 struct dwapb_port_property { 69 struct fwnode_handle *fwnode; 70 unsigned int idx; 71 unsigned int ngpio; 72 unsigned int gpio_base; 73 int irq[DWAPB_MAX_GPIOS]; 74 }; 75 76 struct dwapb_platform_data { 77 struct dwapb_port_property *properties; 78 unsigned int nports; 79 }; 80 81 #ifdef CONFIG_PM_SLEEP 82 /* Store GPIO context across system-wide suspend/resume transitions */ 83 struct dwapb_context { 84 u32 data; 85 u32 dir; 86 u32 ext; 87 u32 int_en; 88 u32 int_mask; 89 u32 int_type; 90 u32 int_pol; 91 u32 int_deb; 92 u32 wake_en; 93 }; 94 #endif 95 96 struct dwapb_gpio_port_irqchip { 97 unsigned int nr_irqs; 98 unsigned int irq[DWAPB_MAX_GPIOS]; 99 }; 100 101 struct dwapb_gpio_port { 102 struct gpio_chip gc; 103 struct dwapb_gpio_port_irqchip *pirq; 104 struct dwapb_gpio *gpio; 105 #ifdef CONFIG_PM_SLEEP 106 struct dwapb_context *ctx; 107 #endif 108 unsigned int idx; 109 }; 110 #define to_dwapb_gpio(_gc) \ 111 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) 112 113 struct dwapb_gpio { 114 struct device *dev; 115 void __iomem *regs; 116 struct dwapb_gpio_port *ports; 117 unsigned int nr_ports; 118 unsigned int flags; 119 struct reset_control *rst; 120 struct clk_bulk_data clks[DWAPB_NR_CLOCKS]; 121 }; 122 123 static inline u32 gpio_reg_v2_convert(unsigned int offset) 124 { 125 switch (offset) { 126 case GPIO_INTMASK: 127 return GPIO_INTMASK_V2; 128 case GPIO_INTTYPE_LEVEL: 129 return GPIO_INTTYPE_LEVEL_V2; 130 case GPIO_INT_POLARITY: 131 return GPIO_INT_POLARITY_V2; 132 case GPIO_INTSTATUS: 133 return GPIO_INTSTATUS_V2; 134 case GPIO_PORTA_EOI: 135 return GPIO_PORTA_EOI_V2; 136 } 137 138 return offset; 139 } 140 141 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) 142 { 143 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) 144 return gpio_reg_v2_convert(offset); 145 146 return offset; 147 } 148 149 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) 150 { 151 struct gpio_chip *gc = &gpio->ports[0].gc; 152 void __iomem *reg_base = gpio->regs; 153 154 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); 155 } 156 157 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, 158 u32 val) 159 { 160 struct gpio_chip *gc = &gpio->ports[0].gc; 161 void __iomem *reg_base = gpio->regs; 162 163 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); 164 } 165 166 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) 167 { 168 struct dwapb_gpio_port *port; 169 int i; 170 171 for (i = 0; i < gpio->nr_ports; i++) { 172 port = &gpio->ports[i]; 173 if (port->idx == offs / DWAPB_MAX_GPIOS) 174 return port; 175 } 176 177 return NULL; 178 } 179 180 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) 181 { 182 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); 183 struct gpio_chip *gc; 184 u32 pol; 185 int val; 186 187 if (!port) 188 return; 189 gc = &port->gc; 190 191 pol = dwapb_read(gpio, GPIO_INT_POLARITY); 192 /* Just read the current value right out of the data register */ 193 val = gc->get(gc, offs % DWAPB_MAX_GPIOS); 194 if (val) 195 pol &= ~BIT(offs); 196 else 197 pol |= BIT(offs); 198 199 dwapb_write(gpio, GPIO_INT_POLARITY, pol); 200 } 201 202 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) 203 { 204 struct gpio_chip *gc = &gpio->ports[0].gc; 205 unsigned long irq_status; 206 irq_hw_number_t hwirq; 207 208 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); 209 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { 210 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); 211 u32 irq_type = irq_get_trigger_type(gpio_irq); 212 213 generic_handle_irq(gpio_irq); 214 215 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 216 dwapb_toggle_trigger(gpio, hwirq); 217 } 218 219 return irq_status; 220 } 221 222 static void dwapb_irq_handler(struct irq_desc *desc) 223 { 224 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); 225 struct irq_chip *chip = irq_desc_get_chip(desc); 226 227 chained_irq_enter(chip, desc); 228 dwapb_do_irq(gpio); 229 chained_irq_exit(chip, desc); 230 } 231 232 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) 233 { 234 return IRQ_RETVAL(dwapb_do_irq(dev_id)); 235 } 236 237 static void dwapb_irq_ack(struct irq_data *d) 238 { 239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 240 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 241 u32 val = BIT(irqd_to_hwirq(d)); 242 unsigned long flags; 243 244 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 245 dwapb_write(gpio, GPIO_PORTA_EOI, val); 246 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 247 } 248 249 static void dwapb_irq_mask(struct irq_data *d) 250 { 251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 252 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 253 irq_hw_number_t hwirq = irqd_to_hwirq(d); 254 unsigned long flags; 255 u32 val; 256 257 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 258 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); 259 dwapb_write(gpio, GPIO_INTMASK, val); 260 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 261 262 gpiochip_disable_irq(gc, hwirq); 263 } 264 265 static void dwapb_irq_unmask(struct irq_data *d) 266 { 267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 269 irq_hw_number_t hwirq = irqd_to_hwirq(d); 270 unsigned long flags; 271 u32 val; 272 273 gpiochip_enable_irq(gc, hwirq); 274 275 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 276 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); 277 dwapb_write(gpio, GPIO_INTMASK, val); 278 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 279 } 280 281 static void dwapb_irq_enable(struct irq_data *d) 282 { 283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 284 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 285 unsigned long flags; 286 u32 val; 287 288 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 289 val = dwapb_read(gpio, GPIO_INTEN); 290 val |= BIT(irqd_to_hwirq(d)); 291 dwapb_write(gpio, GPIO_INTEN, val); 292 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 293 } 294 295 static void dwapb_irq_disable(struct irq_data *d) 296 { 297 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 298 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 299 unsigned long flags; 300 u32 val; 301 302 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 303 val = dwapb_read(gpio, GPIO_INTEN); 304 val &= ~BIT(irqd_to_hwirq(d)); 305 dwapb_write(gpio, GPIO_INTEN, val); 306 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 307 } 308 309 static int dwapb_irq_set_type(struct irq_data *d, u32 type) 310 { 311 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 312 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 313 irq_hw_number_t bit = irqd_to_hwirq(d); 314 unsigned long level, polarity, flags; 315 316 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 317 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 318 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); 319 320 switch (type) { 321 case IRQ_TYPE_EDGE_BOTH: 322 level |= BIT(bit); 323 dwapb_toggle_trigger(gpio, bit); 324 break; 325 case IRQ_TYPE_EDGE_RISING: 326 level |= BIT(bit); 327 polarity |= BIT(bit); 328 break; 329 case IRQ_TYPE_EDGE_FALLING: 330 level |= BIT(bit); 331 polarity &= ~BIT(bit); 332 break; 333 case IRQ_TYPE_LEVEL_HIGH: 334 level &= ~BIT(bit); 335 polarity |= BIT(bit); 336 break; 337 case IRQ_TYPE_LEVEL_LOW: 338 level &= ~BIT(bit); 339 polarity &= ~BIT(bit); 340 break; 341 } 342 343 if (type & IRQ_TYPE_LEVEL_MASK) 344 irq_set_handler_locked(d, handle_level_irq); 345 else if (type & IRQ_TYPE_EDGE_BOTH) 346 irq_set_handler_locked(d, handle_edge_irq); 347 348 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); 349 if (type != IRQ_TYPE_EDGE_BOTH) 350 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); 351 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 352 353 return 0; 354 } 355 356 #ifdef CONFIG_PM_SLEEP 357 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) 358 { 359 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 360 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 361 struct dwapb_context *ctx = gpio->ports[0].ctx; 362 irq_hw_number_t bit = irqd_to_hwirq(d); 363 364 if (enable) 365 ctx->wake_en |= BIT(bit); 366 else 367 ctx->wake_en &= ~BIT(bit); 368 369 return 0; 370 } 371 #else 372 #define dwapb_irq_set_wake NULL 373 #endif 374 375 static const struct irq_chip dwapb_irq_chip = { 376 .name = DWAPB_DRIVER_NAME, 377 .irq_ack = dwapb_irq_ack, 378 .irq_mask = dwapb_irq_mask, 379 .irq_unmask = dwapb_irq_unmask, 380 .irq_set_type = dwapb_irq_set_type, 381 .irq_enable = dwapb_irq_enable, 382 .irq_disable = dwapb_irq_disable, 383 .irq_set_wake = dwapb_irq_set_wake, 384 .flags = IRQCHIP_IMMUTABLE, 385 GPIOCHIP_IRQ_RESOURCE_HELPERS, 386 }; 387 388 static int dwapb_gpio_set_debounce(struct gpio_chip *gc, 389 unsigned offset, unsigned debounce) 390 { 391 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 392 struct dwapb_gpio *gpio = port->gpio; 393 unsigned long flags, val_deb; 394 unsigned long mask = BIT(offset); 395 396 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 397 398 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 399 if (debounce) 400 val_deb |= mask; 401 else 402 val_deb &= ~mask; 403 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); 404 405 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 406 407 return 0; 408 } 409 410 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, 411 unsigned long config) 412 { 413 u32 debounce; 414 415 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 416 return -ENOTSUPP; 417 418 debounce = pinconf_to_config_argument(config); 419 return dwapb_gpio_set_debounce(gc, offset, debounce); 420 } 421 422 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq, 423 struct dwapb_port_property *pp) 424 { 425 int i; 426 427 /* Group all available IRQs into an array of parental IRQs. */ 428 for (i = 0; i < pp->ngpio; ++i) { 429 if (!pp->irq[i]) 430 continue; 431 432 pirq->irq[pirq->nr_irqs++] = pp->irq[i]; 433 } 434 435 return pirq->nr_irqs ? 0 : -ENOENT; 436 } 437 438 static void dwapb_configure_irqs(struct dwapb_gpio *gpio, 439 struct dwapb_gpio_port *port, 440 struct dwapb_port_property *pp) 441 { 442 struct dwapb_gpio_port_irqchip *pirq; 443 struct gpio_chip *gc = &port->gc; 444 struct gpio_irq_chip *girq; 445 int err; 446 447 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); 448 if (!pirq) 449 return; 450 451 if (dwapb_convert_irqs(pirq, pp)) { 452 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); 453 goto err_kfree_pirq; 454 } 455 456 girq = &gc->irq; 457 girq->handler = handle_bad_irq; 458 girq->default_type = IRQ_TYPE_NONE; 459 460 port->pirq = pirq; 461 462 /* 463 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO 464 * IRQ lane shared between several devices. In that case the parental 465 * IRQ has to be handled in the shared way so to be properly delivered 466 * to all the connected devices. 467 */ 468 if (has_acpi_companion(gpio->dev)) { 469 girq->num_parents = 0; 470 girq->parents = NULL; 471 girq->parent_handler = NULL; 472 473 err = devm_request_irq(gpio->dev, pp->irq[0], 474 dwapb_irq_handler_mfd, 475 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio); 476 if (err) { 477 dev_err(gpio->dev, "error requesting IRQ\n"); 478 goto err_kfree_pirq; 479 } 480 } else { 481 girq->num_parents = pirq->nr_irqs; 482 girq->parents = pirq->irq; 483 girq->parent_handler_data = gpio; 484 girq->parent_handler = dwapb_irq_handler; 485 } 486 487 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip); 488 489 return; 490 491 err_kfree_pirq: 492 devm_kfree(gpio->dev, pirq); 493 } 494 495 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, 496 struct dwapb_port_property *pp, 497 unsigned int offs) 498 { 499 struct dwapb_gpio_port *port; 500 void __iomem *dat, *set, *dirout; 501 int err; 502 503 port = &gpio->ports[offs]; 504 port->gpio = gpio; 505 port->idx = pp->idx; 506 507 #ifdef CONFIG_PM_SLEEP 508 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); 509 if (!port->ctx) 510 return -ENOMEM; 511 #endif 512 513 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; 514 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; 515 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; 516 517 /* This registers 32 GPIO lines per port */ 518 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, 519 NULL, 0); 520 if (err) { 521 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", 522 port->idx); 523 return err; 524 } 525 526 port->gc.fwnode = pp->fwnode; 527 port->gc.ngpio = pp->ngpio; 528 port->gc.base = pp->gpio_base; 529 530 /* Only port A support debounce */ 531 if (pp->idx == 0) 532 port->gc.set_config = dwapb_gpio_set_config; 533 534 /* Only port A can provide interrupts in all configurations of the IP */ 535 if (pp->idx == 0) 536 dwapb_configure_irqs(gpio, port, pp); 537 538 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); 539 if (err) { 540 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", 541 port->idx); 542 return err; 543 } 544 545 return 0; 546 } 547 548 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode, 549 struct dwapb_port_property *pp) 550 { 551 int irq, j; 552 553 for (j = 0; j < pp->ngpio; j++) { 554 if (has_acpi_companion(dev)) 555 irq = platform_get_irq_optional(to_platform_device(dev), j); 556 else 557 irq = fwnode_irq_get(fwnode, j); 558 if (irq > 0) 559 pp->irq[j] = irq; 560 } 561 } 562 563 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev) 564 { 565 struct fwnode_handle *fwnode; 566 struct dwapb_platform_data *pdata; 567 struct dwapb_port_property *pp; 568 int nports; 569 int i; 570 571 nports = device_get_child_node_count(dev); 572 if (nports == 0) 573 return ERR_PTR(-ENODEV); 574 575 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 576 if (!pdata) 577 return ERR_PTR(-ENOMEM); 578 579 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); 580 if (!pdata->properties) 581 return ERR_PTR(-ENOMEM); 582 583 pdata->nports = nports; 584 585 i = 0; 586 device_for_each_child_node(dev, fwnode) { 587 pp = &pdata->properties[i++]; 588 pp->fwnode = fwnode; 589 590 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || 591 pp->idx >= DWAPB_MAX_PORTS) { 592 dev_err(dev, 593 "missing/invalid port index for port%d\n", i); 594 fwnode_handle_put(fwnode); 595 return ERR_PTR(-EINVAL); 596 } 597 598 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) && 599 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) { 600 dev_info(dev, 601 "failed to get number of gpios for port%d\n", 602 i); 603 pp->ngpio = DWAPB_MAX_GPIOS; 604 } 605 606 pp->gpio_base = -1; 607 608 /* For internal use only, new platforms mustn't exercise this */ 609 if (is_software_node(fwnode)) 610 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base); 611 612 /* 613 * Only port A can provide interrupts in all configurations of 614 * the IP. 615 */ 616 if (pp->idx == 0) 617 dwapb_get_irq(dev, fwnode, pp); 618 } 619 620 return pdata; 621 } 622 623 static void dwapb_assert_reset(void *data) 624 { 625 struct dwapb_gpio *gpio = data; 626 627 reset_control_assert(gpio->rst); 628 } 629 630 static int dwapb_get_reset(struct dwapb_gpio *gpio) 631 { 632 int err; 633 634 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); 635 if (IS_ERR(gpio->rst)) 636 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst), 637 "Cannot get reset descriptor\n"); 638 639 err = reset_control_deassert(gpio->rst); 640 if (err) { 641 dev_err(gpio->dev, "Cannot deassert reset lane\n"); 642 return err; 643 } 644 645 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); 646 } 647 648 static void dwapb_disable_clks(void *data) 649 { 650 struct dwapb_gpio *gpio = data; 651 652 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 653 } 654 655 static int dwapb_get_clks(struct dwapb_gpio *gpio) 656 { 657 int err; 658 659 /* Optional bus and debounce clocks */ 660 gpio->clks[0].id = "bus"; 661 gpio->clks[1].id = "db"; 662 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, 663 gpio->clks); 664 if (err) 665 return dev_err_probe(gpio->dev, err, 666 "Cannot get APB/Debounce clocks\n"); 667 668 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); 669 if (err) { 670 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); 671 return err; 672 } 673 674 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); 675 } 676 677 static const struct of_device_id dwapb_of_match[] = { 678 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1}, 679 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, 680 { /* Sentinel */ } 681 }; 682 MODULE_DEVICE_TABLE(of, dwapb_of_match); 683 684 static const struct acpi_device_id dwapb_acpi_match[] = { 685 {"HISI0181", GPIO_REG_OFFSET_V1}, 686 {"APMC0D07", GPIO_REG_OFFSET_V1}, 687 {"APMC0D81", GPIO_REG_OFFSET_V2}, 688 { } 689 }; 690 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); 691 692 static int dwapb_gpio_probe(struct platform_device *pdev) 693 { 694 unsigned int i; 695 struct dwapb_gpio *gpio; 696 int err; 697 struct dwapb_platform_data *pdata; 698 struct device *dev = &pdev->dev; 699 700 pdata = dwapb_gpio_get_pdata(dev); 701 if (IS_ERR(pdata)) 702 return PTR_ERR(pdata); 703 704 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 705 if (!gpio) 706 return -ENOMEM; 707 708 gpio->dev = &pdev->dev; 709 gpio->nr_ports = pdata->nports; 710 711 err = dwapb_get_reset(gpio); 712 if (err) 713 return err; 714 715 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, 716 sizeof(*gpio->ports), GFP_KERNEL); 717 if (!gpio->ports) 718 return -ENOMEM; 719 720 gpio->regs = devm_platform_ioremap_resource(pdev, 0); 721 if (IS_ERR(gpio->regs)) 722 return PTR_ERR(gpio->regs); 723 724 err = dwapb_get_clks(gpio); 725 if (err) 726 return err; 727 728 gpio->flags = (uintptr_t)device_get_match_data(dev); 729 730 for (i = 0; i < gpio->nr_ports; i++) { 731 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); 732 if (err) 733 return err; 734 } 735 736 platform_set_drvdata(pdev, gpio); 737 738 return 0; 739 } 740 741 #ifdef CONFIG_PM_SLEEP 742 static int dwapb_gpio_suspend(struct device *dev) 743 { 744 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 745 struct gpio_chip *gc = &gpio->ports[0].gc; 746 unsigned long flags; 747 int i; 748 749 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 750 for (i = 0; i < gpio->nr_ports; i++) { 751 unsigned int offset; 752 unsigned int idx = gpio->ports[i].idx; 753 struct dwapb_context *ctx = gpio->ports[i].ctx; 754 755 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 756 ctx->dir = dwapb_read(gpio, offset); 757 758 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 759 ctx->data = dwapb_read(gpio, offset); 760 761 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 762 ctx->ext = dwapb_read(gpio, offset); 763 764 /* Only port A can provide interrupts */ 765 if (idx == 0) { 766 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); 767 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); 768 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); 769 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 770 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 771 772 /* Mask out interrupts */ 773 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); 774 } 775 } 776 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 777 778 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 779 780 return 0; 781 } 782 783 static int dwapb_gpio_resume(struct device *dev) 784 { 785 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 786 struct gpio_chip *gc = &gpio->ports[0].gc; 787 unsigned long flags; 788 int i, err; 789 790 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); 791 if (err) { 792 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); 793 return err; 794 } 795 796 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 797 for (i = 0; i < gpio->nr_ports; i++) { 798 unsigned int offset; 799 unsigned int idx = gpio->ports[i].idx; 800 struct dwapb_context *ctx = gpio->ports[i].ctx; 801 802 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 803 dwapb_write(gpio, offset, ctx->data); 804 805 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 806 dwapb_write(gpio, offset, ctx->dir); 807 808 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 809 dwapb_write(gpio, offset, ctx->ext); 810 811 /* Only port A can provide interrupts */ 812 if (idx == 0) { 813 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); 814 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); 815 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); 816 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); 817 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); 818 819 /* Clear out spurious interrupts */ 820 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); 821 } 822 } 823 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 824 825 return 0; 826 } 827 #endif 828 829 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, 830 dwapb_gpio_resume); 831 832 static struct platform_driver dwapb_gpio_driver = { 833 .driver = { 834 .name = DWAPB_DRIVER_NAME, 835 .pm = &dwapb_gpio_pm_ops, 836 .of_match_table = dwapb_of_match, 837 .acpi_match_table = dwapb_acpi_match, 838 }, 839 .probe = dwapb_gpio_probe, 840 }; 841 842 module_platform_driver(dwapb_gpio_driver); 843 844 MODULE_LICENSE("GPL"); 845 MODULE_AUTHOR("Jamie Iles"); 846 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); 847 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME); 848