1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Atheros QCA83xx switch family 8 9maintainers: 10 - John Crispin <john@phrozen.org> 11 12description: 13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode 14 describing a port needs to have a valid phandle referencing the internal PHY 15 it is connected to. This is because there is no N:N mapping of port and PHY 16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in 17 the switch node and declare the phandle for the port, referencing the internal 18 PHY it is connected to. In this config, an internal mdio-bus is registered and 19 the MDIO master is used for communication. Mixed external and internal 20 mdio-bus configurations are not supported by the hardware. 21 Each phy has at most 3 LEDs connected and can be declared 22 using the standard LEDs structure. 23 24properties: 25 compatible: 26 oneOf: 27 - enum: 28 - qca,qca8327 29 - qca,qca8328 30 - qca,qca8334 31 - qca,qca8337 32 description: | 33 qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package 34 qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package 35 qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package 36 qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package 37 38 reg: 39 maxItems: 1 40 41 reset-gpios: 42 description: 43 GPIO to be used to reset the whole device 44 maxItems: 1 45 46 qca,ignore-power-on-sel: 47 $ref: /schemas/types.yaml#/definitions/flag 48 description: 49 Ignore power-on pin strapping to configure LED open-drain or EEPROM 50 presence. This is needed for devices with incorrect configuration or when 51 the OEM has decided not to use pin strapping and falls back to SW regs. 52 53 qca,led-open-drain: 54 $ref: /schemas/types.yaml#/definitions/flag 55 description: 56 Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to 57 be set, otherwise the driver will fail at probe. This is required if the 58 OEM does not use pin strapping to set this mode and prefers to set it 59 using SW regs. The pin strappings related to LED open-drain mode are 60 B68 on the QCA832x and B49 on the QCA833x. 61 62 mdio: 63 $ref: /schemas/net/mdio.yaml# 64 unevaluatedProperties: false 65 description: Qca8k switch have an internal mdio to access switch port. 66 If this is not present, the legacy mapping is used and the 67 internal mdio access is used. 68 With the legacy mapping the reg corresponding to the internal 69 mdio is the switch reg with an offset of -1. 70 71$ref: dsa.yaml# 72 73patternProperties: 74 "^(ethernet-)?ports$": 75 type: object 76 patternProperties: 77 "^(ethernet-)?port@[0-6]$": 78 type: object 79 description: Ethernet switch ports 80 81 $ref: dsa-port.yaml# 82 83 properties: 84 qca,sgmii-rxclk-falling-edge: 85 $ref: /schemas/types.yaml#/definitions/flag 86 description: 87 Set the receive clock phase to falling edge. Mostly commonly used on 88 the QCA8327 with CPU port 0 set to SGMII. 89 90 qca,sgmii-txclk-falling-edge: 91 $ref: /schemas/types.yaml#/definitions/flag 92 description: 93 Set the transmit clock phase to falling edge. 94 95 qca,sgmii-enable-pll: 96 $ref: /schemas/types.yaml#/definitions/flag 97 description: 98 For SGMII CPU port, explicitly enable PLL, TX and RX chain along with 99 Signal Detection. On the QCA8327 this should not be enabled, otherwise 100 the SGMII port will not initialize. When used on the QCA8337, revision 3 101 or greater, a warning will be displayed. When the CPU port is set to 102 SGMII on the QCA8337, it is advised to set this unless a communication 103 issue is observed. 104 105 unevaluatedProperties: false 106 107oneOf: 108 - required: 109 - ports 110 - required: 111 - ethernet-ports 112 113required: 114 - compatible 115 - reg 116 117unevaluatedProperties: false 118 119examples: 120 - | 121 #include <dt-bindings/gpio/gpio.h> 122 #include <dt-bindings/leds/common.h> 123 124 mdio { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 128 external_phy_port1: ethernet-phy@0 { 129 reg = <0>; 130 }; 131 132 external_phy_port2: ethernet-phy@1 { 133 reg = <1>; 134 }; 135 136 external_phy_port3: ethernet-phy@2 { 137 reg = <2>; 138 }; 139 140 external_phy_port4: ethernet-phy@3 { 141 reg = <3>; 142 }; 143 144 external_phy_port5: ethernet-phy@4 { 145 reg = <4>; 146 }; 147 148 switch@10 { 149 compatible = "qca,qca8337"; 150 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; 151 reg = <0x10>; 152 153 ports { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 port@0 { 158 reg = <0>; 159 ethernet = <&gmac1>; 160 phy-mode = "rgmii"; 161 162 fixed-link { 163 speed = <1000>; 164 full-duplex; 165 }; 166 }; 167 168 port@1 { 169 reg = <1>; 170 label = "lan1"; 171 phy-handle = <&external_phy_port1>; 172 }; 173 174 port@2 { 175 reg = <2>; 176 label = "lan2"; 177 phy-handle = <&external_phy_port2>; 178 }; 179 180 port@3 { 181 reg = <3>; 182 label = "lan3"; 183 phy-handle = <&external_phy_port3>; 184 }; 185 186 port@4 { 187 reg = <4>; 188 label = "lan4"; 189 phy-handle = <&external_phy_port4>; 190 }; 191 192 port@5 { 193 reg = <5>; 194 label = "wan"; 195 phy-handle = <&external_phy_port5>; 196 }; 197 }; 198 }; 199 }; 200 - | 201 #include <dt-bindings/gpio/gpio.h> 202 203 mdio { 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 switch@10 { 208 compatible = "qca,qca8337"; 209 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; 210 reg = <0x10>; 211 212 ports { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 216 port@0 { 217 reg = <0>; 218 ethernet = <&gmac1>; 219 phy-mode = "rgmii"; 220 221 fixed-link { 222 speed = <1000>; 223 full-duplex; 224 }; 225 }; 226 227 port@1 { 228 reg = <1>; 229 label = "lan1"; 230 phy-mode = "internal"; 231 phy-handle = <&internal_phy_port1>; 232 233 leds { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 237 led@0 { 238 reg = <0>; 239 color = <LED_COLOR_ID_WHITE>; 240 function = LED_FUNCTION_LAN; 241 default-state = "keep"; 242 }; 243 244 led@1 { 245 reg = <1>; 246 color = <LED_COLOR_ID_AMBER>; 247 function = LED_FUNCTION_LAN; 248 default-state = "keep"; 249 }; 250 }; 251 }; 252 253 port@2 { 254 reg = <2>; 255 label = "lan2"; 256 phy-mode = "internal"; 257 phy-handle = <&internal_phy_port2>; 258 }; 259 260 port@3 { 261 reg = <3>; 262 label = "lan3"; 263 phy-mode = "internal"; 264 phy-handle = <&internal_phy_port3>; 265 }; 266 267 port@4 { 268 reg = <4>; 269 label = "lan4"; 270 phy-mode = "internal"; 271 phy-handle = <&internal_phy_port4>; 272 }; 273 274 port@5 { 275 reg = <5>; 276 label = "wan"; 277 phy-mode = "internal"; 278 phy-handle = <&internal_phy_port5>; 279 }; 280 281 port@6 { 282 reg = <0>; 283 ethernet = <&gmac1>; 284 phy-mode = "sgmii"; 285 286 qca,sgmii-rxclk-falling-edge; 287 288 fixed-link { 289 speed = <1000>; 290 full-duplex; 291 }; 292 }; 293 }; 294 295 mdio { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 internal_phy_port1: ethernet-phy@0 { 300 reg = <0>; 301 }; 302 303 internal_phy_port2: ethernet-phy@1 { 304 reg = <1>; 305 }; 306 307 internal_phy_port3: ethernet-phy@2 { 308 reg = <2>; 309 }; 310 311 internal_phy_port4: ethernet-phy@3 { 312 reg = <3>; 313 }; 314 315 internal_phy_port5: ethernet-phy@4 { 316 reg = <4>; 317 }; 318 }; 319 }; 320 }; 321