1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_REG_DEFS_H_ 7 #define _XE_REG_DEFS_H_ 8 9 #include "compat-i915-headers/i915_reg_defs.h" 10 11 /** 12 * struct xe_reg - Register definition 13 * 14 * Register defintion to be used by the individual register. Although the same 15 * definition is used for xe_reg and xe_reg_mcr, they use different internal 16 * APIs for accesses. 17 */ 18 struct xe_reg { 19 union { 20 struct { 21 /** @addr: address */ 22 u32 addr:28; 23 /** 24 * @masked: register is "masked", with upper 16bits used 25 * to identify the bits that are updated on the lower 26 * bits 27 */ 28 u32 masked:1; 29 /** 30 * @mcr: register is multicast/replicated in the 31 * hardware and needs special handling. Any register 32 * with this set should also use a type of xe_reg_mcr_t. 33 * It's only here so the few places that deal with MCR 34 * registers specially (xe_sr.c) and tests using the raw 35 * value can inspect it. 36 */ 37 u32 mcr:1; 38 /** 39 * @ext: access MMIO extension space for current register. 40 */ 41 u32 ext:1; 42 }; 43 /** @raw: Raw value with both address and options */ 44 u32 raw; 45 }; 46 }; 47 48 /** 49 * struct xe_reg_mcr - MCR register definition 50 * 51 * MCR register is the same as a regular register, but uses another type since 52 * the internal API used for accessing them is different: it's never correct to 53 * use regular MMIO access. 54 */ 55 struct xe_reg_mcr { 56 /** @__reg: The register */ 57 struct xe_reg __reg; 58 }; 59 60 61 /** 62 * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the 63 * written bits on the lower 16 bits. 64 * 65 * It only applies to registers explicitly marked in bspec with 66 * "Access: Masked". Registers with this option can have write operations to 67 * specific lower bits by setting the corresponding upper bits. Other bits will 68 * not be affected. This allows register writes without needing a RMW cycle and 69 * without caching in software the register value. 70 * 71 * Example: a write with value 0x00010001 will set bit 0 and all other bits 72 * retain their previous values. 73 * 74 * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER() 75 */ 76 #define XE_REG_OPTION_MASKED .masked = 1 77 78 /** 79 * XE_REG_INITIALIZER - Initializer for xe_reg_t. 80 * @r_: Register offset 81 * @...: Additional options like access mode. See struct xe_reg for available 82 * options. 83 * 84 * Register field is mandatory, and additional options may be passed as 85 * arguments. Usually ``XE_REG()`` should be preferred since it creates an 86 * object of the right type. However when initializing static const storage, 87 * where a compound statement is not allowed, this can be used instead. 88 */ 89 #define XE_REG_INITIALIZER(r_, ...) { .addr = r_, __VA_ARGS__ } 90 91 92 /** 93 * XE_REG - Create a struct xe_reg from offset and additional flags 94 * @r_: Register offset 95 * @...: Additional options like access mode. See struct xe_reg for available 96 * options. 97 */ 98 #define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__)) 99 100 /** 101 * XE_REG_EXT - Create a struct xe_reg from extension offset and additional 102 * flags 103 * @r_: Register extension offset 104 * @...: Additional options like access mode. See struct xe_reg for available 105 * options. 106 */ 107 #define XE_REG_EXT(r_, ...) \ 108 ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .ext = 1)) 109 110 /** 111 * XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags 112 * @r_: Register offset 113 * @...: Additional options like access mode. See struct xe_reg for available 114 * options. 115 */ 116 #define XE_REG_MCR(r_, ...) ((const struct xe_reg_mcr){ \ 117 .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \ 118 }) 119 120 #endif 121