1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J722S SoC Family 4 * 5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/ti,sci_pm_domain.h> 12 13#include "k3-am62p5.dtsi" 14 15/ { 16 model = "Texas Instruments K3 J722S SoC"; 17 compatible = "ti,j722s"; 18 19 cbass_main: bus@f0000 { 20 compatible = "simple-bus"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 25 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 26 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 27 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 28 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 29 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 30 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 31 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 32 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ 33 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 34 <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ 35 <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ 36 <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ 37 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 38 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 39 <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ 40 <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ 41 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 42 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ 43 <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ 44 <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ 45 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ 46 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 47 <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ 48 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 49 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 50 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 51 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 52 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ 53 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 54 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ 55 <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ 56 <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ 57 <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ 58 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ 59 <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ 60 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 61 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 62 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ 63 64 /* MCU Domain Range */ 65 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 66 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, 67 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, 68 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, 69 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, 70 71 /* Wakeup Domain Range */ 72 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, 73 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 74 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, 75 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, 76 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; 77 }; 78}; 79 80/* Main domain overrides */ 81 82&inta_main_dmss { 83 ti,interrupt-ranges = <7 71 21>; 84}; 85 86&oc_sram { 87 reg = <0x00 0x70000000 0x00 0x40000>; 88 ranges = <0x00 0x00 0x70000000 0x40000>; 89}; 90