1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/device.h> 27 #include <linux/dmi.h> 28 #include <linux/gfp.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <linux/libata.h> 32 #include <linux/ahci-remap.h> 33 #include <linux/io-64-nonatomic-lo-hi.h> 34 #include "ahci.h" 35 36 #define DRV_NAME "ahci" 37 #define DRV_VERSION "3.0" 38 39 enum { 40 AHCI_PCI_BAR_STA2X11 = 0, 41 AHCI_PCI_BAR_CAVIUM = 0, 42 AHCI_PCI_BAR_LOONGSON = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46 }; 47 48 enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_ign_iferr, 52 board_ahci_low_power, 53 board_ahci_no_debounce_delay, 54 board_ahci_nomsi, 55 board_ahci_noncq, 56 board_ahci_nosntf, 57 board_ahci_yes_fbs, 58 59 /* board IDs for specific chipsets in alphabetical order */ 60 board_ahci_al, 61 board_ahci_avn, 62 board_ahci_mcp65, 63 board_ahci_mcp77, 64 board_ahci_mcp89, 65 board_ahci_mv, 66 board_ahci_sb600, 67 board_ahci_sb700, /* for SB700 and SB800 */ 68 board_ahci_vt8251, 69 70 /* 71 * board IDs for Intel chipsets that support more than 6 ports 72 * *and* end up needing the PCS quirk. 73 */ 74 board_ahci_pcs7, 75 76 /* aliases */ 77 board_ahci_mcp_linux = board_ahci_mcp65, 78 board_ahci_mcp67 = board_ahci_mcp65, 79 board_ahci_mcp73 = board_ahci_mcp65, 80 board_ahci_mcp79 = board_ahci_mcp77, 81 }; 82 83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 84 static void ahci_remove_one(struct pci_dev *dev); 85 static void ahci_shutdown_one(struct pci_dev *dev); 86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 91 static bool is_mcp89_apple(struct pci_dev *pdev); 92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 93 unsigned long deadline); 94 #ifdef CONFIG_PM 95 static int ahci_pci_device_runtime_suspend(struct device *dev); 96 static int ahci_pci_device_runtime_resume(struct device *dev); 97 #ifdef CONFIG_PM_SLEEP 98 static int ahci_pci_device_suspend(struct device *dev); 99 static int ahci_pci_device_resume(struct device *dev); 100 #endif 101 #endif /* CONFIG_PM */ 102 103 static struct scsi_host_template ahci_sht = { 104 AHCI_SHT("ahci"), 105 }; 106 107 static struct ata_port_operations ahci_vt8251_ops = { 108 .inherits = &ahci_ops, 109 .hardreset = ahci_vt8251_hardreset, 110 }; 111 112 static struct ata_port_operations ahci_p5wdh_ops = { 113 .inherits = &ahci_ops, 114 .hardreset = ahci_p5wdh_hardreset, 115 }; 116 117 static struct ata_port_operations ahci_avn_ops = { 118 .inherits = &ahci_ops, 119 .hardreset = ahci_avn_hardreset, 120 }; 121 122 static const struct ata_port_info ahci_port_info[] = { 123 /* by features */ 124 [board_ahci] = { 125 .flags = AHCI_FLAG_COMMON, 126 .pio_mask = ATA_PIO4, 127 .udma_mask = ATA_UDMA6, 128 .port_ops = &ahci_ops, 129 }, 130 [board_ahci_ign_iferr] = { 131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 132 .flags = AHCI_FLAG_COMMON, 133 .pio_mask = ATA_PIO4, 134 .udma_mask = ATA_UDMA6, 135 .port_ops = &ahci_ops, 136 }, 137 [board_ahci_low_power] = { 138 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY), 139 .flags = AHCI_FLAG_COMMON, 140 .pio_mask = ATA_PIO4, 141 .udma_mask = ATA_UDMA6, 142 .port_ops = &ahci_ops, 143 }, 144 [board_ahci_no_debounce_delay] = { 145 .flags = AHCI_FLAG_COMMON, 146 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, 147 .pio_mask = ATA_PIO4, 148 .udma_mask = ATA_UDMA6, 149 .port_ops = &ahci_ops, 150 }, 151 [board_ahci_nomsi] = { 152 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 153 .flags = AHCI_FLAG_COMMON, 154 .pio_mask = ATA_PIO4, 155 .udma_mask = ATA_UDMA6, 156 .port_ops = &ahci_ops, 157 }, 158 [board_ahci_noncq] = { 159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 160 .flags = AHCI_FLAG_COMMON, 161 .pio_mask = ATA_PIO4, 162 .udma_mask = ATA_UDMA6, 163 .port_ops = &ahci_ops, 164 }, 165 [board_ahci_nosntf] = { 166 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 167 .flags = AHCI_FLAG_COMMON, 168 .pio_mask = ATA_PIO4, 169 .udma_mask = ATA_UDMA6, 170 .port_ops = &ahci_ops, 171 }, 172 [board_ahci_yes_fbs] = { 173 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 174 .flags = AHCI_FLAG_COMMON, 175 .pio_mask = ATA_PIO4, 176 .udma_mask = ATA_UDMA6, 177 .port_ops = &ahci_ops, 178 }, 179 /* by chipsets */ 180 [board_ahci_al] = { 181 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 182 .flags = AHCI_FLAG_COMMON, 183 .pio_mask = ATA_PIO4, 184 .udma_mask = ATA_UDMA6, 185 .port_ops = &ahci_ops, 186 }, 187 [board_ahci_avn] = { 188 .flags = AHCI_FLAG_COMMON, 189 .pio_mask = ATA_PIO4, 190 .udma_mask = ATA_UDMA6, 191 .port_ops = &ahci_avn_ops, 192 }, 193 [board_ahci_mcp65] = { 194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 195 AHCI_HFLAG_YES_NCQ), 196 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 197 .pio_mask = ATA_PIO4, 198 .udma_mask = ATA_UDMA6, 199 .port_ops = &ahci_ops, 200 }, 201 [board_ahci_mcp77] = { 202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 203 .flags = AHCI_FLAG_COMMON, 204 .pio_mask = ATA_PIO4, 205 .udma_mask = ATA_UDMA6, 206 .port_ops = &ahci_ops, 207 }, 208 [board_ahci_mcp89] = { 209 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 210 .flags = AHCI_FLAG_COMMON, 211 .pio_mask = ATA_PIO4, 212 .udma_mask = ATA_UDMA6, 213 .port_ops = &ahci_ops, 214 }, 215 [board_ahci_mv] = { 216 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 217 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 218 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 219 .pio_mask = ATA_PIO4, 220 .udma_mask = ATA_UDMA6, 221 .port_ops = &ahci_ops, 222 }, 223 [board_ahci_sb600] = { 224 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 225 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 226 AHCI_HFLAG_32BIT_ONLY), 227 .flags = AHCI_FLAG_COMMON, 228 .pio_mask = ATA_PIO4, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &ahci_pmp_retry_srst_ops, 231 }, 232 [board_ahci_sb700] = { /* for SB700 and SB800 */ 233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 234 .flags = AHCI_FLAG_COMMON, 235 .pio_mask = ATA_PIO4, 236 .udma_mask = ATA_UDMA6, 237 .port_ops = &ahci_pmp_retry_srst_ops, 238 }, 239 [board_ahci_vt8251] = { 240 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 241 .flags = AHCI_FLAG_COMMON, 242 .pio_mask = ATA_PIO4, 243 .udma_mask = ATA_UDMA6, 244 .port_ops = &ahci_vt8251_ops, 245 }, 246 [board_ahci_pcs7] = { 247 .flags = AHCI_FLAG_COMMON, 248 .pio_mask = ATA_PIO4, 249 .udma_mask = ATA_UDMA6, 250 .port_ops = &ahci_ops, 251 }, 252 }; 253 254 static const struct pci_device_id ahci_pci_tbl[] = { 255 /* Intel */ 256 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 257 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 258 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 259 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 260 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 261 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 262 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 263 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 264 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 265 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 266 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 267 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 268 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/ 269 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 270 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 271 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 272 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 273 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 274 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 275 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 276 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 277 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */ 278 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */ 279 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */ 280 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */ 281 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */ 282 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 283 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */ 284 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 285 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 286 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 287 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 288 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 289 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 290 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 291 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 292 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 293 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */ 294 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 295 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */ 296 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 311 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 312 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 313 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 314 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 315 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 316 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 317 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 318 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */ 319 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 320 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */ 321 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 322 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 323 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 324 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 325 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 326 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 327 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 328 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */ 329 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 330 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 331 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 332 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */ 333 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 334 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 335 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */ 336 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 337 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */ 338 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 339 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */ 340 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 341 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */ 342 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */ 343 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */ 344 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */ 345 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */ 346 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */ 347 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */ 348 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */ 349 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */ 350 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */ 351 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 352 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 353 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 354 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 355 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 356 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 359 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 360 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 361 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 362 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 363 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 364 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 365 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 366 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 367 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/ 368 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */ 369 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */ 370 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */ 371 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */ 372 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */ 373 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */ 374 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */ 375 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 376 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 377 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 378 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 379 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 380 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 381 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 382 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 383 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 384 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */ 385 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */ 386 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */ 387 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */ 388 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 389 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */ 390 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 391 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */ 392 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 393 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */ 394 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 395 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */ 396 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */ 397 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */ 398 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */ 399 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 400 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */ 401 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 402 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 403 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */ 404 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 405 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 406 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 407 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 408 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 409 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 410 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 411 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 412 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 413 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 414 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 415 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 416 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */ 417 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */ 418 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */ 419 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */ 420 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ 421 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ 422 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ 423 424 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 425 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 426 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 427 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 428 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 429 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 430 /* May need to update quirk_jmicron_async_suspend() for additions */ 431 432 /* ATI */ 433 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 434 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 435 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 436 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 437 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 438 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 439 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 440 441 /* Amazon's Annapurna Labs support */ 442 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 443 .class = PCI_CLASS_STORAGE_SATA_AHCI, 444 .class_mask = 0xffffff, 445 board_ahci_al }, 446 /* AMD */ 447 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 448 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ 449 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 450 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */ 451 /* AMD is using RAID class only for ahci controllers */ 452 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 453 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 454 455 /* Dell S140/S150 */ 456 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, 457 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 458 459 /* VIA */ 460 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 461 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 462 463 /* NVIDIA */ 464 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 465 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 466 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 467 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 468 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 469 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 470 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 471 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 472 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 473 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 474 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 475 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 476 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 477 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 478 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 479 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 480 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 481 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 482 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 483 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 484 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 485 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 486 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 487 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 488 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 489 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 490 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 491 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 492 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 493 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 494 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 495 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 496 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 497 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 498 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 499 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 500 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 501 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 502 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 503 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 504 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 505 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 506 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 507 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 508 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 509 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 510 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 511 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 512 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 513 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 514 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 515 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 516 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 517 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 518 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 519 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 520 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 521 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 522 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 523 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 524 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 525 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 526 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 527 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 528 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 529 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 530 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 531 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 532 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 533 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 534 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 535 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 536 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 537 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 538 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 539 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 540 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 541 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 542 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 543 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 544 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 545 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 546 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 547 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 548 549 /* SiS */ 550 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 551 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 552 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 553 554 /* ST Microelectronics */ 555 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 556 557 /* Marvell */ 558 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 559 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 561 .class = PCI_CLASS_STORAGE_SATA_AHCI, 562 .class_mask = 0xffffff, 563 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 565 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 566 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 567 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 568 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 570 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 572 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 574 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 576 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 577 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 578 .driver_data = board_ahci_yes_fbs }, 579 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 580 .driver_data = board_ahci_yes_fbs }, 581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 582 .driver_data = board_ahci_yes_fbs }, 583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 584 .driver_data = board_ahci_yes_fbs }, 585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235), 586 .driver_data = board_ahci_no_debounce_delay }, 587 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 588 .driver_data = board_ahci_yes_fbs }, 589 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 590 .driver_data = board_ahci_yes_fbs }, 591 592 /* Promise */ 593 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 594 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 595 596 /* Asmedia */ 597 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 598 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 599 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 600 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 601 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 602 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 603 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */ 604 605 /* 606 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 607 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 608 */ 609 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 610 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 611 612 /* Enmotus */ 613 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 614 615 /* Loongson */ 616 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 617 618 /* Generic, PCI class code for AHCI */ 619 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 620 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 621 622 { } /* terminate list */ 623 }; 624 625 static const struct dev_pm_ops ahci_pci_pm_ops = { 626 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 627 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 628 ahci_pci_device_runtime_resume, NULL) 629 }; 630 631 static struct pci_driver ahci_pci_driver = { 632 .name = DRV_NAME, 633 .id_table = ahci_pci_tbl, 634 .probe = ahci_init_one, 635 .remove = ahci_remove_one, 636 .shutdown = ahci_shutdown_one, 637 .driver = { 638 .pm = &ahci_pci_pm_ops, 639 }, 640 }; 641 642 #if IS_ENABLED(CONFIG_PATA_MARVELL) 643 static int marvell_enable; 644 #else 645 static int marvell_enable = 1; 646 #endif 647 module_param(marvell_enable, int, 0644); 648 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 649 650 static int mobile_lpm_policy = -1; 651 module_param(mobile_lpm_policy, int, 0644); 652 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 653 654 static void ahci_pci_save_initial_config(struct pci_dev *pdev, 655 struct ahci_host_priv *hpriv) 656 { 657 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 658 dev_info(&pdev->dev, "JMB361 has only one port\n"); 659 hpriv->saved_port_map = 1; 660 } 661 662 /* 663 * Temporary Marvell 6145 hack: PATA port presence 664 * is asserted through the standard AHCI port 665 * presence register, as bit 4 (counting from 0) 666 */ 667 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 668 if (pdev->device == 0x6121) 669 hpriv->mask_port_map = 0x3; 670 else 671 hpriv->mask_port_map = 0xf; 672 dev_info(&pdev->dev, 673 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 674 } 675 676 ahci_save_initial_config(&pdev->dev, hpriv); 677 } 678 679 static void ahci_pci_init_controller(struct ata_host *host) 680 { 681 struct ahci_host_priv *hpriv = host->private_data; 682 struct pci_dev *pdev = to_pci_dev(host->dev); 683 void __iomem *port_mmio; 684 u32 tmp; 685 int mv; 686 687 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 688 if (pdev->device == 0x6121) 689 mv = 2; 690 else 691 mv = 4; 692 port_mmio = __ahci_port_base(hpriv, mv); 693 694 writel(0, port_mmio + PORT_IRQ_MASK); 695 696 /* clear port IRQ */ 697 tmp = readl(port_mmio + PORT_IRQ_STAT); 698 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 699 if (tmp) 700 writel(tmp, port_mmio + PORT_IRQ_STAT); 701 } 702 703 ahci_init_controller(host); 704 } 705 706 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 707 unsigned long deadline) 708 { 709 struct ata_port *ap = link->ap; 710 struct ahci_host_priv *hpriv = ap->host->private_data; 711 bool online; 712 int rc; 713 714 hpriv->stop_engine(ap); 715 716 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 717 deadline, &online, NULL); 718 719 hpriv->start_engine(ap); 720 721 /* vt8251 doesn't clear BSY on signature FIS reception, 722 * request follow-up softreset. 723 */ 724 return online ? -EAGAIN : rc; 725 } 726 727 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 728 unsigned long deadline) 729 { 730 struct ata_port *ap = link->ap; 731 struct ahci_port_priv *pp = ap->private_data; 732 struct ahci_host_priv *hpriv = ap->host->private_data; 733 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 734 struct ata_taskfile tf; 735 bool online; 736 int rc; 737 738 hpriv->stop_engine(ap); 739 740 /* clear D2H reception area to properly wait for D2H FIS */ 741 ata_tf_init(link->device, &tf); 742 tf.status = ATA_BUSY; 743 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 744 745 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 746 deadline, &online, NULL); 747 748 hpriv->start_engine(ap); 749 750 /* The pseudo configuration device on SIMG4726 attached to 751 * ASUS P5W-DH Deluxe doesn't send signature FIS after 752 * hardreset if no device is attached to the first downstream 753 * port && the pseudo device locks up on SRST w/ PMP==0. To 754 * work around this, wait for !BSY only briefly. If BSY isn't 755 * cleared, perform CLO and proceed to IDENTIFY (achieved by 756 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 757 * 758 * Wait for two seconds. Devices attached to downstream port 759 * which can't process the following IDENTIFY after this will 760 * have to be reset again. For most cases, this should 761 * suffice while making probing snappish enough. 762 */ 763 if (online) { 764 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 765 ahci_check_ready); 766 if (rc) 767 ahci_kick_engine(ap); 768 } 769 return rc; 770 } 771 772 /* 773 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 774 * 775 * It has been observed with some SSDs that the timing of events in the 776 * link synchronization phase can leave the port in a state that can not 777 * be recovered by a SATA-hard-reset alone. The failing signature is 778 * SStatus.DET stuck at 1 ("Device presence detected but Phy 779 * communication not established"). It was found that unloading and 780 * reloading the driver when this problem occurs allows the drive 781 * connection to be recovered (DET advanced to 0x3). The critical 782 * component of reloading the driver is that the port state machines are 783 * reset by bouncing "port enable" in the AHCI PCS configuration 784 * register. So, reproduce that effect by bouncing a port whenever we 785 * see DET==1 after a reset. 786 */ 787 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 788 unsigned long deadline) 789 { 790 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 791 struct ata_port *ap = link->ap; 792 struct ahci_port_priv *pp = ap->private_data; 793 struct ahci_host_priv *hpriv = ap->host->private_data; 794 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 795 unsigned long tmo = deadline - jiffies; 796 struct ata_taskfile tf; 797 bool online; 798 int rc, i; 799 800 hpriv->stop_engine(ap); 801 802 for (i = 0; i < 2; i++) { 803 u16 val; 804 u32 sstatus; 805 int port = ap->port_no; 806 struct ata_host *host = ap->host; 807 struct pci_dev *pdev = to_pci_dev(host->dev); 808 809 /* clear D2H reception area to properly wait for D2H FIS */ 810 ata_tf_init(link->device, &tf); 811 tf.status = ATA_BUSY; 812 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 813 814 rc = sata_link_hardreset(link, timing, deadline, &online, 815 ahci_check_ready); 816 817 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 818 (sstatus & 0xf) != 1) 819 break; 820 821 ata_link_info(link, "avn bounce port%d\n", port); 822 823 pci_read_config_word(pdev, 0x92, &val); 824 val &= ~(1 << port); 825 pci_write_config_word(pdev, 0x92, val); 826 ata_msleep(ap, 1000); 827 val |= 1 << port; 828 pci_write_config_word(pdev, 0x92, val); 829 deadline += tmo; 830 } 831 832 hpriv->start_engine(ap); 833 834 if (online) 835 *class = ahci_dev_classify(ap); 836 837 return rc; 838 } 839 840 841 #ifdef CONFIG_PM 842 static void ahci_pci_disable_interrupts(struct ata_host *host) 843 { 844 struct ahci_host_priv *hpriv = host->private_data; 845 void __iomem *mmio = hpriv->mmio; 846 u32 ctl; 847 848 /* AHCI spec rev1.1 section 8.3.3: 849 * Software must disable interrupts prior to requesting a 850 * transition of the HBA to D3 state. 851 */ 852 ctl = readl(mmio + HOST_CTL); 853 ctl &= ~HOST_IRQ_EN; 854 writel(ctl, mmio + HOST_CTL); 855 readl(mmio + HOST_CTL); /* flush */ 856 } 857 858 static int ahci_pci_device_runtime_suspend(struct device *dev) 859 { 860 struct pci_dev *pdev = to_pci_dev(dev); 861 struct ata_host *host = pci_get_drvdata(pdev); 862 863 ahci_pci_disable_interrupts(host); 864 return 0; 865 } 866 867 static int ahci_pci_device_runtime_resume(struct device *dev) 868 { 869 struct pci_dev *pdev = to_pci_dev(dev); 870 struct ata_host *host = pci_get_drvdata(pdev); 871 int rc; 872 873 rc = ahci_reset_controller(host); 874 if (rc) 875 return rc; 876 ahci_pci_init_controller(host); 877 return 0; 878 } 879 880 #ifdef CONFIG_PM_SLEEP 881 static int ahci_pci_device_suspend(struct device *dev) 882 { 883 struct pci_dev *pdev = to_pci_dev(dev); 884 struct ata_host *host = pci_get_drvdata(pdev); 885 struct ahci_host_priv *hpriv = host->private_data; 886 887 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 888 dev_err(&pdev->dev, 889 "BIOS update required for suspend/resume\n"); 890 return -EIO; 891 } 892 893 ahci_pci_disable_interrupts(host); 894 ata_host_suspend(host, PMSG_SUSPEND); 895 return 0; 896 } 897 898 static int ahci_pci_device_resume(struct device *dev) 899 { 900 struct pci_dev *pdev = to_pci_dev(dev); 901 struct ata_host *host = pci_get_drvdata(pdev); 902 int rc; 903 904 /* Apple BIOS helpfully mangles the registers on resume */ 905 if (is_mcp89_apple(pdev)) 906 ahci_mcp89_apple_enable(pdev); 907 908 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 909 rc = ahci_reset_controller(host); 910 if (rc) 911 return rc; 912 913 ahci_pci_init_controller(host); 914 } 915 916 ata_host_resume(host); 917 918 return 0; 919 } 920 #endif 921 922 #endif /* CONFIG_PM */ 923 924 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 925 { 926 const int dma_bits = using_dac ? 64 : 32; 927 int rc; 928 929 /* 930 * If the device fixup already set the dma_mask to some non-standard 931 * value, don't extend it here. This happens on STA2X11, for example. 932 * 933 * XXX: manipulating the DMA mask from platform code is completely 934 * bogus, platform code should use dev->bus_dma_limit instead.. 935 */ 936 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 937 return 0; 938 939 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 940 if (rc) 941 dev_err(&pdev->dev, "DMA enable failed\n"); 942 return rc; 943 } 944 945 static void ahci_pci_print_info(struct ata_host *host) 946 { 947 struct pci_dev *pdev = to_pci_dev(host->dev); 948 u16 cc; 949 const char *scc_s; 950 951 pci_read_config_word(pdev, 0x0a, &cc); 952 if (cc == PCI_CLASS_STORAGE_IDE) 953 scc_s = "IDE"; 954 else if (cc == PCI_CLASS_STORAGE_SATA) 955 scc_s = "SATA"; 956 else if (cc == PCI_CLASS_STORAGE_RAID) 957 scc_s = "RAID"; 958 else 959 scc_s = "unknown"; 960 961 ahci_print_info(host, scc_s); 962 } 963 964 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 965 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 966 * support PMP and the 4726 either directly exports the device 967 * attached to the first downstream port or acts as a hardware storage 968 * controller and emulate a single ATA device (can be RAID 0/1 or some 969 * other configuration). 970 * 971 * When there's no device attached to the first downstream port of the 972 * 4726, "Config Disk" appears, which is a pseudo ATA device to 973 * configure the 4726. However, ATA emulation of the device is very 974 * lame. It doesn't send signature D2H Reg FIS after the initial 975 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 976 * 977 * The following function works around the problem by always using 978 * hardreset on the port and not depending on receiving signature FIS 979 * afterward. If signature FIS isn't received soon, ATA class is 980 * assumed without follow-up softreset. 981 */ 982 static void ahci_p5wdh_workaround(struct ata_host *host) 983 { 984 static const struct dmi_system_id sysids[] = { 985 { 986 .ident = "P5W DH Deluxe", 987 .matches = { 988 DMI_MATCH(DMI_SYS_VENDOR, 989 "ASUSTEK COMPUTER INC"), 990 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 991 }, 992 }, 993 { } 994 }; 995 struct pci_dev *pdev = to_pci_dev(host->dev); 996 997 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 998 dmi_check_system(sysids)) { 999 struct ata_port *ap = host->ports[1]; 1000 1001 dev_info(&pdev->dev, 1002 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1003 1004 ap->ops = &ahci_p5wdh_ops; 1005 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1006 } 1007 } 1008 1009 /* 1010 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1011 * booting in BIOS compatibility mode. We restore the registers but not ID. 1012 */ 1013 static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1014 { 1015 u32 val; 1016 1017 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1018 1019 pci_read_config_dword(pdev, 0xf8, &val); 1020 val |= 1 << 0x1b; 1021 /* the following changes the device ID, but appears not to affect function */ 1022 /* val = (val & ~0xf0000000) | 0x80000000; */ 1023 pci_write_config_dword(pdev, 0xf8, val); 1024 1025 pci_read_config_dword(pdev, 0x54c, &val); 1026 val |= 1 << 0xc; 1027 pci_write_config_dword(pdev, 0x54c, val); 1028 1029 pci_read_config_dword(pdev, 0x4a4, &val); 1030 val &= 0xff; 1031 val |= 0x01060100; 1032 pci_write_config_dword(pdev, 0x4a4, val); 1033 1034 pci_read_config_dword(pdev, 0x54c, &val); 1035 val &= ~(1 << 0xc); 1036 pci_write_config_dword(pdev, 0x54c, val); 1037 1038 pci_read_config_dword(pdev, 0xf8, &val); 1039 val &= ~(1 << 0x1b); 1040 pci_write_config_dword(pdev, 0xf8, val); 1041 } 1042 1043 static bool is_mcp89_apple(struct pci_dev *pdev) 1044 { 1045 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1046 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1047 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1048 pdev->subsystem_device == 0xcb89; 1049 } 1050 1051 /* only some SB600 ahci controllers can do 64bit DMA */ 1052 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1053 { 1054 static const struct dmi_system_id sysids[] = { 1055 /* 1056 * The oldest version known to be broken is 0901 and 1057 * working is 1501 which was released on 2007-10-26. 1058 * Enable 64bit DMA on 1501 and anything newer. 1059 * 1060 * Please read bko#9412 for more info. 1061 */ 1062 { 1063 .ident = "ASUS M2A-VM", 1064 .matches = { 1065 DMI_MATCH(DMI_BOARD_VENDOR, 1066 "ASUSTeK Computer INC."), 1067 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1068 }, 1069 .driver_data = "20071026", /* yyyymmdd */ 1070 }, 1071 /* 1072 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1073 * support 64bit DMA. 1074 * 1075 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1076 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1077 * This spelling mistake was fixed in BIOS version 1.5, so 1078 * 1.5 and later have the Manufacturer as 1079 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1080 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1081 * 1082 * BIOS versions earlier than 1.9 had a Board Product Name 1083 * DMI field of "MS-7376". This was changed to be 1084 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1085 * match on DMI_BOARD_NAME of "MS-7376". 1086 */ 1087 { 1088 .ident = "MSI K9A2 Platinum", 1089 .matches = { 1090 DMI_MATCH(DMI_BOARD_VENDOR, 1091 "MICRO-STAR INTER"), 1092 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1093 }, 1094 }, 1095 /* 1096 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1097 * 64bit DMA. 1098 * 1099 * This board also had the typo mentioned above in the 1100 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1101 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1102 */ 1103 { 1104 .ident = "MSI K9AGM2", 1105 .matches = { 1106 DMI_MATCH(DMI_BOARD_VENDOR, 1107 "MICRO-STAR INTER"), 1108 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1109 }, 1110 }, 1111 /* 1112 * All BIOS versions for the Asus M3A support 64bit DMA. 1113 * (all release versions from 0301 to 1206 were tested) 1114 */ 1115 { 1116 .ident = "ASUS M3A", 1117 .matches = { 1118 DMI_MATCH(DMI_BOARD_VENDOR, 1119 "ASUSTeK Computer INC."), 1120 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1121 }, 1122 }, 1123 { } 1124 }; 1125 const struct dmi_system_id *match; 1126 int year, month, date; 1127 char buf[9]; 1128 1129 match = dmi_first_match(sysids); 1130 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1131 !match) 1132 return false; 1133 1134 if (!match->driver_data) 1135 goto enable_64bit; 1136 1137 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1138 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1139 1140 if (strcmp(buf, match->driver_data) >= 0) 1141 goto enable_64bit; 1142 else { 1143 dev_warn(&pdev->dev, 1144 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1145 match->ident); 1146 return false; 1147 } 1148 1149 enable_64bit: 1150 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1151 return true; 1152 } 1153 1154 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1155 { 1156 static const struct dmi_system_id broken_systems[] = { 1157 { 1158 .ident = "HP Compaq nx6310", 1159 .matches = { 1160 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1161 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1162 }, 1163 /* PCI slot number of the controller */ 1164 .driver_data = (void *)0x1FUL, 1165 }, 1166 { 1167 .ident = "HP Compaq 6720s", 1168 .matches = { 1169 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1170 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1171 }, 1172 /* PCI slot number of the controller */ 1173 .driver_data = (void *)0x1FUL, 1174 }, 1175 1176 { } /* terminate list */ 1177 }; 1178 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1179 1180 if (dmi) { 1181 unsigned long slot = (unsigned long)dmi->driver_data; 1182 /* apply the quirk only to on-board controllers */ 1183 return slot == PCI_SLOT(pdev->devfn); 1184 } 1185 1186 return false; 1187 } 1188 1189 static bool ahci_broken_suspend(struct pci_dev *pdev) 1190 { 1191 static const struct dmi_system_id sysids[] = { 1192 /* 1193 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1194 * to the harddisk doesn't become online after 1195 * resuming from STR. Warn and fail suspend. 1196 * 1197 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1198 * 1199 * Use dates instead of versions to match as HP is 1200 * apparently recycling both product and version 1201 * strings. 1202 * 1203 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1204 */ 1205 { 1206 .ident = "dv4", 1207 .matches = { 1208 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1209 DMI_MATCH(DMI_PRODUCT_NAME, 1210 "HP Pavilion dv4 Notebook PC"), 1211 }, 1212 .driver_data = "20090105", /* F.30 */ 1213 }, 1214 { 1215 .ident = "dv5", 1216 .matches = { 1217 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1218 DMI_MATCH(DMI_PRODUCT_NAME, 1219 "HP Pavilion dv5 Notebook PC"), 1220 }, 1221 .driver_data = "20090506", /* F.16 */ 1222 }, 1223 { 1224 .ident = "dv6", 1225 .matches = { 1226 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1227 DMI_MATCH(DMI_PRODUCT_NAME, 1228 "HP Pavilion dv6 Notebook PC"), 1229 }, 1230 .driver_data = "20090423", /* F.21 */ 1231 }, 1232 { 1233 .ident = "HDX18", 1234 .matches = { 1235 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1236 DMI_MATCH(DMI_PRODUCT_NAME, 1237 "HP HDX18 Notebook PC"), 1238 }, 1239 .driver_data = "20090430", /* F.23 */ 1240 }, 1241 /* 1242 * Acer eMachines G725 has the same problem. BIOS 1243 * V1.03 is known to be broken. V3.04 is known to 1244 * work. Between, there are V1.06, V2.06 and V3.03 1245 * that we don't have much idea about. For now, 1246 * blacklist anything older than V3.04. 1247 * 1248 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1249 */ 1250 { 1251 .ident = "G725", 1252 .matches = { 1253 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1254 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1255 }, 1256 .driver_data = "20091216", /* V3.04 */ 1257 }, 1258 { } /* terminate list */ 1259 }; 1260 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1261 int year, month, date; 1262 char buf[9]; 1263 1264 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1265 return false; 1266 1267 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1268 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1269 1270 return strcmp(buf, dmi->driver_data) < 0; 1271 } 1272 1273 static bool ahci_broken_lpm(struct pci_dev *pdev) 1274 { 1275 static const struct dmi_system_id sysids[] = { 1276 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1277 { 1278 .matches = { 1279 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1280 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1281 }, 1282 .driver_data = "20180406", /* 1.31 */ 1283 }, 1284 { 1285 .matches = { 1286 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1287 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1288 }, 1289 .driver_data = "20180420", /* 1.28 */ 1290 }, 1291 { 1292 .matches = { 1293 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1294 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1295 }, 1296 .driver_data = "20180315", /* 1.33 */ 1297 }, 1298 { 1299 .matches = { 1300 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1301 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1302 }, 1303 /* 1304 * Note date based on release notes, 2.35 has been 1305 * reported to be good, but I've been unable to get 1306 * a hold of the reporter to get the DMI BIOS date. 1307 * TODO: fix this. 1308 */ 1309 .driver_data = "20180310", /* 2.35 */ 1310 }, 1311 { } /* terminate list */ 1312 }; 1313 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1314 int year, month, date; 1315 char buf[9]; 1316 1317 if (!dmi) 1318 return false; 1319 1320 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1321 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1322 1323 return strcmp(buf, dmi->driver_data) < 0; 1324 } 1325 1326 static bool ahci_broken_online(struct pci_dev *pdev) 1327 { 1328 #define ENCODE_BUSDEVFN(bus, slot, func) \ 1329 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1330 static const struct dmi_system_id sysids[] = { 1331 /* 1332 * There are several gigabyte boards which use 1333 * SIMG5723s configured as hardware RAID. Certain 1334 * 5723 firmware revisions shipped there keep the link 1335 * online but fail to answer properly to SRST or 1336 * IDENTIFY when no device is attached downstream 1337 * causing libata to retry quite a few times leading 1338 * to excessive detection delay. 1339 * 1340 * As these firmwares respond to the second reset try 1341 * with invalid device signature, considering unknown 1342 * sig as offline works around the problem acceptably. 1343 */ 1344 { 1345 .ident = "EP45-DQ6", 1346 .matches = { 1347 DMI_MATCH(DMI_BOARD_VENDOR, 1348 "Gigabyte Technology Co., Ltd."), 1349 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1350 }, 1351 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1352 }, 1353 { 1354 .ident = "EP45-DS5", 1355 .matches = { 1356 DMI_MATCH(DMI_BOARD_VENDOR, 1357 "Gigabyte Technology Co., Ltd."), 1358 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1359 }, 1360 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1361 }, 1362 { } /* terminate list */ 1363 }; 1364 #undef ENCODE_BUSDEVFN 1365 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1366 unsigned int val; 1367 1368 if (!dmi) 1369 return false; 1370 1371 val = (unsigned long)dmi->driver_data; 1372 1373 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1374 } 1375 1376 static bool ahci_broken_devslp(struct pci_dev *pdev) 1377 { 1378 /* device with broken DEVSLP but still showing SDS capability */ 1379 static const struct pci_device_id ids[] = { 1380 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1381 {} 1382 }; 1383 1384 return pci_match_id(ids, pdev); 1385 } 1386 1387 #ifdef CONFIG_ATA_ACPI 1388 static void ahci_gtf_filter_workaround(struct ata_host *host) 1389 { 1390 static const struct dmi_system_id sysids[] = { 1391 /* 1392 * Aspire 3810T issues a bunch of SATA enable commands 1393 * via _GTF including an invalid one and one which is 1394 * rejected by the device. Among the successful ones 1395 * is FPDMA non-zero offset enable which when enabled 1396 * only on the drive side leads to NCQ command 1397 * failures. Filter it out. 1398 */ 1399 { 1400 .ident = "Aspire 3810T", 1401 .matches = { 1402 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1403 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1404 }, 1405 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1406 }, 1407 { } 1408 }; 1409 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1410 unsigned int filter; 1411 int i; 1412 1413 if (!dmi) 1414 return; 1415 1416 filter = (unsigned long)dmi->driver_data; 1417 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1418 filter, dmi->ident); 1419 1420 for (i = 0; i < host->n_ports; i++) { 1421 struct ata_port *ap = host->ports[i]; 1422 struct ata_link *link; 1423 struct ata_device *dev; 1424 1425 ata_for_each_link(link, ap, EDGE) 1426 ata_for_each_dev(dev, link, ALL) 1427 dev->gtf_filter |= filter; 1428 } 1429 } 1430 #else 1431 static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1432 {} 1433 #endif 1434 1435 /* 1436 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1437 * as DUMMY, or detected but eventually get a "link down" and never get up 1438 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1439 * port_map may hold a value of 0x00. 1440 * 1441 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1442 * and can significantly reduce the occurrence of the problem. 1443 * 1444 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1445 */ 1446 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1447 struct pci_dev *pdev) 1448 { 1449 static const struct dmi_system_id sysids[] = { 1450 { 1451 .ident = "Acer Switch Alpha 12", 1452 .matches = { 1453 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1454 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1455 }, 1456 }, 1457 { } 1458 }; 1459 1460 if (dmi_check_system(sysids)) { 1461 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1462 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1463 hpriv->port_map = 0x7; 1464 hpriv->cap = 0xC734FF02; 1465 } 1466 } 1467 } 1468 1469 #ifdef CONFIG_ARM64 1470 /* 1471 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1472 * Workaround is to make sure all pending IRQs are served before leaving 1473 * handler. 1474 */ 1475 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1476 { 1477 struct ata_host *host = dev_instance; 1478 struct ahci_host_priv *hpriv; 1479 unsigned int rc = 0; 1480 void __iomem *mmio; 1481 u32 irq_stat, irq_masked; 1482 unsigned int handled = 1; 1483 1484 hpriv = host->private_data; 1485 mmio = hpriv->mmio; 1486 irq_stat = readl(mmio + HOST_IRQ_STAT); 1487 if (!irq_stat) 1488 return IRQ_NONE; 1489 1490 do { 1491 irq_masked = irq_stat & hpriv->port_map; 1492 spin_lock(&host->lock); 1493 rc = ahci_handle_port_intr(host, irq_masked); 1494 if (!rc) 1495 handled = 0; 1496 writel(irq_stat, mmio + HOST_IRQ_STAT); 1497 irq_stat = readl(mmio + HOST_IRQ_STAT); 1498 spin_unlock(&host->lock); 1499 } while (irq_stat); 1500 1501 return IRQ_RETVAL(handled); 1502 } 1503 #endif 1504 1505 static void ahci_remap_check(struct pci_dev *pdev, int bar, 1506 struct ahci_host_priv *hpriv) 1507 { 1508 int i; 1509 u32 cap; 1510 1511 /* 1512 * Check if this device might have remapped nvme devices. 1513 */ 1514 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1515 pci_resource_len(pdev, bar) < SZ_512K || 1516 bar != AHCI_PCI_BAR_STANDARD || 1517 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1518 return; 1519 1520 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1521 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1522 if ((cap & (1 << i)) == 0) 1523 continue; 1524 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1525 != PCI_CLASS_STORAGE_EXPRESS) 1526 continue; 1527 1528 /* We've found a remapped device */ 1529 hpriv->remapped_nvme++; 1530 } 1531 1532 if (!hpriv->remapped_nvme) 1533 return; 1534 1535 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1536 hpriv->remapped_nvme); 1537 dev_warn(&pdev->dev, 1538 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1539 1540 /* 1541 * Don't rely on the msi-x capability in the remap case, 1542 * share the legacy interrupt across ahci and remapped devices. 1543 */ 1544 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1545 } 1546 1547 static int ahci_get_irq_vector(struct ata_host *host, int port) 1548 { 1549 return pci_irq_vector(to_pci_dev(host->dev), port); 1550 } 1551 1552 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1553 struct ahci_host_priv *hpriv) 1554 { 1555 int nvec; 1556 1557 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1558 return -ENODEV; 1559 1560 /* 1561 * If number of MSIs is less than number of ports then Sharing Last 1562 * Message mode could be enforced. In this case assume that advantage 1563 * of multipe MSIs is negated and use single MSI mode instead. 1564 */ 1565 if (n_ports > 1) { 1566 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1567 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1568 if (nvec > 0) { 1569 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1570 hpriv->get_irq_vector = ahci_get_irq_vector; 1571 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1572 return nvec; 1573 } 1574 1575 /* 1576 * Fallback to single MSI mode if the controller 1577 * enforced MRSM mode. 1578 */ 1579 printk(KERN_INFO 1580 "ahci: MRSM is on, fallback to single MSI\n"); 1581 pci_free_irq_vectors(pdev); 1582 } 1583 } 1584 1585 /* 1586 * If the host is not capable of supporting per-port vectors, fall 1587 * back to single MSI before finally attempting single MSI-X. 1588 */ 1589 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1590 if (nvec == 1) 1591 return nvec; 1592 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1593 } 1594 1595 static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1596 struct ahci_host_priv *hpriv) 1597 { 1598 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1599 1600 1601 /* Ignore processing for chipsets that don't use policy */ 1602 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY)) 1603 return; 1604 1605 /* user modified policy via module param */ 1606 if (mobile_lpm_policy != -1) { 1607 policy = mobile_lpm_policy; 1608 goto update_policy; 1609 } 1610 1611 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) { 1612 if (hpriv->cap & HOST_CAP_PART) 1613 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1614 else if (hpriv->cap & HOST_CAP_SSC) 1615 policy = ATA_LPM_MIN_POWER; 1616 } 1617 1618 update_policy: 1619 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1620 ap->target_lpm_policy = policy; 1621 } 1622 1623 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1624 { 1625 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1626 u16 tmp16; 1627 1628 /* 1629 * Only apply the 6-port PCS quirk for known legacy platforms. 1630 */ 1631 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1632 return; 1633 1634 /* Skip applying the quirk on Denverton and beyond */ 1635 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1636 return; 1637 1638 /* 1639 * port_map is determined from PORTS_IMPL PCI register which is 1640 * implemented as write or write-once register. If the register 1641 * isn't programmed, ahci automatically generates it from number 1642 * of ports, which is good enough for PCS programming. It is 1643 * otherwise expected that platform firmware enables the ports 1644 * before the OS boots. 1645 */ 1646 pci_read_config_word(pdev, PCS_6, &tmp16); 1647 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1648 tmp16 |= hpriv->port_map; 1649 pci_write_config_word(pdev, PCS_6, tmp16); 1650 } 1651 } 1652 1653 static ssize_t remapped_nvme_show(struct device *dev, 1654 struct device_attribute *attr, 1655 char *buf) 1656 { 1657 struct ata_host *host = dev_get_drvdata(dev); 1658 struct ahci_host_priv *hpriv = host->private_data; 1659 1660 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme); 1661 } 1662 1663 static DEVICE_ATTR_RO(remapped_nvme); 1664 1665 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1666 { 1667 unsigned int board_id = ent->driver_data; 1668 struct ata_port_info pi = ahci_port_info[board_id]; 1669 const struct ata_port_info *ppi[] = { &pi, NULL }; 1670 struct device *dev = &pdev->dev; 1671 struct ahci_host_priv *hpriv; 1672 struct ata_host *host; 1673 int n_ports, i, rc; 1674 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1675 1676 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1677 1678 ata_print_version_once(&pdev->dev, DRV_VERSION); 1679 1680 /* The AHCI driver can only drive the SATA ports, the PATA driver 1681 can drive them all so if both drivers are selected make sure 1682 AHCI stays out of the way */ 1683 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1684 return -ENODEV; 1685 1686 /* Apple BIOS on MCP89 prevents us using AHCI */ 1687 if (is_mcp89_apple(pdev)) 1688 ahci_mcp89_apple_enable(pdev); 1689 1690 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1691 * At the moment, we can only use the AHCI mode. Let the users know 1692 * that for SAS drives they're out of luck. 1693 */ 1694 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1695 dev_info(&pdev->dev, 1696 "PDC42819 can only drive SATA devices with this driver\n"); 1697 1698 /* Some devices use non-standard BARs */ 1699 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1700 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1701 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1702 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1703 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1704 if (pdev->device == 0xa01c) 1705 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1706 if (pdev->device == 0xa084) 1707 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1708 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1709 if (pdev->device == 0x7a08) 1710 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1711 } 1712 1713 /* acquire resources */ 1714 rc = pcim_enable_device(pdev); 1715 if (rc) 1716 return rc; 1717 1718 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1719 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1720 u8 map; 1721 1722 /* ICH6s share the same PCI ID for both piix and ahci 1723 * modes. Enabling ahci mode while MAP indicates 1724 * combined mode is a bad idea. Yield to ata_piix. 1725 */ 1726 pci_read_config_byte(pdev, ICH_MAP, &map); 1727 if (map & 0x3) { 1728 dev_info(&pdev->dev, 1729 "controller is in combined mode, can't enable AHCI mode\n"); 1730 return -ENODEV; 1731 } 1732 } 1733 1734 /* AHCI controllers often implement SFF compatible interface. 1735 * Grab all PCI BARs just in case. 1736 */ 1737 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1738 if (rc == -EBUSY) 1739 pcim_pin_device(pdev); 1740 if (rc) 1741 return rc; 1742 1743 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1744 if (!hpriv) 1745 return -ENOMEM; 1746 hpriv->flags |= (unsigned long)pi.private_data; 1747 1748 /* MCP65 revision A1 and A2 can't do MSI */ 1749 if (board_id == board_ahci_mcp65 && 1750 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1751 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1752 1753 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1754 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1755 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1756 1757 /* only some SB600s can do 64bit DMA */ 1758 if (ahci_sb600_enable_64bit(pdev)) 1759 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1760 1761 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1762 1763 /* detect remapped nvme devices */ 1764 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1765 1766 sysfs_add_file_to_group(&pdev->dev.kobj, 1767 &dev_attr_remapped_nvme.attr, 1768 NULL); 1769 1770 /* must set flag prior to save config in order to take effect */ 1771 if (ahci_broken_devslp(pdev)) 1772 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1773 1774 #ifdef CONFIG_ARM64 1775 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 1776 pdev->device == 0xa235 && 1777 pdev->revision < 0x30) 1778 hpriv->flags |= AHCI_HFLAG_NO_SXS; 1779 1780 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1781 hpriv->irq_handler = ahci_thunderx_irq_handler; 1782 #endif 1783 1784 /* save initial config */ 1785 ahci_pci_save_initial_config(pdev, hpriv); 1786 1787 /* 1788 * If platform firmware failed to enable ports, try to enable 1789 * them here. 1790 */ 1791 ahci_intel_pcs_quirk(pdev, hpriv); 1792 1793 /* prepare host */ 1794 if (hpriv->cap & HOST_CAP_NCQ) { 1795 pi.flags |= ATA_FLAG_NCQ; 1796 /* 1797 * Auto-activate optimization is supposed to be 1798 * supported on all AHCI controllers indicating NCQ 1799 * capability, but it seems to be broken on some 1800 * chipsets including NVIDIAs. 1801 */ 1802 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1803 pi.flags |= ATA_FLAG_FPDMA_AA; 1804 1805 /* 1806 * All AHCI controllers should be forward-compatible 1807 * with the new auxiliary field. This code should be 1808 * conditionalized if any buggy AHCI controllers are 1809 * encountered. 1810 */ 1811 pi.flags |= ATA_FLAG_FPDMA_AUX; 1812 } 1813 1814 if (hpriv->cap & HOST_CAP_PMP) 1815 pi.flags |= ATA_FLAG_PMP; 1816 1817 ahci_set_em_messages(hpriv, &pi); 1818 1819 if (ahci_broken_system_poweroff(pdev)) { 1820 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1821 dev_info(&pdev->dev, 1822 "quirky BIOS, skipping spindown on poweroff\n"); 1823 } 1824 1825 if (ahci_broken_lpm(pdev)) { 1826 pi.flags |= ATA_FLAG_NO_LPM; 1827 dev_warn(&pdev->dev, 1828 "BIOS update required for Link Power Management support\n"); 1829 } 1830 1831 if (ahci_broken_suspend(pdev)) { 1832 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1833 dev_warn(&pdev->dev, 1834 "BIOS update required for suspend/resume\n"); 1835 } 1836 1837 if (ahci_broken_online(pdev)) { 1838 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1839 dev_info(&pdev->dev, 1840 "online status unreliable, applying workaround\n"); 1841 } 1842 1843 1844 /* Acer SA5-271 workaround modifies private_data */ 1845 acer_sa5_271_workaround(hpriv, pdev); 1846 1847 /* CAP.NP sometimes indicate the index of the last enabled 1848 * port, at other times, that of the last possible port, so 1849 * determining the maximum port number requires looking at 1850 * both CAP.NP and port_map. 1851 */ 1852 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1853 1854 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1855 if (!host) 1856 return -ENOMEM; 1857 host->private_data = hpriv; 1858 1859 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1860 /* legacy intx interrupts */ 1861 pci_intx(pdev, 1); 1862 } 1863 hpriv->irq = pci_irq_vector(pdev, 0); 1864 1865 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1866 host->flags |= ATA_HOST_PARALLEL_SCAN; 1867 else 1868 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1869 1870 if (pi.flags & ATA_FLAG_EM) 1871 ahci_reset_em(host); 1872 1873 for (i = 0; i < host->n_ports; i++) { 1874 struct ata_port *ap = host->ports[i]; 1875 1876 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1877 ata_port_pbar_desc(ap, ahci_pci_bar, 1878 0x100 + ap->port_no * 0x80, "port"); 1879 1880 /* set enclosure management message type */ 1881 if (ap->flags & ATA_FLAG_EM) 1882 ap->em_message_type = hpriv->em_msg_type; 1883 1884 ahci_update_initial_lpm_policy(ap, hpriv); 1885 1886 /* disabled/not-implemented port */ 1887 if (!(hpriv->port_map & (1 << i))) 1888 ap->ops = &ata_dummy_port_ops; 1889 } 1890 1891 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1892 ahci_p5wdh_workaround(host); 1893 1894 /* apply gtf filter quirk */ 1895 ahci_gtf_filter_workaround(host); 1896 1897 /* initialize adapter */ 1898 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1899 if (rc) 1900 return rc; 1901 1902 rc = ahci_reset_controller(host); 1903 if (rc) 1904 return rc; 1905 1906 ahci_pci_init_controller(host); 1907 ahci_pci_print_info(host); 1908 1909 pci_set_master(pdev); 1910 1911 rc = ahci_host_activate(host, &ahci_sht); 1912 if (rc) 1913 return rc; 1914 1915 pm_runtime_put_noidle(&pdev->dev); 1916 return 0; 1917 } 1918 1919 static void ahci_shutdown_one(struct pci_dev *pdev) 1920 { 1921 ata_pci_shutdown_one(pdev); 1922 } 1923 1924 static void ahci_remove_one(struct pci_dev *pdev) 1925 { 1926 sysfs_remove_file_from_group(&pdev->dev.kobj, 1927 &dev_attr_remapped_nvme.attr, 1928 NULL); 1929 pm_runtime_get_noresume(&pdev->dev); 1930 ata_pci_remove_one(pdev); 1931 } 1932 1933 module_pci_driver(ahci_pci_driver); 1934 1935 MODULE_AUTHOR("Jeff Garzik"); 1936 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1937 MODULE_LICENSE("GPL"); 1938 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1939 MODULE_VERSION(DRV_VERSION); 1940