1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149 } 150 151 static void 152 mt7530_mutex_unlock(struct mt7530_priv *priv) 153 { 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156 } 157 158 static void 159 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160 { 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166 } 167 168 static void 169 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170 { 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181 } 182 183 static void 184 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 core_rmw(priv, reg, 0, val); 187 } 188 189 static void 190 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191 { 192 core_rmw(priv, reg, val, 0); 193 } 194 195 static int 196 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197 { 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207 } 208 209 static u32 210 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211 { 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224 } 225 226 static void 227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static u32 237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238 { 239 return mt7530_mii_read(p->priv, p->reg); 240 } 241 242 static u32 243 _mt7530_read(struct mt7530_dummy_poll *p) 244 { 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254 } 255 256 static u32 257 mt7530_read(struct mt7530_priv *priv, u32 reg) 258 { 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263 } 264 265 static void 266 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268 { 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274 } 275 276 static void 277 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 mt7530_rmw(priv, reg, val, val); 280 } 281 282 static void 283 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284 { 285 mt7530_rmw(priv, reg, val, 0); 286 } 287 288 static int 289 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290 { 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318 } 319 320 static void 321 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322 { 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344 } 345 346 static void 347 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350 { 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374 } 375 376 /* Set up switch core clock for MT7530 */ 377 static void mt7530_pll_setup(struct mt7530_priv *priv) 378 { 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400 } 401 402 /* If port 6 is available as a CPU port, always prefer that as the default, 403 * otherwise don't care. 404 */ 405 static struct dsa_port * 406 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 407 { 408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 409 410 if (dsa_port_is_cpu(cpu_dp)) 411 return cpu_dp; 412 413 return NULL; 414 } 415 416 /* Setup port 6 interface mode and TRGMII TX circuit */ 417 static void 418 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 419 { 420 struct mt7530_priv *priv = ds->priv; 421 u32 ncpo1, ssc_delta, xtal; 422 423 /* Disable the MT7530 TRGMII clocks */ 424 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 425 426 if (interface == PHY_INTERFACE_MODE_RGMII) { 427 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 428 P6_INTF_MODE(0)); 429 return; 430 } 431 432 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 433 434 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 435 436 if (xtal == HWTRAP_XTAL_25MHZ) 437 ssc_delta = 0x57; 438 else 439 ssc_delta = 0x87; 440 441 if (priv->id == ID_MT7621) { 442 /* PLL frequency: 125MHz: 1.0GBit */ 443 if (xtal == HWTRAP_XTAL_40MHZ) 444 ncpo1 = 0x0640; 445 if (xtal == HWTRAP_XTAL_25MHZ) 446 ncpo1 = 0x0a00; 447 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 448 if (xtal == HWTRAP_XTAL_40MHZ) 449 ncpo1 = 0x0c80; 450 if (xtal == HWTRAP_XTAL_25MHZ) 451 ncpo1 = 0x1400; 452 } 453 454 /* Setup the MT7530 TRGMII Tx Clock */ 455 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 456 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 457 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 458 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 459 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 460 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 461 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 462 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 463 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 464 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 465 466 /* Enable the MT7530 TRGMII clocks */ 467 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 468 } 469 470 static void 471 mt7531_pll_setup(struct mt7530_priv *priv) 472 { 473 u32 top_sig; 474 u32 hwstrap; 475 u32 xtal; 476 u32 val; 477 478 val = mt7530_read(priv, MT7531_CREV); 479 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 480 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 481 if ((val & CHIP_REV_M) > 0) 482 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 483 HWTRAP_XTAL_FSEL_25MHZ; 484 else 485 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 486 487 /* Step 1 : Disable MT7531 COREPLL */ 488 val = mt7530_read(priv, MT7531_PLLGP_EN); 489 val &= ~EN_COREPLL; 490 mt7530_write(priv, MT7531_PLLGP_EN, val); 491 492 /* Step 2: switch to XTAL output */ 493 val = mt7530_read(priv, MT7531_PLLGP_EN); 494 val |= SW_CLKSW; 495 mt7530_write(priv, MT7531_PLLGP_EN, val); 496 497 val = mt7530_read(priv, MT7531_PLLGP_CR0); 498 val &= ~RG_COREPLL_EN; 499 mt7530_write(priv, MT7531_PLLGP_CR0, val); 500 501 /* Step 3: disable PLLGP and enable program PLLGP */ 502 val = mt7530_read(priv, MT7531_PLLGP_EN); 503 val |= SW_PLLGP; 504 mt7530_write(priv, MT7531_PLLGP_EN, val); 505 506 /* Step 4: program COREPLL output frequency to 500MHz */ 507 val = mt7530_read(priv, MT7531_PLLGP_CR0); 508 val &= ~RG_COREPLL_POSDIV_M; 509 val |= 2 << RG_COREPLL_POSDIV_S; 510 mt7530_write(priv, MT7531_PLLGP_CR0, val); 511 usleep_range(25, 35); 512 513 switch (xtal) { 514 case HWTRAP_XTAL_FSEL_25MHZ: 515 val = mt7530_read(priv, MT7531_PLLGP_CR0); 516 val &= ~RG_COREPLL_SDM_PCW_M; 517 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 518 mt7530_write(priv, MT7531_PLLGP_CR0, val); 519 break; 520 case HWTRAP_XTAL_FSEL_40MHZ: 521 val = mt7530_read(priv, MT7531_PLLGP_CR0); 522 val &= ~RG_COREPLL_SDM_PCW_M; 523 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 524 mt7530_write(priv, MT7531_PLLGP_CR0, val); 525 break; 526 } 527 528 /* Set feedback divide ratio update signal to high */ 529 val = mt7530_read(priv, MT7531_PLLGP_CR0); 530 val |= RG_COREPLL_SDM_PCW_CHG; 531 mt7530_write(priv, MT7531_PLLGP_CR0, val); 532 /* Wait for at least 16 XTAL clocks */ 533 usleep_range(10, 20); 534 535 /* Step 5: set feedback divide ratio update signal to low */ 536 val = mt7530_read(priv, MT7531_PLLGP_CR0); 537 val &= ~RG_COREPLL_SDM_PCW_CHG; 538 mt7530_write(priv, MT7531_PLLGP_CR0, val); 539 540 /* Enable 325M clock for SGMII */ 541 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 542 543 /* Enable 250SSC clock for RGMII */ 544 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 545 546 /* Step 6: Enable MT7531 PLL */ 547 val = mt7530_read(priv, MT7531_PLLGP_CR0); 548 val |= RG_COREPLL_EN; 549 mt7530_write(priv, MT7531_PLLGP_CR0, val); 550 551 val = mt7530_read(priv, MT7531_PLLGP_EN); 552 val |= EN_COREPLL; 553 mt7530_write(priv, MT7531_PLLGP_EN, val); 554 usleep_range(25, 35); 555 } 556 557 static void 558 mt7530_mib_reset(struct dsa_switch *ds) 559 { 560 struct mt7530_priv *priv = ds->priv; 561 562 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 563 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 564 } 565 566 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 567 { 568 return mdiobus_read_nested(priv->bus, port, regnum); 569 } 570 571 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 572 u16 val) 573 { 574 return mdiobus_write_nested(priv->bus, port, regnum, val); 575 } 576 577 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 578 int devad, int regnum) 579 { 580 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 581 } 582 583 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 584 int regnum, u16 val) 585 { 586 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 587 } 588 589 static int 590 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 591 int regnum) 592 { 593 struct mt7530_dummy_poll p; 594 u32 reg, val; 595 int ret; 596 597 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 598 599 mt7530_mutex_lock(priv); 600 601 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 602 !(val & MT7531_PHY_ACS_ST), 20, 100000); 603 if (ret < 0) { 604 dev_err(priv->dev, "poll timeout\n"); 605 goto out; 606 } 607 608 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 609 MT7531_MDIO_DEV_ADDR(devad) | regnum; 610 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 611 612 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 613 !(val & MT7531_PHY_ACS_ST), 20, 100000); 614 if (ret < 0) { 615 dev_err(priv->dev, "poll timeout\n"); 616 goto out; 617 } 618 619 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 620 MT7531_MDIO_DEV_ADDR(devad); 621 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 622 623 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 624 !(val & MT7531_PHY_ACS_ST), 20, 100000); 625 if (ret < 0) { 626 dev_err(priv->dev, "poll timeout\n"); 627 goto out; 628 } 629 630 ret = val & MT7531_MDIO_RW_DATA_MASK; 631 out: 632 mt7530_mutex_unlock(priv); 633 634 return ret; 635 } 636 637 static int 638 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 639 int regnum, u16 data) 640 { 641 struct mt7530_dummy_poll p; 642 u32 val, reg; 643 int ret; 644 645 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 646 647 mt7530_mutex_lock(priv); 648 649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 650 !(val & MT7531_PHY_ACS_ST), 20, 100000); 651 if (ret < 0) { 652 dev_err(priv->dev, "poll timeout\n"); 653 goto out; 654 } 655 656 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 657 MT7531_MDIO_DEV_ADDR(devad) | regnum; 658 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 659 660 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 661 !(val & MT7531_PHY_ACS_ST), 20, 100000); 662 if (ret < 0) { 663 dev_err(priv->dev, "poll timeout\n"); 664 goto out; 665 } 666 667 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 668 MT7531_MDIO_DEV_ADDR(devad) | data; 669 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 670 671 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 672 !(val & MT7531_PHY_ACS_ST), 20, 100000); 673 if (ret < 0) { 674 dev_err(priv->dev, "poll timeout\n"); 675 goto out; 676 } 677 678 out: 679 mt7530_mutex_unlock(priv); 680 681 return ret; 682 } 683 684 static int 685 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 686 { 687 struct mt7530_dummy_poll p; 688 int ret; 689 u32 val; 690 691 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 692 693 mt7530_mutex_lock(priv); 694 695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 696 !(val & MT7531_PHY_ACS_ST), 20, 100000); 697 if (ret < 0) { 698 dev_err(priv->dev, "poll timeout\n"); 699 goto out; 700 } 701 702 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 703 MT7531_MDIO_REG_ADDR(regnum); 704 705 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 706 707 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 708 !(val & MT7531_PHY_ACS_ST), 20, 100000); 709 if (ret < 0) { 710 dev_err(priv->dev, "poll timeout\n"); 711 goto out; 712 } 713 714 ret = val & MT7531_MDIO_RW_DATA_MASK; 715 out: 716 mt7530_mutex_unlock(priv); 717 718 return ret; 719 } 720 721 static int 722 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 723 u16 data) 724 { 725 struct mt7530_dummy_poll p; 726 int ret; 727 u32 reg; 728 729 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 730 731 mt7530_mutex_lock(priv); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 734 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 741 MT7531_MDIO_REG_ADDR(regnum) | data; 742 743 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 744 745 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 746 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 747 if (ret < 0) { 748 dev_err(priv->dev, "poll timeout\n"); 749 goto out; 750 } 751 752 out: 753 mt7530_mutex_unlock(priv); 754 755 return ret; 756 } 757 758 static int 759 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 760 { 761 struct mt7530_priv *priv = bus->priv; 762 763 return priv->info->phy_read_c22(priv, port, regnum); 764 } 765 766 static int 767 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 768 { 769 struct mt7530_priv *priv = bus->priv; 770 771 return priv->info->phy_read_c45(priv, port, devad, regnum); 772 } 773 774 static int 775 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 776 { 777 struct mt7530_priv *priv = bus->priv; 778 779 return priv->info->phy_write_c22(priv, port, regnum, val); 780 } 781 782 static int 783 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 784 u16 val) 785 { 786 struct mt7530_priv *priv = bus->priv; 787 788 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 789 } 790 791 static void 792 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 793 uint8_t *data) 794 { 795 int i; 796 797 if (stringset != ETH_SS_STATS) 798 return; 799 800 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 801 ethtool_puts(&data, mt7530_mib[i].name); 802 } 803 804 static void 805 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 806 uint64_t *data) 807 { 808 struct mt7530_priv *priv = ds->priv; 809 const struct mt7530_mib_desc *mib; 810 u32 reg, i; 811 u64 hi; 812 813 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 814 mib = &mt7530_mib[i]; 815 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 816 817 data[i] = mt7530_read(priv, reg); 818 if (mib->size == 2) { 819 hi = mt7530_read(priv, reg + 4); 820 data[i] |= hi << 32; 821 } 822 } 823 } 824 825 static int 826 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 827 { 828 if (sset != ETH_SS_STATS) 829 return 0; 830 831 return ARRAY_SIZE(mt7530_mib); 832 } 833 834 static int 835 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 836 { 837 struct mt7530_priv *priv = ds->priv; 838 unsigned int secs = msecs / 1000; 839 unsigned int tmp_age_count; 840 unsigned int error = -1; 841 unsigned int age_count; 842 unsigned int age_unit; 843 844 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 845 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 846 return -ERANGE; 847 848 /* iterate through all possible age_count to find the closest pair */ 849 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 850 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 851 852 if (tmp_age_unit <= AGE_UNIT_MAX) { 853 unsigned int tmp_error = secs - 854 (tmp_age_count + 1) * (tmp_age_unit + 1); 855 856 /* found a closer pair */ 857 if (error > tmp_error) { 858 error = tmp_error; 859 age_count = tmp_age_count; 860 age_unit = tmp_age_unit; 861 } 862 863 /* found the exact match, so break the loop */ 864 if (!error) 865 break; 866 } 867 } 868 869 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 870 871 return 0; 872 } 873 874 static const char *p5_intf_modes(unsigned int p5_interface) 875 { 876 switch (p5_interface) { 877 case P5_DISABLED: 878 return "DISABLED"; 879 case P5_INTF_SEL_PHY_P0: 880 return "PHY P0"; 881 case P5_INTF_SEL_PHY_P4: 882 return "PHY P4"; 883 case P5_INTF_SEL_GMAC5: 884 return "GMAC5"; 885 default: 886 return "unknown"; 887 } 888 } 889 890 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 891 { 892 struct mt7530_priv *priv = ds->priv; 893 u8 tx_delay = 0; 894 int val; 895 896 mutex_lock(&priv->reg_mutex); 897 898 val = mt7530_read(priv, MT7530_MHWTRAP); 899 900 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 901 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 902 903 switch (priv->p5_intf_sel) { 904 case P5_INTF_SEL_PHY_P0: 905 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 906 val |= MHWTRAP_PHY0_SEL; 907 fallthrough; 908 case P5_INTF_SEL_PHY_P4: 909 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 910 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 911 912 /* Setup the MAC by default for the cpu port */ 913 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 914 break; 915 case P5_INTF_SEL_GMAC5: 916 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 917 val &= ~MHWTRAP_P5_DIS; 918 break; 919 default: 920 break; 921 } 922 923 /* Setup RGMII settings */ 924 if (phy_interface_mode_is_rgmii(interface)) { 925 val |= MHWTRAP_P5_RGMII_MODE; 926 927 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 928 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 929 930 /* Don't set delay in DSA mode */ 931 if (!dsa_is_dsa_port(priv->ds, 5) && 932 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 933 interface == PHY_INTERFACE_MODE_RGMII_ID)) 934 tx_delay = 4; /* n * 0.5 ns */ 935 936 /* P5 RGMII TX Clock Control: delay x */ 937 mt7530_write(priv, MT7530_P5RGMIITXCR, 938 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 939 940 /* reduce P5 RGMII Tx driving, 8mA */ 941 mt7530_write(priv, MT7530_IO_DRV_CR, 942 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 943 } 944 945 mt7530_write(priv, MT7530_MHWTRAP, val); 946 947 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 948 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 949 950 mutex_unlock(&priv->reg_mutex); 951 } 952 953 /* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std 954 * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA 955 * must only be propagated to C-VLAN and MAC Bridge components. That means 956 * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports, 957 * these frames are supposed to be processed by the CPU (software). So we make 958 * the switch only forward them to the CPU port. And if received from a CPU 959 * port, forward to a single port. The software is responsible of making the 960 * switch conform to the latter by setting a single port as destination port on 961 * the special tag. 962 * 963 * This switch intellectual property cannot conform to this part of the standard 964 * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC 965 * DAs, it also includes :22-FF which the scope of propagation is not supposed 966 * to be restricted for these MAC DAs. 967 */ 968 static void 969 mt753x_trap_frames(struct mt7530_priv *priv) 970 { 971 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 972 * VLAN-untagged. 973 */ 974 mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK | 975 MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | 976 MT753X_BPDU_PORT_FW_MASK, 977 MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 978 MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | 979 MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 980 MT753X_BPDU_CPU_ONLY); 981 982 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 983 * them VLAN-untagged. 984 */ 985 mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK | 986 MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK | 987 MT753X_R01_PORT_FW_MASK, 988 MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 989 MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | 990 MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 991 MT753X_BPDU_CPU_ONLY); 992 993 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 994 * them VLAN-untagged. 995 */ 996 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK | 997 MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK | 998 MT753X_R03_PORT_FW_MASK, 999 MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1000 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | 1001 MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1002 MT753X_BPDU_CPU_ONLY); 1003 } 1004 1005 static void 1006 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1007 { 1008 struct mt7530_priv *priv = ds->priv; 1009 1010 /* Enable Mediatek header mode on the cpu port */ 1011 mt7530_write(priv, MT7530_PVC_P(port), 1012 PORT_SPEC_TAG); 1013 1014 /* Enable flooding on the CPU port */ 1015 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1016 UNU_FFP(BIT(port))); 1017 1018 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1019 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1020 * is affine to the inbound user port. 1021 */ 1022 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1023 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1024 1025 /* CPU port gets connected to all user ports of 1026 * the switch. 1027 */ 1028 mt7530_write(priv, MT7530_PCR_P(port), 1029 PCR_MATRIX(dsa_user_ports(priv->ds))); 1030 1031 /* Set to fallback mode for independent VLAN learning */ 1032 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1033 MT7530_PORT_FALLBACK_MODE); 1034 } 1035 1036 static int 1037 mt7530_port_enable(struct dsa_switch *ds, int port, 1038 struct phy_device *phy) 1039 { 1040 struct dsa_port *dp = dsa_to_port(ds, port); 1041 struct mt7530_priv *priv = ds->priv; 1042 1043 mutex_lock(&priv->reg_mutex); 1044 1045 /* Allow the user port gets connected to the cpu port and also 1046 * restore the port matrix if the port is the member of a certain 1047 * bridge. 1048 */ 1049 if (dsa_port_is_user(dp)) { 1050 struct dsa_port *cpu_dp = dp->cpu_dp; 1051 1052 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1053 } 1054 priv->ports[port].enable = true; 1055 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1056 priv->ports[port].pm); 1057 1058 mutex_unlock(&priv->reg_mutex); 1059 1060 return 0; 1061 } 1062 1063 static void 1064 mt7530_port_disable(struct dsa_switch *ds, int port) 1065 { 1066 struct mt7530_priv *priv = ds->priv; 1067 1068 mutex_lock(&priv->reg_mutex); 1069 1070 /* Clear up all port matrix which could be restored in the next 1071 * enablement for the port. 1072 */ 1073 priv->ports[port].enable = false; 1074 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1075 PCR_MATRIX_CLR); 1076 1077 mutex_unlock(&priv->reg_mutex); 1078 } 1079 1080 static int 1081 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1082 { 1083 struct mt7530_priv *priv = ds->priv; 1084 int length; 1085 u32 val; 1086 1087 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1088 * largest MTU of the user ports. Because the switch only has a global 1089 * RX length register, only allowing CPU port here is enough. 1090 */ 1091 if (!dsa_is_cpu_port(ds, port)) 1092 return 0; 1093 1094 mt7530_mutex_lock(priv); 1095 1096 val = mt7530_mii_read(priv, MT7530_GMACCR); 1097 val &= ~MAX_RX_PKT_LEN_MASK; 1098 1099 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1100 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1101 if (length <= 1522) { 1102 val |= MAX_RX_PKT_LEN_1522; 1103 } else if (length <= 1536) { 1104 val |= MAX_RX_PKT_LEN_1536; 1105 } else if (length <= 1552) { 1106 val |= MAX_RX_PKT_LEN_1552; 1107 } else { 1108 val &= ~MAX_RX_JUMBO_MASK; 1109 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1110 val |= MAX_RX_PKT_LEN_JUMBO; 1111 } 1112 1113 mt7530_mii_write(priv, MT7530_GMACCR, val); 1114 1115 mt7530_mutex_unlock(priv); 1116 1117 return 0; 1118 } 1119 1120 static int 1121 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1122 { 1123 return MT7530_MAX_MTU; 1124 } 1125 1126 static void 1127 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1128 { 1129 struct mt7530_priv *priv = ds->priv; 1130 u32 stp_state; 1131 1132 switch (state) { 1133 case BR_STATE_DISABLED: 1134 stp_state = MT7530_STP_DISABLED; 1135 break; 1136 case BR_STATE_BLOCKING: 1137 stp_state = MT7530_STP_BLOCKING; 1138 break; 1139 case BR_STATE_LISTENING: 1140 stp_state = MT7530_STP_LISTENING; 1141 break; 1142 case BR_STATE_LEARNING: 1143 stp_state = MT7530_STP_LEARNING; 1144 break; 1145 case BR_STATE_FORWARDING: 1146 default: 1147 stp_state = MT7530_STP_FORWARDING; 1148 break; 1149 } 1150 1151 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1152 FID_PST(FID_BRIDGED, stp_state)); 1153 } 1154 1155 static int 1156 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1157 struct switchdev_brport_flags flags, 1158 struct netlink_ext_ack *extack) 1159 { 1160 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1161 BR_BCAST_FLOOD)) 1162 return -EINVAL; 1163 1164 return 0; 1165 } 1166 1167 static int 1168 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1169 struct switchdev_brport_flags flags, 1170 struct netlink_ext_ack *extack) 1171 { 1172 struct mt7530_priv *priv = ds->priv; 1173 1174 if (flags.mask & BR_LEARNING) 1175 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1176 flags.val & BR_LEARNING ? 0 : SA_DIS); 1177 1178 if (flags.mask & BR_FLOOD) 1179 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1180 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1181 1182 if (flags.mask & BR_MCAST_FLOOD) 1183 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1184 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1185 1186 if (flags.mask & BR_BCAST_FLOOD) 1187 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1188 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1189 1190 return 0; 1191 } 1192 1193 static int 1194 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1195 struct dsa_bridge bridge, bool *tx_fwd_offload, 1196 struct netlink_ext_ack *extack) 1197 { 1198 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1199 struct dsa_port *cpu_dp = dp->cpu_dp; 1200 u32 port_bitmap = BIT(cpu_dp->index); 1201 struct mt7530_priv *priv = ds->priv; 1202 1203 mutex_lock(&priv->reg_mutex); 1204 1205 dsa_switch_for_each_user_port(other_dp, ds) { 1206 int other_port = other_dp->index; 1207 1208 if (dp == other_dp) 1209 continue; 1210 1211 /* Add this port to the port matrix of the other ports in the 1212 * same bridge. If the port is disabled, port matrix is kept 1213 * and not being setup until the port becomes enabled. 1214 */ 1215 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1216 continue; 1217 1218 if (priv->ports[other_port].enable) 1219 mt7530_set(priv, MT7530_PCR_P(other_port), 1220 PCR_MATRIX(BIT(port))); 1221 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1222 1223 port_bitmap |= BIT(other_port); 1224 } 1225 1226 /* Add the all other ports to this port matrix. */ 1227 if (priv->ports[port].enable) 1228 mt7530_rmw(priv, MT7530_PCR_P(port), 1229 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1230 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1231 1232 /* Set to fallback mode for independent VLAN learning */ 1233 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1234 MT7530_PORT_FALLBACK_MODE); 1235 1236 mutex_unlock(&priv->reg_mutex); 1237 1238 return 0; 1239 } 1240 1241 static void 1242 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1243 { 1244 struct mt7530_priv *priv = ds->priv; 1245 bool all_user_ports_removed = true; 1246 int i; 1247 1248 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1249 * bridge. Don't set standalone ports to fallback mode. 1250 */ 1251 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1252 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1253 MT7530_PORT_FALLBACK_MODE); 1254 1255 mt7530_rmw(priv, MT7530_PVC_P(port), 1256 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1257 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1258 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1259 MT7530_VLAN_ACC_ALL); 1260 1261 /* Set PVID to 0 */ 1262 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1263 G0_PORT_VID_DEF); 1264 1265 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1266 if (dsa_is_user_port(ds, i) && 1267 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1268 all_user_ports_removed = false; 1269 break; 1270 } 1271 } 1272 1273 /* CPU port also does the same thing until all user ports belonging to 1274 * the CPU port get out of VLAN filtering mode. 1275 */ 1276 if (all_user_ports_removed) { 1277 struct dsa_port *dp = dsa_to_port(ds, port); 1278 struct dsa_port *cpu_dp = dp->cpu_dp; 1279 1280 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1281 PCR_MATRIX(dsa_user_ports(priv->ds))); 1282 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1283 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1284 } 1285 } 1286 1287 static void 1288 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1289 { 1290 struct mt7530_priv *priv = ds->priv; 1291 1292 /* Trapped into security mode allows packet forwarding through VLAN 1293 * table lookup. 1294 */ 1295 if (dsa_is_user_port(ds, port)) { 1296 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1297 MT7530_PORT_SECURITY_MODE); 1298 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1299 G0_PORT_VID(priv->ports[port].pvid)); 1300 1301 /* Only accept tagged frames if PVID is not set */ 1302 if (!priv->ports[port].pvid) 1303 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1304 MT7530_VLAN_ACC_TAGGED); 1305 1306 /* Set the port as a user port which is to be able to recognize 1307 * VID from incoming packets before fetching entry within the 1308 * VLAN table. 1309 */ 1310 mt7530_rmw(priv, MT7530_PVC_P(port), 1311 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1312 VLAN_ATTR(MT7530_VLAN_USER) | 1313 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1314 } else { 1315 /* Also set CPU ports to the "user" VLAN port attribute, to 1316 * allow VLAN classification, but keep the EG_TAG attribute as 1317 * "consistent" (i.o.w. don't change its value) for packets 1318 * received by the switch from the CPU, so that tagged packets 1319 * are forwarded to user ports as tagged, and untagged as 1320 * untagged. 1321 */ 1322 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1323 VLAN_ATTR(MT7530_VLAN_USER)); 1324 } 1325 } 1326 1327 static void 1328 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1329 struct dsa_bridge bridge) 1330 { 1331 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1332 struct dsa_port *cpu_dp = dp->cpu_dp; 1333 struct mt7530_priv *priv = ds->priv; 1334 1335 mutex_lock(&priv->reg_mutex); 1336 1337 dsa_switch_for_each_user_port(other_dp, ds) { 1338 int other_port = other_dp->index; 1339 1340 if (dp == other_dp) 1341 continue; 1342 1343 /* Remove this port from the port matrix of the other ports 1344 * in the same bridge. If the port is disabled, port matrix 1345 * is kept and not being setup until the port becomes enabled. 1346 */ 1347 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1348 continue; 1349 1350 if (priv->ports[other_port].enable) 1351 mt7530_clear(priv, MT7530_PCR_P(other_port), 1352 PCR_MATRIX(BIT(port))); 1353 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1354 } 1355 1356 /* Set the cpu port to be the only one in the port matrix of 1357 * this port. 1358 */ 1359 if (priv->ports[port].enable) 1360 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1361 PCR_MATRIX(BIT(cpu_dp->index))); 1362 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1363 1364 /* When a port is removed from the bridge, the port would be set up 1365 * back to the default as is at initial boot which is a VLAN-unaware 1366 * port. 1367 */ 1368 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1369 MT7530_PORT_MATRIX_MODE); 1370 1371 mutex_unlock(&priv->reg_mutex); 1372 } 1373 1374 static int 1375 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1376 const unsigned char *addr, u16 vid, 1377 struct dsa_db db) 1378 { 1379 struct mt7530_priv *priv = ds->priv; 1380 int ret; 1381 u8 port_mask = BIT(port); 1382 1383 mutex_lock(&priv->reg_mutex); 1384 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1385 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1386 mutex_unlock(&priv->reg_mutex); 1387 1388 return ret; 1389 } 1390 1391 static int 1392 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1393 const unsigned char *addr, u16 vid, 1394 struct dsa_db db) 1395 { 1396 struct mt7530_priv *priv = ds->priv; 1397 int ret; 1398 u8 port_mask = BIT(port); 1399 1400 mutex_lock(&priv->reg_mutex); 1401 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1402 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1403 mutex_unlock(&priv->reg_mutex); 1404 1405 return ret; 1406 } 1407 1408 static int 1409 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1410 dsa_fdb_dump_cb_t *cb, void *data) 1411 { 1412 struct mt7530_priv *priv = ds->priv; 1413 struct mt7530_fdb _fdb = { 0 }; 1414 int cnt = MT7530_NUM_FDB_RECORDS; 1415 int ret = 0; 1416 u32 rsp = 0; 1417 1418 mutex_lock(&priv->reg_mutex); 1419 1420 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1421 if (ret < 0) 1422 goto err; 1423 1424 do { 1425 if (rsp & ATC_SRCH_HIT) { 1426 mt7530_fdb_read(priv, &_fdb); 1427 if (_fdb.port_mask & BIT(port)) { 1428 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1429 data); 1430 if (ret < 0) 1431 break; 1432 } 1433 } 1434 } while (--cnt && 1435 !(rsp & ATC_SRCH_END) && 1436 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1437 err: 1438 mutex_unlock(&priv->reg_mutex); 1439 1440 return 0; 1441 } 1442 1443 static int 1444 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1445 const struct switchdev_obj_port_mdb *mdb, 1446 struct dsa_db db) 1447 { 1448 struct mt7530_priv *priv = ds->priv; 1449 const u8 *addr = mdb->addr; 1450 u16 vid = mdb->vid; 1451 u8 port_mask = 0; 1452 int ret; 1453 1454 mutex_lock(&priv->reg_mutex); 1455 1456 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1457 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1458 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1459 & PORT_MAP_MASK; 1460 1461 port_mask |= BIT(port); 1462 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1463 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1464 1465 mutex_unlock(&priv->reg_mutex); 1466 1467 return ret; 1468 } 1469 1470 static int 1471 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1472 const struct switchdev_obj_port_mdb *mdb, 1473 struct dsa_db db) 1474 { 1475 struct mt7530_priv *priv = ds->priv; 1476 const u8 *addr = mdb->addr; 1477 u16 vid = mdb->vid; 1478 u8 port_mask = 0; 1479 int ret; 1480 1481 mutex_lock(&priv->reg_mutex); 1482 1483 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1484 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1485 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1486 & PORT_MAP_MASK; 1487 1488 port_mask &= ~BIT(port); 1489 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1490 port_mask ? STATIC_ENT : STATIC_EMP); 1491 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1492 1493 mutex_unlock(&priv->reg_mutex); 1494 1495 return ret; 1496 } 1497 1498 static int 1499 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1500 { 1501 struct mt7530_dummy_poll p; 1502 u32 val; 1503 int ret; 1504 1505 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1506 mt7530_write(priv, MT7530_VTCR, val); 1507 1508 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1509 ret = readx_poll_timeout(_mt7530_read, &p, val, 1510 !(val & VTCR_BUSY), 20, 20000); 1511 if (ret < 0) { 1512 dev_err(priv->dev, "poll timeout\n"); 1513 return ret; 1514 } 1515 1516 val = mt7530_read(priv, MT7530_VTCR); 1517 if (val & VTCR_INVALID) { 1518 dev_err(priv->dev, "read VTCR invalid\n"); 1519 return -EINVAL; 1520 } 1521 1522 return 0; 1523 } 1524 1525 static int 1526 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1527 struct netlink_ext_ack *extack) 1528 { 1529 struct dsa_port *dp = dsa_to_port(ds, port); 1530 struct dsa_port *cpu_dp = dp->cpu_dp; 1531 1532 if (vlan_filtering) { 1533 /* The port is being kept as VLAN-unaware port when bridge is 1534 * set up with vlan_filtering not being set, Otherwise, the 1535 * port and the corresponding CPU port is required the setup 1536 * for becoming a VLAN-aware port. 1537 */ 1538 mt7530_port_set_vlan_aware(ds, port); 1539 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1540 } else { 1541 mt7530_port_set_vlan_unaware(ds, port); 1542 } 1543 1544 return 0; 1545 } 1546 1547 static void 1548 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1549 struct mt7530_hw_vlan_entry *entry) 1550 { 1551 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1552 u8 new_members; 1553 u32 val; 1554 1555 new_members = entry->old_members | BIT(entry->port); 1556 1557 /* Validate the entry with independent learning, create egress tag per 1558 * VLAN and joining the port as one of the port members. 1559 */ 1560 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1561 VLAN_VALID; 1562 mt7530_write(priv, MT7530_VAWD1, val); 1563 1564 /* Decide whether adding tag or not for those outgoing packets from the 1565 * port inside the VLAN. 1566 * CPU port is always taken as a tagged port for serving more than one 1567 * VLANs across and also being applied with egress type stack mode for 1568 * that VLAN tags would be appended after hardware special tag used as 1569 * DSA tag. 1570 */ 1571 if (dsa_port_is_cpu(dp)) 1572 val = MT7530_VLAN_EGRESS_STACK; 1573 else if (entry->untagged) 1574 val = MT7530_VLAN_EGRESS_UNTAG; 1575 else 1576 val = MT7530_VLAN_EGRESS_TAG; 1577 mt7530_rmw(priv, MT7530_VAWD2, 1578 ETAG_CTRL_P_MASK(entry->port), 1579 ETAG_CTRL_P(entry->port, val)); 1580 } 1581 1582 static void 1583 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1584 struct mt7530_hw_vlan_entry *entry) 1585 { 1586 u8 new_members; 1587 u32 val; 1588 1589 new_members = entry->old_members & ~BIT(entry->port); 1590 1591 val = mt7530_read(priv, MT7530_VAWD1); 1592 if (!(val & VLAN_VALID)) { 1593 dev_err(priv->dev, 1594 "Cannot be deleted due to invalid entry\n"); 1595 return; 1596 } 1597 1598 if (new_members) { 1599 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1600 VLAN_VALID; 1601 mt7530_write(priv, MT7530_VAWD1, val); 1602 } else { 1603 mt7530_write(priv, MT7530_VAWD1, 0); 1604 mt7530_write(priv, MT7530_VAWD2, 0); 1605 } 1606 } 1607 1608 static void 1609 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1610 struct mt7530_hw_vlan_entry *entry, 1611 mt7530_vlan_op vlan_op) 1612 { 1613 u32 val; 1614 1615 /* Fetch entry */ 1616 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1617 1618 val = mt7530_read(priv, MT7530_VAWD1); 1619 1620 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1621 1622 /* Manipulate entry */ 1623 vlan_op(priv, entry); 1624 1625 /* Flush result to hardware */ 1626 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1627 } 1628 1629 static int 1630 mt7530_setup_vlan0(struct mt7530_priv *priv) 1631 { 1632 u32 val; 1633 1634 /* Validate the entry with independent learning, keep the original 1635 * ingress tag attribute. 1636 */ 1637 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1638 VLAN_VALID; 1639 mt7530_write(priv, MT7530_VAWD1, val); 1640 1641 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1642 } 1643 1644 static int 1645 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1646 const struct switchdev_obj_port_vlan *vlan, 1647 struct netlink_ext_ack *extack) 1648 { 1649 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1650 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1651 struct mt7530_hw_vlan_entry new_entry; 1652 struct mt7530_priv *priv = ds->priv; 1653 1654 mutex_lock(&priv->reg_mutex); 1655 1656 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1657 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1658 1659 if (pvid) { 1660 priv->ports[port].pvid = vlan->vid; 1661 1662 /* Accept all frames if PVID is set */ 1663 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1664 MT7530_VLAN_ACC_ALL); 1665 1666 /* Only configure PVID if VLAN filtering is enabled */ 1667 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1668 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1669 G0_PORT_VID_MASK, 1670 G0_PORT_VID(vlan->vid)); 1671 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1672 /* This VLAN is overwritten without PVID, so unset it */ 1673 priv->ports[port].pvid = G0_PORT_VID_DEF; 1674 1675 /* Only accept tagged frames if the port is VLAN-aware */ 1676 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1677 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1678 MT7530_VLAN_ACC_TAGGED); 1679 1680 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1681 G0_PORT_VID_DEF); 1682 } 1683 1684 mutex_unlock(&priv->reg_mutex); 1685 1686 return 0; 1687 } 1688 1689 static int 1690 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1691 const struct switchdev_obj_port_vlan *vlan) 1692 { 1693 struct mt7530_hw_vlan_entry target_entry; 1694 struct mt7530_priv *priv = ds->priv; 1695 1696 mutex_lock(&priv->reg_mutex); 1697 1698 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1699 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1700 mt7530_hw_vlan_del); 1701 1702 /* PVID is being restored to the default whenever the PVID port 1703 * is being removed from the VLAN. 1704 */ 1705 if (priv->ports[port].pvid == vlan->vid) { 1706 priv->ports[port].pvid = G0_PORT_VID_DEF; 1707 1708 /* Only accept tagged frames if the port is VLAN-aware */ 1709 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1710 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1711 MT7530_VLAN_ACC_TAGGED); 1712 1713 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1714 G0_PORT_VID_DEF); 1715 } 1716 1717 1718 mutex_unlock(&priv->reg_mutex); 1719 1720 return 0; 1721 } 1722 1723 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1724 { 1725 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1726 MIRROR_PORT(val); 1727 } 1728 1729 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1730 { 1731 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1732 MIRROR_PORT(val); 1733 } 1734 1735 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1736 struct dsa_mall_mirror_tc_entry *mirror, 1737 bool ingress, struct netlink_ext_ack *extack) 1738 { 1739 struct mt7530_priv *priv = ds->priv; 1740 int monitor_port; 1741 u32 val; 1742 1743 /* Check for existent entry */ 1744 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1745 return -EEXIST; 1746 1747 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1748 1749 /* MT7530 only supports one monitor port */ 1750 monitor_port = mt753x_mirror_port_get(priv->id, val); 1751 if (val & MT753X_MIRROR_EN(priv->id) && 1752 monitor_port != mirror->to_local_port) 1753 return -EEXIST; 1754 1755 val |= MT753X_MIRROR_EN(priv->id); 1756 val &= ~MT753X_MIRROR_MASK(priv->id); 1757 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1758 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1759 1760 val = mt7530_read(priv, MT7530_PCR_P(port)); 1761 if (ingress) { 1762 val |= PORT_RX_MIR; 1763 priv->mirror_rx |= BIT(port); 1764 } else { 1765 val |= PORT_TX_MIR; 1766 priv->mirror_tx |= BIT(port); 1767 } 1768 mt7530_write(priv, MT7530_PCR_P(port), val); 1769 1770 return 0; 1771 } 1772 1773 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1774 struct dsa_mall_mirror_tc_entry *mirror) 1775 { 1776 struct mt7530_priv *priv = ds->priv; 1777 u32 val; 1778 1779 val = mt7530_read(priv, MT7530_PCR_P(port)); 1780 if (mirror->ingress) { 1781 val &= ~PORT_RX_MIR; 1782 priv->mirror_rx &= ~BIT(port); 1783 } else { 1784 val &= ~PORT_TX_MIR; 1785 priv->mirror_tx &= ~BIT(port); 1786 } 1787 mt7530_write(priv, MT7530_PCR_P(port), val); 1788 1789 if (!priv->mirror_rx && !priv->mirror_tx) { 1790 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1791 val &= ~MT753X_MIRROR_EN(priv->id); 1792 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1793 } 1794 } 1795 1796 static enum dsa_tag_protocol 1797 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1798 enum dsa_tag_protocol mp) 1799 { 1800 return DSA_TAG_PROTO_MTK; 1801 } 1802 1803 #ifdef CONFIG_GPIOLIB 1804 static inline u32 1805 mt7530_gpio_to_bit(unsigned int offset) 1806 { 1807 /* Map GPIO offset to register bit 1808 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1809 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1810 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1811 * [14:12] port 3 LED 0..2 as GPIO 9..11 1812 * [18:16] port 4 LED 0..2 as GPIO 12..14 1813 */ 1814 return BIT(offset + offset / 3); 1815 } 1816 1817 static int 1818 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1819 { 1820 struct mt7530_priv *priv = gpiochip_get_data(gc); 1821 u32 bit = mt7530_gpio_to_bit(offset); 1822 1823 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1824 } 1825 1826 static void 1827 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1828 { 1829 struct mt7530_priv *priv = gpiochip_get_data(gc); 1830 u32 bit = mt7530_gpio_to_bit(offset); 1831 1832 if (value) 1833 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1834 else 1835 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1836 } 1837 1838 static int 1839 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1840 { 1841 struct mt7530_priv *priv = gpiochip_get_data(gc); 1842 u32 bit = mt7530_gpio_to_bit(offset); 1843 1844 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1845 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1846 } 1847 1848 static int 1849 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1850 { 1851 struct mt7530_priv *priv = gpiochip_get_data(gc); 1852 u32 bit = mt7530_gpio_to_bit(offset); 1853 1854 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1855 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1856 1857 return 0; 1858 } 1859 1860 static int 1861 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1862 { 1863 struct mt7530_priv *priv = gpiochip_get_data(gc); 1864 u32 bit = mt7530_gpio_to_bit(offset); 1865 1866 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1867 1868 if (value) 1869 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1870 else 1871 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1872 1873 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1874 1875 return 0; 1876 } 1877 1878 static int 1879 mt7530_setup_gpio(struct mt7530_priv *priv) 1880 { 1881 struct device *dev = priv->dev; 1882 struct gpio_chip *gc; 1883 1884 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1885 if (!gc) 1886 return -ENOMEM; 1887 1888 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1889 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1890 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1891 1892 gc->label = "mt7530"; 1893 gc->parent = dev; 1894 gc->owner = THIS_MODULE; 1895 gc->get_direction = mt7530_gpio_get_direction; 1896 gc->direction_input = mt7530_gpio_direction_input; 1897 gc->direction_output = mt7530_gpio_direction_output; 1898 gc->get = mt7530_gpio_get; 1899 gc->set = mt7530_gpio_set; 1900 gc->base = -1; 1901 gc->ngpio = 15; 1902 gc->can_sleep = true; 1903 1904 return devm_gpiochip_add_data(dev, gc, priv); 1905 } 1906 #endif /* CONFIG_GPIOLIB */ 1907 1908 static irqreturn_t 1909 mt7530_irq_thread_fn(int irq, void *dev_id) 1910 { 1911 struct mt7530_priv *priv = dev_id; 1912 bool handled = false; 1913 u32 val; 1914 int p; 1915 1916 mt7530_mutex_lock(priv); 1917 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1918 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1919 mt7530_mutex_unlock(priv); 1920 1921 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1922 if (BIT(p) & val) { 1923 unsigned int irq; 1924 1925 irq = irq_find_mapping(priv->irq_domain, p); 1926 handle_nested_irq(irq); 1927 handled = true; 1928 } 1929 } 1930 1931 return IRQ_RETVAL(handled); 1932 } 1933 1934 static void 1935 mt7530_irq_mask(struct irq_data *d) 1936 { 1937 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1938 1939 priv->irq_enable &= ~BIT(d->hwirq); 1940 } 1941 1942 static void 1943 mt7530_irq_unmask(struct irq_data *d) 1944 { 1945 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1946 1947 priv->irq_enable |= BIT(d->hwirq); 1948 } 1949 1950 static void 1951 mt7530_irq_bus_lock(struct irq_data *d) 1952 { 1953 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1954 1955 mt7530_mutex_lock(priv); 1956 } 1957 1958 static void 1959 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1960 { 1961 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1962 1963 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1964 mt7530_mutex_unlock(priv); 1965 } 1966 1967 static struct irq_chip mt7530_irq_chip = { 1968 .name = KBUILD_MODNAME, 1969 .irq_mask = mt7530_irq_mask, 1970 .irq_unmask = mt7530_irq_unmask, 1971 .irq_bus_lock = mt7530_irq_bus_lock, 1972 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1973 }; 1974 1975 static int 1976 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1977 irq_hw_number_t hwirq) 1978 { 1979 irq_set_chip_data(irq, domain->host_data); 1980 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1981 irq_set_nested_thread(irq, true); 1982 irq_set_noprobe(irq); 1983 1984 return 0; 1985 } 1986 1987 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1988 .map = mt7530_irq_map, 1989 .xlate = irq_domain_xlate_onecell, 1990 }; 1991 1992 static void 1993 mt7988_irq_mask(struct irq_data *d) 1994 { 1995 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1996 1997 priv->irq_enable &= ~BIT(d->hwirq); 1998 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1999 } 2000 2001 static void 2002 mt7988_irq_unmask(struct irq_data *d) 2003 { 2004 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2005 2006 priv->irq_enable |= BIT(d->hwirq); 2007 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2008 } 2009 2010 static struct irq_chip mt7988_irq_chip = { 2011 .name = KBUILD_MODNAME, 2012 .irq_mask = mt7988_irq_mask, 2013 .irq_unmask = mt7988_irq_unmask, 2014 }; 2015 2016 static int 2017 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2018 irq_hw_number_t hwirq) 2019 { 2020 irq_set_chip_data(irq, domain->host_data); 2021 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2022 irq_set_nested_thread(irq, true); 2023 irq_set_noprobe(irq); 2024 2025 return 0; 2026 } 2027 2028 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2029 .map = mt7988_irq_map, 2030 .xlate = irq_domain_xlate_onecell, 2031 }; 2032 2033 static void 2034 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2035 { 2036 struct dsa_switch *ds = priv->ds; 2037 int p; 2038 2039 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2040 if (BIT(p) & ds->phys_mii_mask) { 2041 unsigned int irq; 2042 2043 irq = irq_create_mapping(priv->irq_domain, p); 2044 ds->user_mii_bus->irq[p] = irq; 2045 } 2046 } 2047 } 2048 2049 static int 2050 mt7530_setup_irq(struct mt7530_priv *priv) 2051 { 2052 struct device *dev = priv->dev; 2053 struct device_node *np = dev->of_node; 2054 int ret; 2055 2056 if (!of_property_read_bool(np, "interrupt-controller")) { 2057 dev_info(dev, "no interrupt support\n"); 2058 return 0; 2059 } 2060 2061 priv->irq = of_irq_get(np, 0); 2062 if (priv->irq <= 0) { 2063 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2064 return priv->irq ? : -EINVAL; 2065 } 2066 2067 if (priv->id == ID_MT7988) 2068 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2069 &mt7988_irq_domain_ops, 2070 priv); 2071 else 2072 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2073 &mt7530_irq_domain_ops, 2074 priv); 2075 2076 if (!priv->irq_domain) { 2077 dev_err(dev, "failed to create IRQ domain\n"); 2078 return -ENOMEM; 2079 } 2080 2081 /* This register must be set for MT7530 to properly fire interrupts */ 2082 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2083 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2084 2085 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2086 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2087 if (ret) { 2088 irq_domain_remove(priv->irq_domain); 2089 dev_err(dev, "failed to request IRQ: %d\n", ret); 2090 return ret; 2091 } 2092 2093 return 0; 2094 } 2095 2096 static void 2097 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2098 { 2099 int p; 2100 2101 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2102 if (BIT(p) & priv->ds->phys_mii_mask) { 2103 unsigned int irq; 2104 2105 irq = irq_find_mapping(priv->irq_domain, p); 2106 irq_dispose_mapping(irq); 2107 } 2108 } 2109 } 2110 2111 static void 2112 mt7530_free_irq_common(struct mt7530_priv *priv) 2113 { 2114 free_irq(priv->irq, priv); 2115 irq_domain_remove(priv->irq_domain); 2116 } 2117 2118 static void 2119 mt7530_free_irq(struct mt7530_priv *priv) 2120 { 2121 struct device_node *mnp, *np = priv->dev->of_node; 2122 2123 mnp = of_get_child_by_name(np, "mdio"); 2124 if (!mnp) 2125 mt7530_free_mdio_irq(priv); 2126 of_node_put(mnp); 2127 2128 mt7530_free_irq_common(priv); 2129 } 2130 2131 static int 2132 mt7530_setup_mdio(struct mt7530_priv *priv) 2133 { 2134 struct device_node *mnp, *np = priv->dev->of_node; 2135 struct dsa_switch *ds = priv->ds; 2136 struct device *dev = priv->dev; 2137 struct mii_bus *bus; 2138 static int idx; 2139 int ret = 0; 2140 2141 mnp = of_get_child_by_name(np, "mdio"); 2142 2143 if (mnp && !of_device_is_available(mnp)) 2144 goto out; 2145 2146 bus = devm_mdiobus_alloc(dev); 2147 if (!bus) { 2148 ret = -ENOMEM; 2149 goto out; 2150 } 2151 2152 if (!mnp) 2153 ds->user_mii_bus = bus; 2154 2155 bus->priv = priv; 2156 bus->name = KBUILD_MODNAME "-mii"; 2157 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2158 bus->read = mt753x_phy_read_c22; 2159 bus->write = mt753x_phy_write_c22; 2160 bus->read_c45 = mt753x_phy_read_c45; 2161 bus->write_c45 = mt753x_phy_write_c45; 2162 bus->parent = dev; 2163 bus->phy_mask = ~ds->phys_mii_mask; 2164 2165 if (priv->irq && !mnp) 2166 mt7530_setup_mdio_irq(priv); 2167 2168 ret = devm_of_mdiobus_register(dev, bus, mnp); 2169 if (ret) { 2170 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2171 if (priv->irq && !mnp) 2172 mt7530_free_mdio_irq(priv); 2173 } 2174 2175 out: 2176 of_node_put(mnp); 2177 return ret; 2178 } 2179 2180 static int 2181 mt7530_setup(struct dsa_switch *ds) 2182 { 2183 struct mt7530_priv *priv = ds->priv; 2184 struct device_node *dn = NULL; 2185 struct device_node *phy_node; 2186 struct device_node *mac_np; 2187 struct mt7530_dummy_poll p; 2188 phy_interface_t interface; 2189 struct dsa_port *cpu_dp; 2190 u32 id, val; 2191 int ret, i; 2192 2193 /* The parent node of conduit netdev which holds the common system 2194 * controller also is the container for two GMACs nodes representing 2195 * as two netdev instances. 2196 */ 2197 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2198 dn = cpu_dp->conduit->dev.of_node->parent; 2199 /* It doesn't matter which CPU port is found first, 2200 * their conduits should share the same parent OF node 2201 */ 2202 break; 2203 } 2204 2205 if (!dn) { 2206 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2207 return -EINVAL; 2208 } 2209 2210 ds->assisted_learning_on_cpu_port = true; 2211 ds->mtu_enforcement_ingress = true; 2212 2213 if (priv->id == ID_MT7530) { 2214 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2215 ret = regulator_enable(priv->core_pwr); 2216 if (ret < 0) { 2217 dev_err(priv->dev, 2218 "Failed to enable core power: %d\n", ret); 2219 return ret; 2220 } 2221 2222 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2223 ret = regulator_enable(priv->io_pwr); 2224 if (ret < 0) { 2225 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2226 ret); 2227 return ret; 2228 } 2229 } 2230 2231 /* Reset whole chip through gpio pin or memory-mapped registers for 2232 * different type of hardware 2233 */ 2234 if (priv->mcm) { 2235 reset_control_assert(priv->rstc); 2236 usleep_range(5000, 5100); 2237 reset_control_deassert(priv->rstc); 2238 } else { 2239 gpiod_set_value_cansleep(priv->reset, 0); 2240 usleep_range(5000, 5100); 2241 gpiod_set_value_cansleep(priv->reset, 1); 2242 } 2243 2244 /* Waiting for MT7530 got to stable */ 2245 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2246 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2247 20, 1000000); 2248 if (ret < 0) { 2249 dev_err(priv->dev, "reset timeout\n"); 2250 return ret; 2251 } 2252 2253 id = mt7530_read(priv, MT7530_CREV); 2254 id >>= CHIP_NAME_SHIFT; 2255 if (id != MT7530_ID) { 2256 dev_err(priv->dev, "chip %x can't be supported\n", id); 2257 return -ENODEV; 2258 } 2259 2260 if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) { 2261 dev_err(priv->dev, 2262 "MT7530 with a 20MHz XTAL is not supported!\n"); 2263 return -EINVAL; 2264 } 2265 2266 /* Reset the switch through internal reset */ 2267 mt7530_write(priv, MT7530_SYS_CTRL, 2268 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2269 SYS_CTRL_REG_RST); 2270 2271 mt7530_pll_setup(priv); 2272 2273 /* Lower Tx driving for TRGMII path */ 2274 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2275 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2276 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2277 2278 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2279 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2280 RD_TAP_MASK, RD_TAP(16)); 2281 2282 /* Enable port 6 */ 2283 val = mt7530_read(priv, MT7530_MHWTRAP); 2284 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2285 val |= MHWTRAP_MANUAL; 2286 mt7530_write(priv, MT7530_MHWTRAP, val); 2287 2288 mt753x_trap_frames(priv); 2289 2290 /* Enable and reset MIB counters */ 2291 mt7530_mib_reset(ds); 2292 2293 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2294 /* Clear link settings and enable force mode to force link down 2295 * on all ports until they're enabled later. 2296 */ 2297 mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | 2298 PMCR_FORCE_MODE, PMCR_FORCE_MODE); 2299 2300 /* Disable forwarding by default on all ports */ 2301 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2302 PCR_MATRIX_CLR); 2303 2304 /* Disable learning by default on all ports */ 2305 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2306 2307 if (dsa_is_cpu_port(ds, i)) { 2308 mt753x_cpu_port_enable(ds, i); 2309 } else { 2310 mt7530_port_disable(ds, i); 2311 2312 /* Set default PVID to 0 on all user ports */ 2313 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2314 G0_PORT_VID_DEF); 2315 } 2316 /* Enable consistent egress tag */ 2317 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2318 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2319 } 2320 2321 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2322 ret = mt7530_setup_vlan0(priv); 2323 if (ret) 2324 return ret; 2325 2326 /* Setup port 5 */ 2327 if (!dsa_is_unused_port(ds, 5)) { 2328 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2329 } else { 2330 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2331 * Set priv->p5_intf_sel to the appropriate value if PHY muxing 2332 * is detected. 2333 */ 2334 for_each_child_of_node(dn, mac_np) { 2335 if (!of_device_is_compatible(mac_np, 2336 "mediatek,eth-mac")) 2337 continue; 2338 2339 ret = of_property_read_u32(mac_np, "reg", &id); 2340 if (ret < 0 || id != 1) 2341 continue; 2342 2343 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2344 if (!phy_node) 2345 continue; 2346 2347 if (phy_node->parent == priv->dev->of_node->parent) { 2348 ret = of_get_phy_mode(mac_np, &interface); 2349 if (ret && ret != -ENODEV) { 2350 of_node_put(mac_np); 2351 of_node_put(phy_node); 2352 return ret; 2353 } 2354 id = of_mdio_parse_addr(ds->dev, phy_node); 2355 if (id == 0) 2356 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2357 if (id == 4) 2358 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2359 } 2360 of_node_put(mac_np); 2361 of_node_put(phy_node); 2362 break; 2363 } 2364 2365 if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || 2366 priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) 2367 mt7530_setup_port5(ds, interface); 2368 } 2369 2370 #ifdef CONFIG_GPIOLIB 2371 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2372 ret = mt7530_setup_gpio(priv); 2373 if (ret) 2374 return ret; 2375 } 2376 #endif /* CONFIG_GPIOLIB */ 2377 2378 /* Flush the FDB table */ 2379 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2380 if (ret < 0) 2381 return ret; 2382 2383 return 0; 2384 } 2385 2386 static int 2387 mt7531_setup_common(struct dsa_switch *ds) 2388 { 2389 struct mt7530_priv *priv = ds->priv; 2390 int ret, i; 2391 2392 mt753x_trap_frames(priv); 2393 2394 /* Enable and reset MIB counters */ 2395 mt7530_mib_reset(ds); 2396 2397 /* Disable flooding on all ports */ 2398 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2399 UNU_FFP_MASK); 2400 2401 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2402 /* Clear link settings and enable force mode to force link down 2403 * on all ports until they're enabled later. 2404 */ 2405 mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | 2406 MT7531_FORCE_MODE, MT7531_FORCE_MODE); 2407 2408 /* Disable forwarding by default on all ports */ 2409 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2410 PCR_MATRIX_CLR); 2411 2412 /* Disable learning by default on all ports */ 2413 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2414 2415 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2416 2417 if (dsa_is_cpu_port(ds, i)) { 2418 mt753x_cpu_port_enable(ds, i); 2419 } else { 2420 mt7530_port_disable(ds, i); 2421 2422 /* Set default PVID to 0 on all user ports */ 2423 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2424 G0_PORT_VID_DEF); 2425 } 2426 2427 /* Enable consistent egress tag */ 2428 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2429 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2430 } 2431 2432 /* Flush the FDB table */ 2433 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2434 if (ret < 0) 2435 return ret; 2436 2437 return 0; 2438 } 2439 2440 static int 2441 mt7531_setup(struct dsa_switch *ds) 2442 { 2443 struct mt7530_priv *priv = ds->priv; 2444 struct mt7530_dummy_poll p; 2445 u32 val, id; 2446 int ret, i; 2447 2448 /* Reset whole chip through gpio pin or memory-mapped registers for 2449 * different type of hardware 2450 */ 2451 if (priv->mcm) { 2452 reset_control_assert(priv->rstc); 2453 usleep_range(5000, 5100); 2454 reset_control_deassert(priv->rstc); 2455 } else { 2456 gpiod_set_value_cansleep(priv->reset, 0); 2457 usleep_range(5000, 5100); 2458 gpiod_set_value_cansleep(priv->reset, 1); 2459 } 2460 2461 /* Waiting for MT7530 got to stable */ 2462 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2463 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2464 20, 1000000); 2465 if (ret < 0) { 2466 dev_err(priv->dev, "reset timeout\n"); 2467 return ret; 2468 } 2469 2470 id = mt7530_read(priv, MT7531_CREV); 2471 id >>= CHIP_NAME_SHIFT; 2472 2473 if (id != MT7531_ID) { 2474 dev_err(priv->dev, "chip %x can't be supported\n", id); 2475 return -ENODEV; 2476 } 2477 2478 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2479 * MT7531BE has got only one SGMII unit which is for port 6. 2480 */ 2481 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2482 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2483 2484 /* Force link down on all ports before internal reset */ 2485 for (i = 0; i < MT7530_NUM_PORTS; i++) 2486 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2487 2488 /* Reset the switch through internal reset */ 2489 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2490 2491 if (!priv->p5_sgmii) { 2492 mt7531_pll_setup(priv); 2493 } else { 2494 /* Let ds->user_mii_bus be able to access external phy. */ 2495 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2496 MT7531_EXT_P_MDC_11); 2497 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2498 MT7531_EXT_P_MDIO_12); 2499 } 2500 2501 if (!dsa_is_unused_port(ds, 5)) 2502 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2503 2504 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2505 MT7531_GPIO0_INTERRUPT); 2506 2507 /* Enable PHY core PLL, since phy_device has not yet been created 2508 * provided for phy_[read,write]_mmd_indirect is called, we provide 2509 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2510 * function. 2511 */ 2512 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2513 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2514 val |= MT7531_PHY_PLL_BYPASS_MODE; 2515 val &= ~MT7531_PHY_PLL_OFF; 2516 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2517 CORE_PLL_GROUP4, val); 2518 2519 mt7531_setup_common(ds); 2520 2521 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2522 ret = mt7530_setup_vlan0(priv); 2523 if (ret) 2524 return ret; 2525 2526 ds->assisted_learning_on_cpu_port = true; 2527 ds->mtu_enforcement_ingress = true; 2528 2529 return 0; 2530 } 2531 2532 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2533 struct phylink_config *config) 2534 { 2535 switch (port) { 2536 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2537 case 0 ... 4: 2538 __set_bit(PHY_INTERFACE_MODE_GMII, 2539 config->supported_interfaces); 2540 break; 2541 2542 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2543 case 5: 2544 phy_interface_set_rgmii(config->supported_interfaces); 2545 __set_bit(PHY_INTERFACE_MODE_MII, 2546 config->supported_interfaces); 2547 __set_bit(PHY_INTERFACE_MODE_GMII, 2548 config->supported_interfaces); 2549 break; 2550 2551 /* Port 6 supports rgmii and trgmii. */ 2552 case 6: 2553 __set_bit(PHY_INTERFACE_MODE_RGMII, 2554 config->supported_interfaces); 2555 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2556 config->supported_interfaces); 2557 break; 2558 } 2559 } 2560 2561 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2562 struct phylink_config *config) 2563 { 2564 struct mt7530_priv *priv = ds->priv; 2565 2566 switch (port) { 2567 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2568 case 0 ... 4: 2569 __set_bit(PHY_INTERFACE_MODE_GMII, 2570 config->supported_interfaces); 2571 break; 2572 2573 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2574 * MT7531AE. 2575 */ 2576 case 5: 2577 if (!priv->p5_sgmii) { 2578 phy_interface_set_rgmii(config->supported_interfaces); 2579 break; 2580 } 2581 fallthrough; 2582 2583 /* Port 6 supports sgmii/802.3z. */ 2584 case 6: 2585 __set_bit(PHY_INTERFACE_MODE_SGMII, 2586 config->supported_interfaces); 2587 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2588 config->supported_interfaces); 2589 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2590 config->supported_interfaces); 2591 2592 config->mac_capabilities |= MAC_2500FD; 2593 break; 2594 } 2595 } 2596 2597 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2598 struct phylink_config *config) 2599 { 2600 switch (port) { 2601 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2602 case 0 ... 3: 2603 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2604 config->supported_interfaces); 2605 break; 2606 2607 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2608 case 6: 2609 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2610 config->supported_interfaces); 2611 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2612 MAC_10000FD; 2613 } 2614 } 2615 2616 static void 2617 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2618 phy_interface_t interface) 2619 { 2620 struct mt7530_priv *priv = ds->priv; 2621 2622 if (port == 5) 2623 mt7530_setup_port5(priv->ds, interface); 2624 else if (port == 6) 2625 mt7530_setup_port6(priv->ds, interface); 2626 } 2627 2628 static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2629 phy_interface_t interface, 2630 struct phy_device *phydev) 2631 { 2632 u32 val; 2633 2634 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2635 val |= GP_CLK_EN; 2636 val &= ~GP_MODE_MASK; 2637 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2638 val &= ~CLK_SKEW_IN_MASK; 2639 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2640 val &= ~CLK_SKEW_OUT_MASK; 2641 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2642 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2643 2644 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2645 if (!phydev || phy_driver_is_genphy(phydev)) { 2646 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2647 switch (interface) { 2648 case PHY_INTERFACE_MODE_RGMII: 2649 val |= TXCLK_NO_REVERSE; 2650 val |= RXCLK_NO_DELAY; 2651 break; 2652 case PHY_INTERFACE_MODE_RGMII_RXID: 2653 val |= TXCLK_NO_REVERSE; 2654 break; 2655 case PHY_INTERFACE_MODE_RGMII_TXID: 2656 val |= RXCLK_NO_DELAY; 2657 break; 2658 case PHY_INTERFACE_MODE_RGMII_ID: 2659 break; 2660 default: 2661 break; 2662 } 2663 } 2664 2665 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2666 } 2667 2668 static void 2669 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2670 phy_interface_t interface) 2671 { 2672 struct mt7530_priv *priv = ds->priv; 2673 struct phy_device *phydev; 2674 struct dsa_port *dp; 2675 2676 if (phy_interface_mode_is_rgmii(interface)) { 2677 dp = dsa_to_port(ds, port); 2678 phydev = dp->user->phydev; 2679 mt7531_rgmii_setup(priv, port, interface, phydev); 2680 } 2681 } 2682 2683 static struct phylink_pcs * 2684 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2685 phy_interface_t interface) 2686 { 2687 struct mt7530_priv *priv = ds->priv; 2688 2689 switch (interface) { 2690 case PHY_INTERFACE_MODE_TRGMII: 2691 return &priv->pcs[port].pcs; 2692 case PHY_INTERFACE_MODE_SGMII: 2693 case PHY_INTERFACE_MODE_1000BASEX: 2694 case PHY_INTERFACE_MODE_2500BASEX: 2695 return priv->ports[port].sgmii_pcs; 2696 default: 2697 return NULL; 2698 } 2699 } 2700 2701 static void 2702 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2703 const struct phylink_link_state *state) 2704 { 2705 struct mt7530_priv *priv = ds->priv; 2706 2707 if ((port == 5 || port == 6) && priv->info->mac_port_config) 2708 priv->info->mac_port_config(ds, port, mode, state->interface); 2709 2710 /* Are we connected to external phy */ 2711 if (port == 5 && dsa_is_user_port(ds, 5)) 2712 mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY); 2713 } 2714 2715 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2716 unsigned int mode, 2717 phy_interface_t interface) 2718 { 2719 struct mt7530_priv *priv = ds->priv; 2720 2721 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2722 } 2723 2724 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2725 unsigned int mode, 2726 phy_interface_t interface, 2727 struct phy_device *phydev, 2728 int speed, int duplex, 2729 bool tx_pause, bool rx_pause) 2730 { 2731 struct mt7530_priv *priv = ds->priv; 2732 u32 mcr; 2733 2734 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2735 2736 switch (speed) { 2737 case SPEED_1000: 2738 case SPEED_2500: 2739 case SPEED_10000: 2740 mcr |= PMCR_FORCE_SPEED_1000; 2741 break; 2742 case SPEED_100: 2743 mcr |= PMCR_FORCE_SPEED_100; 2744 break; 2745 } 2746 if (duplex == DUPLEX_FULL) { 2747 mcr |= PMCR_FORCE_FDX; 2748 if (tx_pause) 2749 mcr |= PMCR_TX_FC_EN; 2750 if (rx_pause) 2751 mcr |= PMCR_RX_FC_EN; 2752 } 2753 2754 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2755 switch (speed) { 2756 case SPEED_1000: 2757 case SPEED_2500: 2758 mcr |= PMCR_FORCE_EEE1G; 2759 break; 2760 case SPEED_100: 2761 mcr |= PMCR_FORCE_EEE100; 2762 break; 2763 } 2764 } 2765 2766 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2767 } 2768 2769 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2770 struct phylink_config *config) 2771 { 2772 struct mt7530_priv *priv = ds->priv; 2773 2774 /* This switch only supports full-duplex at 1Gbps */ 2775 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2776 MAC_10 | MAC_100 | MAC_1000FD; 2777 2778 priv->info->mac_port_get_caps(ds, port, config); 2779 } 2780 2781 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2782 unsigned long *supported, 2783 const struct phylink_link_state *state) 2784 { 2785 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2786 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2787 phy_interface_mode_is_8023z(state->interface)) 2788 phylink_clear(supported, Autoneg); 2789 2790 return 0; 2791 } 2792 2793 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2794 struct phylink_link_state *state) 2795 { 2796 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2797 int port = pcs_to_mt753x_pcs(pcs)->port; 2798 u32 pmsr; 2799 2800 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2801 2802 state->link = (pmsr & PMSR_LINK); 2803 state->an_complete = state->link; 2804 state->duplex = !!(pmsr & PMSR_DPX); 2805 2806 switch (pmsr & PMSR_SPEED_MASK) { 2807 case PMSR_SPEED_10: 2808 state->speed = SPEED_10; 2809 break; 2810 case PMSR_SPEED_100: 2811 state->speed = SPEED_100; 2812 break; 2813 case PMSR_SPEED_1000: 2814 state->speed = SPEED_1000; 2815 break; 2816 default: 2817 state->speed = SPEED_UNKNOWN; 2818 break; 2819 } 2820 2821 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2822 if (pmsr & PMSR_RX_FC) 2823 state->pause |= MLO_PAUSE_RX; 2824 if (pmsr & PMSR_TX_FC) 2825 state->pause |= MLO_PAUSE_TX; 2826 } 2827 2828 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 2829 phy_interface_t interface, 2830 const unsigned long *advertising, 2831 bool permit_pause_to_mac) 2832 { 2833 return 0; 2834 } 2835 2836 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 2837 { 2838 } 2839 2840 static const struct phylink_pcs_ops mt7530_pcs_ops = { 2841 .pcs_validate = mt753x_pcs_validate, 2842 .pcs_get_state = mt7530_pcs_get_state, 2843 .pcs_config = mt753x_pcs_config, 2844 .pcs_an_restart = mt7530_pcs_an_restart, 2845 }; 2846 2847 static int 2848 mt753x_setup(struct dsa_switch *ds) 2849 { 2850 struct mt7530_priv *priv = ds->priv; 2851 int ret = priv->info->sw_setup(ds); 2852 int i; 2853 2854 if (ret) 2855 return ret; 2856 2857 ret = mt7530_setup_irq(priv); 2858 if (ret) 2859 return ret; 2860 2861 ret = mt7530_setup_mdio(priv); 2862 if (ret && priv->irq) 2863 mt7530_free_irq_common(priv); 2864 2865 /* Initialise the PCS devices */ 2866 for (i = 0; i < priv->ds->num_ports; i++) { 2867 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 2868 priv->pcs[i].pcs.neg_mode = true; 2869 priv->pcs[i].priv = priv; 2870 priv->pcs[i].port = i; 2871 } 2872 2873 if (priv->create_sgmii) { 2874 ret = priv->create_sgmii(priv); 2875 if (ret && priv->irq) 2876 mt7530_free_irq(priv); 2877 } 2878 2879 return ret; 2880 } 2881 2882 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 2883 struct ethtool_keee *e) 2884 { 2885 struct mt7530_priv *priv = ds->priv; 2886 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 2887 2888 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 2889 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 2890 2891 return 0; 2892 } 2893 2894 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 2895 struct ethtool_keee *e) 2896 { 2897 struct mt7530_priv *priv = ds->priv; 2898 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 2899 2900 if (e->tx_lpi_timer > 0xFFF) 2901 return -EINVAL; 2902 2903 set = SET_LPI_THRESH(e->tx_lpi_timer); 2904 if (!e->tx_lpi_enabled) 2905 /* Force LPI Mode without a delay */ 2906 set |= LPI_MODE_EN; 2907 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 2908 2909 return 0; 2910 } 2911 2912 static void 2913 mt753x_conduit_state_change(struct dsa_switch *ds, 2914 const struct net_device *conduit, 2915 bool operational) 2916 { 2917 struct dsa_port *cpu_dp = conduit->dsa_ptr; 2918 struct mt7530_priv *priv = ds->priv; 2919 int val = 0; 2920 u8 mask; 2921 2922 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 2923 * forwarded to the numerically smallest CPU port whose conduit 2924 * interface is up. 2925 */ 2926 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 2927 return; 2928 2929 mask = BIT(cpu_dp->index); 2930 2931 if (operational) 2932 priv->active_cpu_ports |= mask; 2933 else 2934 priv->active_cpu_ports &= ~mask; 2935 2936 if (priv->active_cpu_ports) 2937 val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports)); 2938 2939 mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); 2940 } 2941 2942 static int mt7988_setup(struct dsa_switch *ds) 2943 { 2944 struct mt7530_priv *priv = ds->priv; 2945 2946 /* Reset the switch */ 2947 reset_control_assert(priv->rstc); 2948 usleep_range(20, 50); 2949 reset_control_deassert(priv->rstc); 2950 usleep_range(20, 50); 2951 2952 /* Reset the switch PHYs */ 2953 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 2954 2955 return mt7531_setup_common(ds); 2956 } 2957 2958 const struct dsa_switch_ops mt7530_switch_ops = { 2959 .get_tag_protocol = mtk_get_tag_protocol, 2960 .setup = mt753x_setup, 2961 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 2962 .get_strings = mt7530_get_strings, 2963 .get_ethtool_stats = mt7530_get_ethtool_stats, 2964 .get_sset_count = mt7530_get_sset_count, 2965 .set_ageing_time = mt7530_set_ageing_time, 2966 .port_enable = mt7530_port_enable, 2967 .port_disable = mt7530_port_disable, 2968 .port_change_mtu = mt7530_port_change_mtu, 2969 .port_max_mtu = mt7530_port_max_mtu, 2970 .port_stp_state_set = mt7530_stp_state_set, 2971 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 2972 .port_bridge_flags = mt7530_port_bridge_flags, 2973 .port_bridge_join = mt7530_port_bridge_join, 2974 .port_bridge_leave = mt7530_port_bridge_leave, 2975 .port_fdb_add = mt7530_port_fdb_add, 2976 .port_fdb_del = mt7530_port_fdb_del, 2977 .port_fdb_dump = mt7530_port_fdb_dump, 2978 .port_mdb_add = mt7530_port_mdb_add, 2979 .port_mdb_del = mt7530_port_mdb_del, 2980 .port_vlan_filtering = mt7530_port_vlan_filtering, 2981 .port_vlan_add = mt7530_port_vlan_add, 2982 .port_vlan_del = mt7530_port_vlan_del, 2983 .port_mirror_add = mt753x_port_mirror_add, 2984 .port_mirror_del = mt753x_port_mirror_del, 2985 .phylink_get_caps = mt753x_phylink_get_caps, 2986 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 2987 .phylink_mac_config = mt753x_phylink_mac_config, 2988 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 2989 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 2990 .get_mac_eee = mt753x_get_mac_eee, 2991 .set_mac_eee = mt753x_set_mac_eee, 2992 .conduit_state_change = mt753x_conduit_state_change, 2993 }; 2994 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 2995 2996 const struct mt753x_info mt753x_table[] = { 2997 [ID_MT7621] = { 2998 .id = ID_MT7621, 2999 .pcs_ops = &mt7530_pcs_ops, 3000 .sw_setup = mt7530_setup, 3001 .phy_read_c22 = mt7530_phy_read_c22, 3002 .phy_write_c22 = mt7530_phy_write_c22, 3003 .phy_read_c45 = mt7530_phy_read_c45, 3004 .phy_write_c45 = mt7530_phy_write_c45, 3005 .mac_port_get_caps = mt7530_mac_port_get_caps, 3006 .mac_port_config = mt7530_mac_config, 3007 }, 3008 [ID_MT7530] = { 3009 .id = ID_MT7530, 3010 .pcs_ops = &mt7530_pcs_ops, 3011 .sw_setup = mt7530_setup, 3012 .phy_read_c22 = mt7530_phy_read_c22, 3013 .phy_write_c22 = mt7530_phy_write_c22, 3014 .phy_read_c45 = mt7530_phy_read_c45, 3015 .phy_write_c45 = mt7530_phy_write_c45, 3016 .mac_port_get_caps = mt7530_mac_port_get_caps, 3017 .mac_port_config = mt7530_mac_config, 3018 }, 3019 [ID_MT7531] = { 3020 .id = ID_MT7531, 3021 .pcs_ops = &mt7530_pcs_ops, 3022 .sw_setup = mt7531_setup, 3023 .phy_read_c22 = mt7531_ind_c22_phy_read, 3024 .phy_write_c22 = mt7531_ind_c22_phy_write, 3025 .phy_read_c45 = mt7531_ind_c45_phy_read, 3026 .phy_write_c45 = mt7531_ind_c45_phy_write, 3027 .mac_port_get_caps = mt7531_mac_port_get_caps, 3028 .mac_port_config = mt7531_mac_config, 3029 }, 3030 [ID_MT7988] = { 3031 .id = ID_MT7988, 3032 .pcs_ops = &mt7530_pcs_ops, 3033 .sw_setup = mt7988_setup, 3034 .phy_read_c22 = mt7531_ind_c22_phy_read, 3035 .phy_write_c22 = mt7531_ind_c22_phy_write, 3036 .phy_read_c45 = mt7531_ind_c45_phy_read, 3037 .phy_write_c45 = mt7531_ind_c45_phy_write, 3038 .mac_port_get_caps = mt7988_mac_port_get_caps, 3039 }, 3040 }; 3041 EXPORT_SYMBOL_GPL(mt753x_table); 3042 3043 int 3044 mt7530_probe_common(struct mt7530_priv *priv) 3045 { 3046 struct device *dev = priv->dev; 3047 3048 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3049 if (!priv->ds) 3050 return -ENOMEM; 3051 3052 priv->ds->dev = dev; 3053 priv->ds->num_ports = MT7530_NUM_PORTS; 3054 3055 /* Get the hardware identifier from the devicetree node. 3056 * We will need it for some of the clock and regulator setup. 3057 */ 3058 priv->info = of_device_get_match_data(dev); 3059 if (!priv->info) 3060 return -EINVAL; 3061 3062 /* Sanity check if these required device operations are filled 3063 * properly. 3064 */ 3065 if (!priv->info->sw_setup || !priv->info->phy_read_c22 || 3066 !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps) 3067 return -EINVAL; 3068 3069 priv->id = priv->info->id; 3070 priv->dev = dev; 3071 priv->ds->priv = priv; 3072 priv->ds->ops = &mt7530_switch_ops; 3073 mutex_init(&priv->reg_mutex); 3074 dev_set_drvdata(dev, priv); 3075 3076 return 0; 3077 } 3078 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3079 3080 void 3081 mt7530_remove_common(struct mt7530_priv *priv) 3082 { 3083 if (priv->irq) 3084 mt7530_free_irq(priv); 3085 3086 dsa_unregister_switch(priv->ds); 3087 3088 mutex_destroy(&priv->reg_mutex); 3089 } 3090 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3091 3092 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3093 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3094 MODULE_LICENSE("GPL"); 3095