1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx NWL PCIe Root Port Bridge 8 9maintainers: 10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com> 11 12allOf: 13 - $ref: /schemas/pci/pci-bus.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 15 16properties: 17 compatible: 18 const: xlnx,nwl-pcie-2.11 19 20 reg: 21 items: 22 - description: PCIe bridge registers location. 23 - description: PCIe Controller registers location. 24 - description: PCIe Configuration space region. 25 26 reg-names: 27 items: 28 - const: breg 29 - const: pcireg 30 - const: cfg 31 32 interrupts: 33 items: 34 - description: interrupt asserted when miscellaneous interrupt is received 35 - description: unused interrupt(dummy) 36 - description: interrupt asserted when a legacy interrupt is received 37 - description: msi1 interrupt asserted when an MSI is received 38 - description: msi0 interrupt asserted when an MSI is received 39 40 interrupt-names: 41 items: 42 - const: misc 43 - const: dummy 44 - const: intx 45 - const: msi1 46 - const: msi0 47 48 interrupt-map-mask: 49 items: 50 - const: 0 51 - const: 0 52 - const: 0 53 - const: 7 54 55 "#interrupt-cells": 56 const: 1 57 58 msi-parent: 59 description: MSI controller the device is capable of using. 60 61 interrupt-map: 62 maxItems: 4 63 64 power-domains: 65 maxItems: 1 66 67 iommus: 68 maxItems: 1 69 70 dma-coherent: 71 description: optional, only needed if DMA operations are coherent. 72 73 clocks: 74 maxItems: 1 75 description: optional, input clock specifier. 76 77 legacy-interrupt-controller: 78 description: Interrupt controller node for handling legacy PCI interrupts. 79 type: object 80 properties: 81 "#address-cells": 82 const: 0 83 84 "#interrupt-cells": 85 const: 1 86 87 "interrupt-controller": true 88 89 required: 90 - "#address-cells" 91 - "#interrupt-cells" 92 - interrupt-controller 93 94 additionalProperties: false 95 96required: 97 - compatible 98 - reg 99 - reg-names 100 - interrupts 101 - "#interrupt-cells" 102 - interrupt-map 103 - interrupt-map-mask 104 - msi-controller 105 - power-domains 106 107unevaluatedProperties: false 108 109examples: 110 - | 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 112 #include <dt-bindings/interrupt-controller/irq.h> 113 #include <dt-bindings/power/xlnx-zynqmp-power.h> 114 soc { 115 #address-cells = <2>; 116 #size-cells = <2>; 117 nwl_pcie: pcie@fd0e0000 { 118 compatible = "xlnx,nwl-pcie-2.11"; 119 reg = <0x0 0xfd0e0000 0x0 0x1000>, 120 <0x0 0xfd480000 0x0 0x1000>, 121 <0x80 0x00000000 0x0 0x10000000>; 122 reg-names = "breg", "pcireg", "cfg"; 123 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, 124 <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; 125 #address-cells = <3>; 126 #size-cells = <2>; 127 #interrupt-cells = <1>; 128 msi-controller; 129 device_type = "pci"; 130 interrupt-parent = <&gic>; 131 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 132 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 133 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 134 interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; 135 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 136 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 137 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 138 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 139 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 140 msi-parent = <&nwl_pcie>; 141 power-domains = <&zynqmp_firmware PD_PCIE>; 142 iommus = <&smmu 0x4d0>; 143 pcie_intc: legacy-interrupt-controller { 144 interrupt-controller; 145 #address-cells = <0>; 146 #interrupt-cells = <1>; 147 }; 148 }; 149 }; 150