1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Mobile TPU PWM driver 4 * 5 * Copyright (C) 2012 Renesas Solutions Corp. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/init.h> 12 #include <linux/ioport.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pwm.h> 19 #include <linux/slab.h> 20 #include <linux/spinlock.h> 21 22 #define TPU_CHANNEL_MAX 4 23 24 #define TPU_TSTR 0x00 /* Timer start register (shared) */ 25 26 #define TPU_TCRn 0x00 /* Timer control register */ 27 #define TPU_TCR_CCLR_NONE (0 << 5) 28 #define TPU_TCR_CCLR_TGRA (1 << 5) 29 #define TPU_TCR_CCLR_TGRB (2 << 5) 30 #define TPU_TCR_CCLR_TGRC (5 << 5) 31 #define TPU_TCR_CCLR_TGRD (6 << 5) 32 #define TPU_TCR_CKEG_RISING (0 << 3) 33 #define TPU_TCR_CKEG_FALLING (1 << 3) 34 #define TPU_TCR_CKEG_BOTH (2 << 3) 35 #define TPU_TMDRn 0x04 /* Timer mode register */ 36 #define TPU_TMDR_BFWT (1 << 6) 37 #define TPU_TMDR_BFB (1 << 5) 38 #define TPU_TMDR_BFA (1 << 4) 39 #define TPU_TMDR_MD_NORMAL (0 << 0) 40 #define TPU_TMDR_MD_PWM (2 << 0) 41 #define TPU_TIORn 0x08 /* Timer I/O control register */ 42 #define TPU_TIOR_IOA_0 (0 << 0) 43 #define TPU_TIOR_IOA_0_CLR (1 << 0) 44 #define TPU_TIOR_IOA_0_SET (2 << 0) 45 #define TPU_TIOR_IOA_0_TOGGLE (3 << 0) 46 #define TPU_TIOR_IOA_1 (4 << 0) 47 #define TPU_TIOR_IOA_1_CLR (5 << 0) 48 #define TPU_TIOR_IOA_1_SET (6 << 0) 49 #define TPU_TIOR_IOA_1_TOGGLE (7 << 0) 50 #define TPU_TIERn 0x0c /* Timer interrupt enable register */ 51 #define TPU_TSRn 0x10 /* Timer status register */ 52 #define TPU_TCNTn 0x14 /* Timer counter */ 53 #define TPU_TGRAn 0x18 /* Timer general register A */ 54 #define TPU_TGRBn 0x1c /* Timer general register B */ 55 #define TPU_TGRCn 0x20 /* Timer general register C */ 56 #define TPU_TGRDn 0x24 /* Timer general register D */ 57 58 #define TPU_CHANNEL_OFFSET 0x10 59 #define TPU_CHANNEL_SIZE 0x40 60 61 enum tpu_pin_state { 62 TPU_PIN_INACTIVE, /* Pin is driven inactive */ 63 TPU_PIN_PWM, /* Pin is driven by PWM */ 64 TPU_PIN_ACTIVE, /* Pin is driven active */ 65 }; 66 67 struct tpu_device; 68 69 struct tpu_pwm_device { 70 bool timer_on; /* Whether the timer is running */ 71 72 struct tpu_device *tpu; 73 unsigned int channel; /* Channel number in the TPU */ 74 75 enum pwm_polarity polarity; 76 unsigned int prescaler; 77 u16 period; 78 u16 duty; 79 }; 80 81 struct tpu_device { 82 struct platform_device *pdev; 83 struct pwm_chip chip; 84 spinlock_t lock; 85 86 void __iomem *base; 87 struct clk *clk; 88 struct tpu_pwm_device tpd[TPU_CHANNEL_MAX]; 89 }; 90 91 #define to_tpu_device(c) container_of(c, struct tpu_device, chip) 92 93 static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value) 94 { 95 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET 96 + tpd->channel * TPU_CHANNEL_SIZE; 97 98 iowrite16(value, base + reg_nr); 99 } 100 101 static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd, 102 enum tpu_pin_state state) 103 { 104 static const char * const states[] = { "inactive", "PWM", "active" }; 105 106 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n", 107 tpd->channel, states[state]); 108 109 switch (state) { 110 case TPU_PIN_INACTIVE: 111 tpu_pwm_write(tpd, TPU_TIORn, 112 tpd->polarity == PWM_POLARITY_INVERSED ? 113 TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0); 114 break; 115 case TPU_PIN_PWM: 116 tpu_pwm_write(tpd, TPU_TIORn, 117 tpd->polarity == PWM_POLARITY_INVERSED ? 118 TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR); 119 break; 120 case TPU_PIN_ACTIVE: 121 tpu_pwm_write(tpd, TPU_TIORn, 122 tpd->polarity == PWM_POLARITY_INVERSED ? 123 TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1); 124 break; 125 } 126 } 127 128 static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start) 129 { 130 unsigned long flags; 131 u16 value; 132 133 spin_lock_irqsave(&tpd->tpu->lock, flags); 134 value = ioread16(tpd->tpu->base + TPU_TSTR); 135 136 if (start) 137 value |= 1 << tpd->channel; 138 else 139 value &= ~(1 << tpd->channel); 140 141 iowrite16(value, tpd->tpu->base + TPU_TSTR); 142 spin_unlock_irqrestore(&tpd->tpu->lock, flags); 143 } 144 145 static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd) 146 { 147 int ret; 148 149 if (!tpd->timer_on) { 150 /* Wake up device and enable clock. */ 151 pm_runtime_get_sync(&tpd->tpu->pdev->dev); 152 ret = clk_prepare_enable(tpd->tpu->clk); 153 if (ret) { 154 dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n"); 155 return ret; 156 } 157 tpd->timer_on = true; 158 } 159 160 /* 161 * Make sure the channel is stopped, as we need to reconfigure it 162 * completely. First drive the pin to the inactive state to avoid 163 * glitches. 164 */ 165 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE); 166 tpu_pwm_start_stop(tpd, false); 167 168 /* 169 * - Clear TCNT on TGRB match 170 * - Count on rising edge 171 * - Set prescaler 172 * - Output 0 until TGRA, output 1 until TGRB (active low polarity) 173 * - Output 1 until TGRA, output 0 until TGRB (active high polarity 174 * - PWM mode 175 */ 176 tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING | 177 tpd->prescaler); 178 tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM); 179 tpu_pwm_set_pin(tpd, TPU_PIN_PWM); 180 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); 181 tpu_pwm_write(tpd, TPU_TGRBn, tpd->period); 182 183 dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", 184 tpd->channel, tpd->duty, tpd->period); 185 186 /* Start the channel. */ 187 tpu_pwm_start_stop(tpd, true); 188 189 return 0; 190 } 191 192 static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd) 193 { 194 if (!tpd->timer_on) 195 return; 196 197 /* Disable channel. */ 198 tpu_pwm_start_stop(tpd, false); 199 200 /* Stop clock and mark device as idle. */ 201 clk_disable_unprepare(tpd->tpu->clk); 202 pm_runtime_put(&tpd->tpu->pdev->dev); 203 204 tpd->timer_on = false; 205 } 206 207 /* ----------------------------------------------------------------------------- 208 * PWM API 209 */ 210 211 static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 212 { 213 struct tpu_device *tpu = to_tpu_device(chip); 214 struct tpu_pwm_device *tpd; 215 216 if (pwm->hwpwm >= TPU_CHANNEL_MAX) 217 return -EINVAL; 218 219 tpd = &tpu->tpd[pwm->hwpwm]; 220 221 tpd->tpu = tpu; 222 tpd->channel = pwm->hwpwm; 223 tpd->polarity = PWM_POLARITY_NORMAL; 224 tpd->prescaler = 0; 225 tpd->period = 0; 226 tpd->duty = 0; 227 228 tpd->timer_on = false; 229 230 return 0; 231 } 232 233 static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 234 { 235 struct tpu_device *tpu = to_tpu_device(chip); 236 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 237 238 tpu_pwm_timer_stop(tpd); 239 } 240 241 static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 242 u64 duty_ns, u64 period_ns, bool enabled) 243 { 244 struct tpu_device *tpu = to_tpu_device(chip); 245 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 246 unsigned int prescaler; 247 bool duty_only = false; 248 u32 clk_rate; 249 u64 period; 250 u32 duty; 251 int ret; 252 253 clk_rate = clk_get_rate(tpu->clk); 254 if (unlikely(clk_rate > NSEC_PER_SEC)) { 255 /* 256 * This won't happen in the nearer future, so this is only a 257 * safeguard to prevent the following calculation from 258 * overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is 259 * not greater than period_ns and so fits into an u64. 260 */ 261 return -EINVAL; 262 } 263 264 period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC); 265 266 /* 267 * Find the minimal prescaler in [0..3] such that 268 * 269 * period >> (2 * prescaler) < 0x10000 270 * 271 * This could be calculated using something like: 272 * 273 * prescaler = max(ilog2(period) / 2, 7) - 7; 274 * 275 * but given there are only four allowed results and that ilog2 isn't 276 * cheap on all platforms using a switch statement is more effective. 277 */ 278 switch (period) { 279 case 1 ... 0xffff: 280 prescaler = 0; 281 break; 282 283 case 0x10000 ... 0x3ffff: 284 prescaler = 1; 285 break; 286 287 case 0x40000 ... 0xfffff: 288 prescaler = 2; 289 break; 290 291 case 0x100000 ... 0x3fffff: 292 prescaler = 3; 293 break; 294 295 default: 296 return -EINVAL; 297 } 298 299 period >>= 2 * prescaler; 300 301 if (duty_ns) 302 duty = mul_u64_u64_div_u64(clk_rate, duty_ns, 303 (u64)NSEC_PER_SEC << (2 * prescaler)); 304 else 305 duty = 0; 306 307 dev_dbg(&tpu->pdev->dev, 308 "rate %u, prescaler %u, period %u, duty %u\n", 309 clk_rate, 1 << (2 * prescaler), (u32)period, duty); 310 311 if (tpd->prescaler == prescaler && tpd->period == period) 312 duty_only = true; 313 314 tpd->prescaler = prescaler; 315 tpd->period = period; 316 tpd->duty = duty; 317 318 /* If the channel is disabled we're done. */ 319 if (!enabled) 320 return 0; 321 322 if (duty_only && tpd->timer_on) { 323 /* 324 * If only the duty cycle changed and the timer is already 325 * running, there's no need to reconfigure it completely, Just 326 * modify the duty cycle. 327 */ 328 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); 329 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel, 330 tpd->duty); 331 } else { 332 /* Otherwise perform a full reconfiguration. */ 333 ret = tpu_pwm_timer_start(tpd); 334 if (ret < 0) 335 return ret; 336 } 337 338 if (duty == 0 || duty == period) { 339 /* 340 * To avoid running the timer when not strictly required, handle 341 * 0% and 100% duty cycles as fixed levels and stop the timer. 342 */ 343 tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); 344 tpu_pwm_timer_stop(tpd); 345 } 346 347 return 0; 348 } 349 350 static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, 351 enum pwm_polarity polarity) 352 { 353 struct tpu_device *tpu = to_tpu_device(chip); 354 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 355 356 tpd->polarity = polarity; 357 358 return 0; 359 } 360 361 static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 362 { 363 struct tpu_device *tpu = to_tpu_device(chip); 364 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 365 int ret; 366 367 ret = tpu_pwm_timer_start(tpd); 368 if (ret < 0) 369 return ret; 370 371 /* 372 * To avoid running the timer when not strictly required, handle 0% and 373 * 100% duty cycles as fixed levels and stop the timer. 374 */ 375 if (tpd->duty == 0 || tpd->duty == tpd->period) { 376 tpu_pwm_set_pin(tpd, tpd->duty ? 377 TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); 378 tpu_pwm_timer_stop(tpd); 379 } 380 381 return 0; 382 } 383 384 static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 385 { 386 struct tpu_device *tpu = to_tpu_device(chip); 387 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 388 389 /* The timer must be running to modify the pin output configuration. */ 390 tpu_pwm_timer_start(tpd); 391 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE); 392 tpu_pwm_timer_stop(tpd); 393 } 394 395 static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 396 const struct pwm_state *state) 397 { 398 int err; 399 bool enabled = pwm->state.enabled; 400 401 if (state->polarity != pwm->state.polarity) { 402 if (enabled) { 403 tpu_pwm_disable(chip, pwm); 404 enabled = false; 405 } 406 407 err = tpu_pwm_set_polarity(chip, pwm, state->polarity); 408 if (err) 409 return err; 410 } 411 412 if (!state->enabled) { 413 if (enabled) 414 tpu_pwm_disable(chip, pwm); 415 416 return 0; 417 } 418 419 err = tpu_pwm_config(pwm->chip, pwm, 420 state->duty_cycle, state->period, enabled); 421 if (err) 422 return err; 423 424 if (!enabled) 425 err = tpu_pwm_enable(chip, pwm); 426 427 return err; 428 } 429 430 static const struct pwm_ops tpu_pwm_ops = { 431 .request = tpu_pwm_request, 432 .free = tpu_pwm_free, 433 .apply = tpu_pwm_apply, 434 }; 435 436 /* ----------------------------------------------------------------------------- 437 * Probe and remove 438 */ 439 440 static int tpu_probe(struct platform_device *pdev) 441 { 442 struct tpu_device *tpu; 443 int ret; 444 445 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); 446 if (tpu == NULL) 447 return -ENOMEM; 448 449 spin_lock_init(&tpu->lock); 450 tpu->pdev = pdev; 451 452 /* Map memory, get clock and pin control. */ 453 tpu->base = devm_platform_ioremap_resource(pdev, 0); 454 if (IS_ERR(tpu->base)) 455 return PTR_ERR(tpu->base); 456 457 tpu->clk = devm_clk_get(&pdev->dev, NULL); 458 if (IS_ERR(tpu->clk)) 459 return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n"); 460 461 /* Initialize and register the device. */ 462 platform_set_drvdata(pdev, tpu); 463 464 tpu->chip.dev = &pdev->dev; 465 tpu->chip.ops = &tpu_pwm_ops; 466 tpu->chip.npwm = TPU_CHANNEL_MAX; 467 468 ret = devm_pm_runtime_enable(&pdev->dev); 469 if (ret < 0) 470 return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n"); 471 472 ret = devm_pwmchip_add(&pdev->dev, &tpu->chip); 473 if (ret < 0) 474 return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n"); 475 476 return 0; 477 } 478 479 #ifdef CONFIG_OF 480 static const struct of_device_id tpu_of_table[] = { 481 { .compatible = "renesas,tpu-r8a73a4", }, 482 { .compatible = "renesas,tpu-r8a7740", }, 483 { .compatible = "renesas,tpu-r8a7790", }, 484 { .compatible = "renesas,tpu", }, 485 { }, 486 }; 487 488 MODULE_DEVICE_TABLE(of, tpu_of_table); 489 #endif 490 491 static struct platform_driver tpu_driver = { 492 .probe = tpu_probe, 493 .driver = { 494 .name = "renesas-tpu-pwm", 495 .of_match_table = of_match_ptr(tpu_of_table), 496 } 497 }; 498 499 module_platform_driver(tpu_driver); 500 501 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 502 MODULE_DESCRIPTION("Renesas TPU PWM Driver"); 503 MODULE_LICENSE("GPL v2"); 504 MODULE_ALIAS("platform:renesas-tpu-pwm"); 505