1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT6779 Pin Controller 8 9maintainers: 10 - Andy Teng <andy.teng@mediatek.com> 11 12description: |+ 13 The pin controller node should be the child of a syscon node with the 14 required property: 15 - compatible: "syscon" 16 17properties: 18 compatible: 19 const: mediatek,mt6779-pinctrl 20 21 reg: 22 minItems: 9 23 maxItems: 9 24 25 reg-names: 26 items: 27 - const: "gpio" 28 - const: "iocfg_rm" 29 - const: "iocfg_br" 30 - const: "iocfg_lm" 31 - const: "iocfg_lb" 32 - const: "iocfg_rt" 33 - const: "iocfg_lt" 34 - const: "iocfg_tl" 35 - const: "eint" 36 37 gpio-controller: true 38 39 "#gpio-cells": 40 const: 2 41 description: | 42 Number of cells in GPIO specifier. Since the generic GPIO 43 binding is used, the amount of cells must be specified as 2. See the below 44 mentioned gpio binding representation for description of particular cells. 45 46 gpio-ranges: 47 minItems: 1 48 maxItems: 5 49 description: | 50 GPIO valid number range. 51 52 interrupt-controller: true 53 54 interrupts: 55 maxItems: 1 56 description: | 57 Specifies the summary IRQ. 58 59 "#interrupt-cells": 60 const: 2 61 62allOf: 63 - $ref: "pinctrl.yaml#" 64 65required: 66 - compatible 67 - reg 68 - reg-names 69 - gpio-controller 70 - "#gpio-cells" 71 - gpio-ranges 72 - interrupt-controller 73 - interrupts 74 - "#interrupt-cells" 75 76patternProperties: 77 '-[0-9]*$': 78 type: object 79 additionalProperties: false 80 81 patternProperties: 82 '-pins*$': 83 type: object 84 description: | 85 A pinctrl node should contain at least one subnodes representing the 86 pinctrl groups available on the machine. Each subnode will list the 87 pins it needs, and how they should be configured, with regard to muxer 88 configuration, pullups, drive strength, input enable/disable and input schmitt. 89 $ref: "/schemas/pinctrl/pincfg-node.yaml" 90 91 properties: 92 pinmux: 93 description: 94 integer array, represents gpio pin number and mux setting. 95 Supported pin number and mux varies for different SoCs, and are defined 96 as macros in boot/dts/<soc>-pinfunc.h directly. 97 98 bias-disable: true 99 100 bias-pull-up: true 101 102 bias-pull-down: true 103 104 input-enable: true 105 106 input-disable: true 107 108 output-low: true 109 110 output-high: true 111 112 input-schmitt-enable: true 113 114 input-schmitt-disable: true 115 116 mediatek,pull-up-adv: 117 description: | 118 Pull up setings for 2 pull resistors, R0 and R1. User can 119 configure those special pins. Valid arguments are described as below: 120 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 121 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 122 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 123 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 124 $ref: /schemas/types.yaml#/definitions/uint32 125 enum: [0, 1, 2, 3] 126 127 mediatek,pull-down-adv: 128 description: | 129 Pull down settings for 2 pull resistors, R0 and R1. User can 130 configure those special pins. Valid arguments are described as below: 131 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 132 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 133 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 134 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 135 $ref: /schemas/types.yaml#/definitions/uint32 136 enum: [0, 1, 2, 3] 137 138 required: 139 - pinmux 140 141 additionalProperties: false 142 143additionalProperties: false 144 145examples: 146 - | 147 #include <dt-bindings/interrupt-controller/irq.h> 148 #include <dt-bindings/interrupt-controller/arm-gic.h> 149 #include <dt-bindings/pinctrl/mt6779-pinfunc.h> 150 151 soc { 152 #address-cells = <2>; 153 #size-cells = <2>; 154 155 pio: pinctrl@10005000 { 156 compatible = "mediatek,mt6779-pinctrl"; 157 reg = <0 0x10005000 0 0x1000>, 158 <0 0x11c20000 0 0x1000>, 159 <0 0x11d10000 0 0x1000>, 160 <0 0x11e20000 0 0x1000>, 161 <0 0x11e70000 0 0x1000>, 162 <0 0x11ea0000 0 0x1000>, 163 <0 0x11f20000 0 0x1000>, 164 <0 0x11f30000 0 0x1000>, 165 <0 0x1000b000 0 0x1000>; 166 reg-names = "gpio", "iocfg_rm", 167 "iocfg_br", "iocfg_lm", 168 "iocfg_lb", "iocfg_rt", 169 "iocfg_lt", "iocfg_tl", 170 "eint"; 171 gpio-controller; 172 #gpio-cells = <2>; 173 gpio-ranges = <&pio 0 0 210>; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 177 178 mmc0_pins_default: mmc0-0 { 179 cmd-dat-pins { 180 pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, 181 <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, 182 <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, 183 <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, 184 <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, 185 <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, 186 <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, 187 <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, 188 <PINMUX_GPIO167__FUNC_MSDC0_CMD>; 189 input-enable; 190 mediatek,pull-up-adv = <1>; 191 }; 192 clk-pins { 193 pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; 194 mediatek,pull-down-adv = <2>; 195 }; 196 rst-pins { 197 pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; 198 mediatek,pull-up-adv = <0>; 199 }; 200 }; 201 }; 202 203 mmc0 { 204 pinctrl-0 = <&mmc0_pins_default>; 205 pinctrl-names = "default"; 206 }; 207 }; 208