xref: /linux/arch/arm64/boot/dts/apm/apm-storm.dtsi (revision 561add0da6d3d07c9bccb0832fb6ed5619167d26) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 *
5 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 */
7
8/ {
9	compatible = "apm,xgene-storm";
10	interrupt-parent = <&gic>;
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	cpus {
15		#address-cells = <2>;
16		#size-cells = <0>;
17
18		cpu@0 {
19			device_type = "cpu";
20			compatible = "apm,potenza";
21			reg = <0x0 0x000>;
22			enable-method = "spin-table";
23			cpu-release-addr = <0x1 0x0000fff8>;
24			next-level-cache = <&xgene_L2_0>;
25		};
26		cpu@1 {
27			device_type = "cpu";
28			compatible = "apm,potenza";
29			reg = <0x0 0x001>;
30			enable-method = "spin-table";
31			cpu-release-addr = <0x1 0x0000fff8>;
32			next-level-cache = <&xgene_L2_0>;
33		};
34		cpu@100 {
35			device_type = "cpu";
36			compatible = "apm,potenza";
37			reg = <0x0 0x100>;
38			enable-method = "spin-table";
39			cpu-release-addr = <0x1 0x0000fff8>;
40			next-level-cache = <&xgene_L2_1>;
41		};
42		cpu@101 {
43			device_type = "cpu";
44			compatible = "apm,potenza";
45			reg = <0x0 0x101>;
46			enable-method = "spin-table";
47			cpu-release-addr = <0x1 0x0000fff8>;
48			next-level-cache = <&xgene_L2_1>;
49		};
50		cpu@200 {
51			device_type = "cpu";
52			compatible = "apm,potenza";
53			reg = <0x0 0x200>;
54			enable-method = "spin-table";
55			cpu-release-addr = <0x1 0x0000fff8>;
56			next-level-cache = <&xgene_L2_2>;
57		};
58		cpu@201 {
59			device_type = "cpu";
60			compatible = "apm,potenza";
61			reg = <0x0 0x201>;
62			enable-method = "spin-table";
63			cpu-release-addr = <0x1 0x0000fff8>;
64			next-level-cache = <&xgene_L2_2>;
65		};
66		cpu@300 {
67			device_type = "cpu";
68			compatible = "apm,potenza";
69			reg = <0x0 0x300>;
70			enable-method = "spin-table";
71			cpu-release-addr = <0x1 0x0000fff8>;
72			next-level-cache = <&xgene_L2_3>;
73		};
74		cpu@301 {
75			device_type = "cpu";
76			compatible = "apm,potenza";
77			reg = <0x0 0x301>;
78			enable-method = "spin-table";
79			cpu-release-addr = <0x1 0x0000fff8>;
80			next-level-cache = <&xgene_L2_3>;
81		};
82		xgene_L2_0: l2-cache-0 {
83			compatible = "cache";
84			cache-level = <2>;
85			cache-unified;
86		};
87		xgene_L2_1: l2-cache-1 {
88			compatible = "cache";
89			cache-level = <2>;
90			cache-unified;
91		};
92		xgene_L2_2: l2-cache-2 {
93			compatible = "cache";
94			cache-level = <2>;
95			cache-unified;
96		};
97		xgene_L2_3: l2-cache-3 {
98			compatible = "cache";
99			cache-level = <2>;
100			cache-unified;
101		};
102	};
103
104	gic: interrupt-controller@78010000 {
105		compatible = "arm,cortex-a15-gic";
106		#interrupt-cells = <3>;
107		interrupt-controller;
108		reg = <0x0 0x78010000 0x0 0x1000>,	/* GIC Dist */
109		      <0x0 0x78020000 0x0 0x1000>,	/* GIC CPU */
110		      <0x0 0x78040000 0x0 0x2000>,	/* GIC VCPU Control */
111		      <0x0 0x78060000 0x0 0x2000>;	/* GIC VCPU */
112		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
113	};
114
115	timer {
116		compatible = "arm,armv8-timer";
117		interrupts = <1 0 0xff08>,	/* Secure Phys IRQ */
118			     <1 13 0xff08>,	/* Non-secure Phys IRQ */
119			     <1 14 0xff08>,	/* Virt IRQ */
120			     <1 15 0xff08>;	/* Hyp IRQ */
121		clock-frequency = <50000000>;
122	};
123
124	pmu {
125		compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
126		interrupts = <1 12 0xff04>;
127	};
128
129	soc {
130		compatible = "simple-bus";
131		#address-cells = <2>;
132		#size-cells = <2>;
133		ranges;
134		dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
135
136		clocks {
137			#address-cells = <2>;
138			#size-cells = <2>;
139			ranges;
140			refclk: refclk {
141				compatible = "fixed-clock";
142				#clock-cells = <1>;
143				clock-frequency = <100000000>;
144				clock-output-names = "refclk";
145			};
146
147			pcppll: pcppll@17000100 {
148				compatible = "apm,xgene-pcppll-clock";
149				#clock-cells = <1>;
150				clocks = <&refclk 0>;
151				clock-names = "pcppll";
152				reg = <0x0 0x17000100 0x0 0x1000>;
153				clock-output-names = "pcppll";
154				type = <0>;
155			};
156
157			socpll: socpll@17000120 {
158				compatible = "apm,xgene-socpll-clock";
159				#clock-cells = <1>;
160				clocks = <&refclk 0>;
161				clock-names = "socpll";
162				reg = <0x0 0x17000120 0x0 0x1000>;
163				clock-output-names = "socpll";
164				type = <1>;
165			};
166
167			socplldiv2: socplldiv2  {
168				compatible = "fixed-factor-clock";
169				#clock-cells = <1>;
170				clocks = <&socpll 0>;
171				clock-names = "socplldiv2";
172				clock-mult = <1>;
173				clock-div = <2>;
174				clock-output-names = "socplldiv2";
175			};
176
177			ahbclk: ahbclk@17000000 {
178				compatible = "apm,xgene-device-clock";
179				#clock-cells = <1>;
180				clocks = <&socplldiv2 0>;
181				reg = <0x0 0x17000000 0x0 0x2000>;
182				reg-names = "div-reg";
183				divider-offset = <0x164>;
184				divider-width = <0x5>;
185				divider-shift = <0x0>;
186				clock-output-names = "ahbclk";
187			};
188
189			sdioclk: sdioclk@1f2ac000 {
190				compatible = "apm,xgene-device-clock";
191				#clock-cells = <1>;
192				clocks = <&socplldiv2 0>;
193				reg = <0x0 0x1f2ac000 0x0 0x1000
194					0x0 0x17000000 0x0 0x2000>;
195				reg-names = "csr-reg", "div-reg";
196				csr-offset = <0x0>;
197				csr-mask = <0x2>;
198				enable-offset = <0x8>;
199				enable-mask = <0x2>;
200				divider-offset = <0x178>;
201				divider-width = <0x8>;
202				divider-shift = <0x0>;
203				clock-output-names = "sdioclk";
204			};
205
206			ethclk: ethclk {
207				compatible = "apm,xgene-device-clock";
208				#clock-cells = <1>;
209				clocks = <&socplldiv2 0>;
210				clock-names = "ethclk";
211				reg = <0x0 0x17000000 0x0 0x1000>;
212				reg-names = "div-reg";
213				divider-offset = <0x238>;
214				divider-width = <0x9>;
215				divider-shift = <0x0>;
216				clock-output-names = "ethclk";
217			};
218
219			menetclk: menetclk {
220				compatible = "apm,xgene-device-clock";
221				#clock-cells = <1>;
222				clocks = <&ethclk 0>;
223				reg = <0x0 0x1702c000 0x0 0x1000>;
224				reg-names = "csr-reg";
225				clock-output-names = "menetclk";
226			};
227
228			sge0clk: sge0clk@1f21c000 {
229				compatible = "apm,xgene-device-clock";
230				#clock-cells = <1>;
231				clocks = <&socplldiv2 0>;
232				reg = <0x0 0x1f21c000 0x0 0x1000>;
233				reg-names = "csr-reg";
234				csr-mask = <0xa>;
235				enable-mask = <0xf>;
236				clock-output-names = "sge0clk";
237			};
238
239			xge0clk: xge0clk@1f61c000 {
240				compatible = "apm,xgene-device-clock";
241				#clock-cells = <1>;
242				clocks = <&socplldiv2 0>;
243				reg = <0x0 0x1f61c000 0x0 0x1000>;
244				reg-names = "csr-reg";
245				csr-mask = <0x3>;
246				clock-output-names = "xge0clk";
247			};
248
249			xge1clk: xge1clk@1f62c000 {
250				compatible = "apm,xgene-device-clock";
251				status = "disabled";
252				#clock-cells = <1>;
253				clocks = <&socplldiv2 0>;
254				reg = <0x0 0x1f62c000 0x0 0x1000>;
255				reg-names = "csr-reg";
256				csr-mask = <0x3>;
257				clock-output-names = "xge1clk";
258			};
259
260			sataphy1clk: sataphy1clk@1f21c000 {
261				compatible = "apm,xgene-device-clock";
262				#clock-cells = <1>;
263				clocks = <&socplldiv2 0>;
264				reg = <0x0 0x1f21c000 0x0 0x1000>;
265				reg-names = "csr-reg";
266				clock-output-names = "sataphy1clk";
267				status = "disabled";
268				csr-offset = <0x4>;
269				csr-mask = <0x00>;
270				enable-offset = <0x0>;
271				enable-mask = <0x06>;
272			};
273
274			sataphy2clk: sataphy1clk@1f22c000 {
275				compatible = "apm,xgene-device-clock";
276				#clock-cells = <1>;
277				clocks = <&socplldiv2 0>;
278				reg = <0x0 0x1f22c000 0x0 0x1000>;
279				reg-names = "csr-reg";
280				clock-output-names = "sataphy2clk";
281				status = "okay";
282				csr-offset = <0x4>;
283				csr-mask = <0x3a>;
284				enable-offset = <0x0>;
285				enable-mask = <0x06>;
286			};
287
288			sataphy3clk: sataphy1clk@1f23c000 {
289				compatible = "apm,xgene-device-clock";
290				#clock-cells = <1>;
291				clocks = <&socplldiv2 0>;
292				reg = <0x0 0x1f23c000 0x0 0x1000>;
293				reg-names = "csr-reg";
294				clock-output-names = "sataphy3clk";
295				status = "okay";
296				csr-offset = <0x4>;
297				csr-mask = <0x3a>;
298				enable-offset = <0x0>;
299				enable-mask = <0x06>;
300			};
301
302			sata01clk: sata01clk@1f21c000 {
303				compatible = "apm,xgene-device-clock";
304				#clock-cells = <1>;
305				clocks = <&socplldiv2 0>;
306				reg = <0x0 0x1f21c000 0x0 0x1000>;
307				reg-names = "csr-reg";
308				clock-output-names = "sata01clk";
309				csr-offset = <0x4>;
310				csr-mask = <0x05>;
311				enable-offset = <0x0>;
312				enable-mask = <0x39>;
313			};
314
315			sata23clk: sata23clk@1f22c000 {
316				compatible = "apm,xgene-device-clock";
317				#clock-cells = <1>;
318				clocks = <&socplldiv2 0>;
319				reg = <0x0 0x1f22c000 0x0 0x1000>;
320				reg-names = "csr-reg";
321				clock-output-names = "sata23clk";
322				csr-offset = <0x4>;
323				csr-mask = <0x05>;
324				enable-offset = <0x0>;
325				enable-mask = <0x39>;
326			};
327
328			sata45clk: sata45clk@1f23c000 {
329				compatible = "apm,xgene-device-clock";
330				#clock-cells = <1>;
331				clocks = <&socplldiv2 0>;
332				reg = <0x0 0x1f23c000 0x0 0x1000>;
333				reg-names = "csr-reg";
334				clock-output-names = "sata45clk";
335				csr-offset = <0x4>;
336				csr-mask = <0x05>;
337				enable-offset = <0x0>;
338				enable-mask = <0x39>;
339			};
340
341			rtcclk: rtcclk@17000000 {
342				compatible = "apm,xgene-device-clock";
343				#clock-cells = <1>;
344				clocks = <&socplldiv2 0>;
345				reg = <0x0 0x17000000 0x0 0x2000>;
346				reg-names = "csr-reg";
347				csr-offset = <0xc>;
348				csr-mask = <0x2>;
349				enable-offset = <0x10>;
350				enable-mask = <0x2>;
351				clock-output-names = "rtcclk";
352			};
353
354			rngpkaclk: rngpkaclk@17000000 {
355				compatible = "apm,xgene-device-clock";
356				#clock-cells = <1>;
357				clocks = <&socplldiv2 0>;
358				reg = <0x0 0x17000000 0x0 0x2000>;
359				reg-names = "csr-reg";
360				csr-offset = <0xc>;
361				csr-mask = <0x10>;
362				enable-offset = <0x10>;
363				enable-mask = <0x10>;
364				clock-output-names = "rngpkaclk";
365			};
366
367			pcie0clk: pcie0clk@1f2bc000 {
368				status = "disabled";
369				compatible = "apm,xgene-device-clock";
370				#clock-cells = <1>;
371				clocks = <&socplldiv2 0>;
372				reg = <0x0 0x1f2bc000 0x0 0x1000>;
373				reg-names = "csr-reg";
374				clock-output-names = "pcie0clk";
375			};
376
377			pcie1clk: pcie1clk@1f2cc000 {
378				status = "disabled";
379				compatible = "apm,xgene-device-clock";
380				#clock-cells = <1>;
381				clocks = <&socplldiv2 0>;
382				reg = <0x0 0x1f2cc000 0x0 0x1000>;
383				reg-names = "csr-reg";
384				clock-output-names = "pcie1clk";
385			};
386
387			pcie2clk: pcie2clk@1f2dc000 {
388				status = "disabled";
389				compatible = "apm,xgene-device-clock";
390				#clock-cells = <1>;
391				clocks = <&socplldiv2 0>;
392				reg = <0x0 0x1f2dc000 0x0 0x1000>;
393				reg-names = "csr-reg";
394				clock-output-names = "pcie2clk";
395			};
396
397			pcie3clk: pcie3clk@1f50c000 {
398				status = "disabled";
399				compatible = "apm,xgene-device-clock";
400				#clock-cells = <1>;
401				clocks = <&socplldiv2 0>;
402				reg = <0x0 0x1f50c000 0x0 0x1000>;
403				reg-names = "csr-reg";
404				clock-output-names = "pcie3clk";
405			};
406
407			pcie4clk: pcie4clk@1f51c000 {
408				status = "disabled";
409				compatible = "apm,xgene-device-clock";
410				#clock-cells = <1>;
411				clocks = <&socplldiv2 0>;
412				reg = <0x0 0x1f51c000 0x0 0x1000>;
413				reg-names = "csr-reg";
414				clock-output-names = "pcie4clk";
415			};
416
417			dmaclk: dmaclk@1f27c000 {
418				compatible = "apm,xgene-device-clock";
419				#clock-cells = <1>;
420				clocks = <&socplldiv2 0>;
421				reg = <0x0 0x1f27c000 0x0 0x1000>;
422				reg-names = "csr-reg";
423				clock-output-names = "dmaclk";
424			};
425		};
426
427		msi: msi@79000000 {
428			compatible = "apm,xgene1-msi";
429			msi-controller;
430			reg = <0x00 0x79000000 0x0 0x900000>;
431			interrupts = <  0x0 0x10 0x4
432					0x0 0x11 0x4
433					0x0 0x12 0x4
434					0x0 0x13 0x4
435					0x0 0x14 0x4
436					0x0 0x15 0x4
437					0x0 0x16 0x4
438					0x0 0x17 0x4
439					0x0 0x18 0x4
440					0x0 0x19 0x4
441					0x0 0x1a 0x4
442					0x0 0x1b 0x4
443					0x0 0x1c 0x4
444					0x0 0x1d 0x4
445					0x0 0x1e 0x4
446					0x0 0x1f 0x4>;
447		};
448
449		scu: system-clk-controller@17000000 {
450			compatible = "apm,xgene-scu","syscon";
451			reg = <0x0 0x17000000 0x0 0x400>;
452		};
453
454		reboot: reboot@17000014 {
455			compatible = "syscon-reboot";
456			regmap = <&scu>;
457			offset = <0x14>;
458			mask = <0x1>;
459		};
460
461		csw: csw@7e200000 {
462			compatible = "apm,xgene-csw", "syscon";
463			reg = <0x0 0x7e200000 0x0 0x1000>;
464		};
465
466		mcba: mcba@7e700000 {
467			compatible = "apm,xgene-mcb", "syscon";
468			reg = <0x0 0x7e700000 0x0 0x1000>;
469		};
470
471		mcbb: mcbb@7e720000 {
472			compatible = "apm,xgene-mcb", "syscon";
473			reg = <0x0 0x7e720000 0x0 0x1000>;
474		};
475
476		efuse: efuse@1054a000 {
477			compatible = "apm,xgene-efuse", "syscon";
478			reg = <0x0 0x1054a000 0x0 0x20>;
479		};
480
481		rb: rb@7e000000 {
482			compatible = "apm,xgene-rb", "syscon";
483			reg = <0x0 0x7e000000 0x0 0x10>;
484		};
485
486		edac@78800000 {
487			compatible = "apm,xgene-edac";
488			#address-cells = <2>;
489			#size-cells = <2>;
490			ranges;
491			regmap-csw = <&csw>;
492			regmap-mcba = <&mcba>;
493			regmap-mcbb = <&mcbb>;
494			regmap-efuse = <&efuse>;
495			regmap-rb = <&rb>;
496			reg = <0x0 0x78800000 0x0 0x100>;
497			interrupts = <0x0 0x20 0x4>,
498				     <0x0 0x21 0x4>,
499				     <0x0 0x27 0x4>;
500
501			edacmc@7e800000 {
502				compatible = "apm,xgene-edac-mc";
503				reg = <0x0 0x7e800000 0x0 0x1000>;
504				memory-controller = <0>;
505			};
506
507			edacmc@7e840000 {
508				compatible = "apm,xgene-edac-mc";
509				reg = <0x0 0x7e840000 0x0 0x1000>;
510				memory-controller = <1>;
511			};
512
513			edacmc@7e880000 {
514				compatible = "apm,xgene-edac-mc";
515				reg = <0x0 0x7e880000 0x0 0x1000>;
516				memory-controller = <2>;
517			};
518
519			edacmc@7e8c0000 {
520				compatible = "apm,xgene-edac-mc";
521				reg = <0x0 0x7e8c0000 0x0 0x1000>;
522				memory-controller = <3>;
523			};
524
525			edacpmd@7c000000 {
526				compatible = "apm,xgene-edac-pmd";
527				reg = <0x0 0x7c000000 0x0 0x200000>;
528				pmd-controller = <0>;
529			};
530
531			edacpmd@7c200000 {
532				compatible = "apm,xgene-edac-pmd";
533				reg = <0x0 0x7c200000 0x0 0x200000>;
534				pmd-controller = <1>;
535			};
536
537			edacpmd@7c400000 {
538				compatible = "apm,xgene-edac-pmd";
539				reg = <0x0 0x7c400000 0x0 0x200000>;
540				pmd-controller = <2>;
541			};
542
543			edacpmd@7c600000 {
544				compatible = "apm,xgene-edac-pmd";
545				reg = <0x0 0x7c600000 0x0 0x200000>;
546				pmd-controller = <3>;
547			};
548
549			edacl3@7e600000 {
550				compatible = "apm,xgene-edac-l3";
551				reg = <0x0 0x7e600000 0x0 0x1000>;
552			};
553
554			edacsoc@7e930000 {
555				compatible = "apm,xgene-edac-soc-v1";
556				reg = <0x0 0x7e930000 0x0 0x1000>;
557			};
558		};
559
560		pmu: pmu@78810000 {
561			compatible = "apm,xgene-pmu-v2";
562			#address-cells = <2>;
563			#size-cells = <2>;
564			ranges;
565			regmap-csw = <&csw>;
566			regmap-mcba = <&mcba>;
567			regmap-mcbb = <&mcbb>;
568			reg = <0x0 0x78810000 0x0 0x1000>;
569			interrupts = <0x0 0x22 0x4>;
570
571			pmul3c@7e610000 {
572				compatible = "apm,xgene-pmu-l3c";
573				reg = <0x0 0x7e610000 0x0 0x1000>;
574			};
575
576			pmuiob@7e940000 {
577				compatible = "apm,xgene-pmu-iob";
578				reg = <0x0 0x7e940000 0x0 0x1000>;
579			};
580
581			pmucmcb@7e710000 {
582				compatible = "apm,xgene-pmu-mcb";
583				reg = <0x0 0x7e710000 0x0 0x1000>;
584				enable-bit-index = <0>;
585			};
586
587			pmucmcb@7e730000 {
588				compatible = "apm,xgene-pmu-mcb";
589				reg = <0x0 0x7e730000 0x0 0x1000>;
590				enable-bit-index = <1>;
591			};
592
593			pmucmc@7e810000 {
594				compatible = "apm,xgene-pmu-mc";
595				reg = <0x0 0x7e810000 0x0 0x1000>;
596				enable-bit-index = <0>;
597			};
598
599			pmucmc@7e850000 {
600				compatible = "apm,xgene-pmu-mc";
601				reg = <0x0 0x7e850000 0x0 0x1000>;
602				enable-bit-index = <1>;
603			};
604
605			pmucmc@7e890000 {
606				compatible = "apm,xgene-pmu-mc";
607				reg = <0x0 0x7e890000 0x0 0x1000>;
608				enable-bit-index = <2>;
609			};
610
611			pmucmc@7e8d0000 {
612				compatible = "apm,xgene-pmu-mc";
613				reg = <0x0 0x7e8d0000 0x0 0x1000>;
614				enable-bit-index = <3>;
615			};
616		};
617
618		pcie0: pcie@1f2b0000 {
619			status = "disabled";
620			device_type = "pci";
621			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
622			#interrupt-cells = <1>;
623			#size-cells = <2>;
624			#address-cells = <3>;
625			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
626				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
627			reg-names = "csr", "cfg";
628			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
629				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
630				  0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
631			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
632				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
633			bus-range = <0x00 0xff>;
634			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
635			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
636					 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
637					 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
638					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
639			dma-coherent;
640			clocks = <&pcie0clk 0>;
641			msi-parent = <&msi>;
642		};
643
644		pcie1: pcie@1f2c0000 {
645			status = "disabled";
646			device_type = "pci";
647			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
648			#interrupt-cells = <1>;
649			#size-cells = <2>;
650			#address-cells = <3>;
651			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
652				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
653			reg-names = "csr", "cfg";
654			ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
655				  0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
656				  0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
657			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
658				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
659			bus-range = <0x00 0xff>;
660			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
661			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
662					 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
663					 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
664					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
665			dma-coherent;
666			clocks = <&pcie1clk 0>;
667			msi-parent = <&msi>;
668		};
669
670		pcie2: pcie@1f2d0000 {
671			status = "disabled";
672			device_type = "pci";
673			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
674			#interrupt-cells = <1>;
675			#size-cells = <2>;
676			#address-cells = <3>;
677			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
678				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
679			reg-names = "csr", "cfg";
680			ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
681				  0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
682				  0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
683			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
684				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
685			bus-range = <0x00 0xff>;
686			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
687			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
688					 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
689					 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
690					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
691			dma-coherent;
692			clocks = <&pcie2clk 0>;
693			msi-parent = <&msi>;
694		};
695
696		pcie3: pcie@1f500000 {
697			status = "disabled";
698			device_type = "pci";
699			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
700			#interrupt-cells = <1>;
701			#size-cells = <2>;
702			#address-cells = <3>;
703			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
704				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
705			reg-names = "csr", "cfg";
706			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
707				  0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
708				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
709			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
710				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
711			bus-range = <0x00 0xff>;
712			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
713			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
714					 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
715					 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
716					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
717			dma-coherent;
718			clocks = <&pcie3clk 0>;
719			msi-parent = <&msi>;
720		};
721
722		pcie4: pcie@1f510000 {
723			status = "disabled";
724			device_type = "pci";
725			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
726			#interrupt-cells = <1>;
727			#size-cells = <2>;
728			#address-cells = <3>;
729			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
730				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
731			reg-names = "csr", "cfg";
732			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
733				  0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
734				  0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
735			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
736				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
737			bus-range = <0x00 0xff>;
738			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
739			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
740					 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
741					 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
742					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
743			dma-coherent;
744			clocks = <&pcie4clk 0>;
745			msi-parent = <&msi>;
746		};
747
748		mailbox: mailbox@10540000 {
749			compatible = "apm,xgene-slimpro-mbox";
750			reg = <0x0 0x10540000 0x0 0xa000>;
751			#mbox-cells = <1>;
752			interrupts =    <0x0 0x0 0x4>,
753					<0x0 0x1 0x4>,
754					<0x0 0x2 0x4>,
755					<0x0 0x3 0x4>,
756					<0x0 0x4 0x4>,
757					<0x0 0x5 0x4>,
758					<0x0 0x6 0x4>,
759					<0x0 0x7 0x4>;
760		};
761
762		i2cslimpro {
763			compatible = "apm,xgene-slimpro-i2c";
764			mboxes = <&mailbox 0>;
765		};
766
767		hwmonslimpro {
768			compatible = "apm,xgene-slimpro-hwmon";
769			mboxes = <&mailbox 7>;
770		};
771
772		serial0: serial@1c020000 {
773			status = "disabled";
774			compatible = "ns16550a";
775			reg = <0 0x1c020000 0x0 0x1000>;
776			reg-shift = <2>;
777			clock-frequency = <10000000>; /* Updated by bootloader */
778			interrupt-parent = <&gic>;
779			interrupts = <0x0 0x4c 0x4>;
780		};
781
782		serial1: serial@1c021000 {
783			status = "disabled";
784			compatible = "ns16550a";
785			reg = <0 0x1c021000 0x0 0x1000>;
786			reg-shift = <2>;
787			clock-frequency = <10000000>; /* Updated by bootloader */
788			interrupt-parent = <&gic>;
789			interrupts = <0x0 0x4d 0x4>;
790		};
791
792		serial2: serial@1c022000 {
793			status = "disabled";
794			compatible = "ns16550a";
795			reg = <0 0x1c022000 0x0 0x1000>;
796			reg-shift = <2>;
797			clock-frequency = <10000000>; /* Updated by bootloader */
798			interrupt-parent = <&gic>;
799			interrupts = <0x0 0x4e 0x4>;
800		};
801
802		serial3: serial@1c023000 {
803			status = "disabled";
804			compatible = "ns16550a";
805			reg = <0 0x1c023000 0x0 0x1000>;
806			reg-shift = <2>;
807			clock-frequency = <10000000>; /* Updated by bootloader */
808			interrupt-parent = <&gic>;
809			interrupts = <0x0 0x4f 0x4>;
810		};
811
812		mmc0: mmc@1c000000 {
813			compatible = "arasan,sdhci-4.9a";
814			reg = <0x0 0x1c000000 0x0 0x100>;
815			interrupts = <0x0 0x49 0x4>;
816			dma-coherent;
817			no-1-8-v;
818			clock-names = "clk_xin", "clk_ahb";
819			clocks = <&sdioclk 0>, <&ahbclk 0>;
820		};
821
822		gfcgpio: gpio0@1701c000 {
823			compatible = "apm,xgene-gpio";
824			reg = <0x0 0x1701c000 0x0 0x40>;
825			gpio-controller;
826			#gpio-cells = <2>;
827		};
828
829		dwgpio: gpio@1c024000 {
830			compatible = "snps,dw-apb-gpio";
831			reg = <0x0 0x1c024000 0x0 0x1000>;
832			#address-cells = <1>;
833			#size-cells = <0>;
834
835			porta: gpio-controller@0 {
836				compatible = "snps,dw-apb-gpio-port";
837				gpio-controller;
838				#gpio-cells = <2>;
839				snps,nr-gpios = <32>;
840				reg = <0>;
841			};
842		};
843
844		i2c0: i2c@10512000 {
845			status = "disabled";
846			#address-cells = <1>;
847			#size-cells = <0>;
848			compatible = "snps,designware-i2c";
849			reg = <0x0 0x10512000 0x0 0x1000>;
850			interrupts = <0 0x44 0x4>;
851			#clock-cells = <1>;
852			clocks = <&ahbclk 0>;
853			bus_num = <0>;
854		};
855
856		phy1: phy@1f21a000 {
857			compatible = "apm,xgene-phy";
858			reg = <0x0 0x1f21a000 0x0 0x100>;
859			#phy-cells = <1>;
860			clocks = <&sataphy1clk 0>;
861			status = "disabled";
862			apm,tx-boost-gain = <30 30 30 30 30 30>;
863			apm,tx-eye-tuning = <2 10 10 2 10 10>;
864		};
865
866		phy2: phy@1f22a000 {
867			compatible = "apm,xgene-phy";
868			reg = <0x0 0x1f22a000 0x0 0x100>;
869			#phy-cells = <1>;
870			clocks = <&sataphy2clk 0>;
871			status = "okay";
872			apm,tx-boost-gain = <30 30 30 30 30 30>;
873			apm,tx-eye-tuning = <1 10 10 2 10 10>;
874		};
875
876		phy3: phy@1f23a000 {
877			compatible = "apm,xgene-phy";
878			reg = <0x0 0x1f23a000 0x0 0x100>;
879			#phy-cells = <1>;
880			clocks = <&sataphy3clk 0>;
881			status = "okay";
882			apm,tx-boost-gain = <31 31 31 31 31 31>;
883			apm,tx-eye-tuning = <2 10 10 2 10 10>;
884		};
885
886		sata1: sata@1a000000 {
887			compatible = "apm,xgene-ahci";
888			reg = <0x0 0x1a000000 0x0 0x1000>,
889			      <0x0 0x1f210000 0x0 0x1000>,
890			      <0x0 0x1f21d000 0x0 0x1000>,
891			      <0x0 0x1f21e000 0x0 0x1000>,
892			      <0x0 0x1f217000 0x0 0x1000>;
893			interrupts = <0x0 0x86 0x4>;
894			dma-coherent;
895			status = "disabled";
896			clocks = <&sata01clk 0>;
897			phys = <&phy1 0>;
898			phy-names = "sata-phy";
899		};
900
901		sata2: sata@1a400000 {
902			compatible = "apm,xgene-ahci";
903			reg = <0x0 0x1a400000 0x0 0x1000>,
904			      <0x0 0x1f220000 0x0 0x1000>,
905			      <0x0 0x1f22d000 0x0 0x1000>,
906			      <0x0 0x1f22e000 0x0 0x1000>,
907			      <0x0 0x1f227000 0x0 0x1000>;
908			interrupts = <0x0 0x87 0x4>;
909			dma-coherent;
910			status = "okay";
911			clocks = <&sata23clk 0>;
912			phys = <&phy2 0>;
913			phy-names = "sata-phy";
914		};
915
916		sata3: sata@1a800000 {
917			compatible = "apm,xgene-ahci";
918			reg = <0x0 0x1a800000 0x0 0x1000>,
919			      <0x0 0x1f230000 0x0 0x1000>,
920			      <0x0 0x1f23d000 0x0 0x1000>,
921			      <0x0 0x1f23e000 0x0 0x1000>;
922			interrupts = <0x0 0x88 0x4>;
923			dma-coherent;
924			status = "okay";
925			clocks = <&sata45clk 0>;
926			phys = <&phy3 0>;
927			phy-names = "sata-phy";
928		};
929
930		/* Node-name might need to be coded as dwusb for backward compatibility */
931		usb0: usb@19000000 {
932			status = "disabled";
933			compatible = "snps,dwc3";
934			reg = <0x0 0x19000000 0x0 0x100000>;
935			interrupts = <0x0 0x89 0x4>;
936			dma-coherent;
937			dr_mode = "host";
938		};
939
940		usb1: usb@19800000 {
941			status = "disabled";
942			compatible = "snps,dwc3";
943			reg = <0x0 0x19800000 0x0 0x100000>;
944			interrupts = <0x0 0x8a 0x4>;
945			dma-coherent;
946			dr_mode = "host";
947		};
948
949		sbgpio: gpio@17001000{
950			compatible = "apm,xgene-gpio-sb";
951			reg = <0x0 0x17001000 0x0 0x400>;
952			#gpio-cells = <2>;
953			gpio-controller;
954			interrupts = 	<0x0 0x28 0x1>,
955					<0x0 0x29 0x1>,
956					<0x0 0x2a 0x1>,
957					<0x0 0x2b 0x1>,
958					<0x0 0x2c 0x1>,
959					<0x0 0x2d 0x1>;
960			interrupt-parent = <&gic>;
961			#interrupt-cells = <2>;
962			interrupt-controller;
963		};
964
965		rtc: rtc@10510000 {
966			compatible = "apm,xgene-rtc";
967			reg = <0x0 0x10510000 0x0 0x400>;
968			interrupts = <0x0 0x46 0x4>;
969			#clock-cells = <1>;
970			clocks = <&rtcclk 0>;
971		};
972
973		mdio: mdio@17020000 {
974			compatible = "apm,xgene-mdio-rgmii";
975			#address-cells = <1>;
976			#size-cells = <0>;
977			reg = <0x0 0x17020000 0x0 0xd100>;
978			clocks = <&menetclk 0>;
979		};
980
981		menet: ethernet@17020000 {
982			compatible = "apm,xgene-enet";
983			status = "disabled";
984			reg = <0x0 0x17020000 0x0 0xd100>,
985			      <0x0 0x17030000 0x0 0xc300>,
986			      <0x0 0x10000000 0x0 0x200>;
987			reg-names = "enet_csr", "ring_csr", "ring_cmd";
988			interrupts = <0x0 0x3c 0x4>;
989			dma-coherent;
990			clocks = <&menetclk 0>;
991			/* mac address will be overwritten by the bootloader */
992			local-mac-address = [00 00 00 00 00 00];
993			phy-connection-type = "rgmii";
994			phy-handle = <&menetphy>,<&menet0phy>;
995			mdio {
996				compatible = "apm,xgene-mdio";
997				#address-cells = <1>;
998				#size-cells = <0>;
999				menetphy: menetphy@3 {
1000					compatible = "ethernet-phy-id001c.c915";
1001					reg = <0x3>;
1002				};
1003
1004			};
1005		};
1006
1007		sgenet0: ethernet@1f210000 {
1008			compatible = "apm,xgene1-sgenet";
1009			status = "disabled";
1010			reg = <0x0 0x1f210000 0x0 0xd100>,
1011			      <0x0 0x1f200000 0x0 0xc300>,
1012			      <0x0 0x1b000000 0x0 0x200>;
1013			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1014			interrupts = <0x0 0xa0 0x4>,
1015				     <0x0 0xa1 0x4>;
1016			dma-coherent;
1017			clocks = <&sge0clk 0>;
1018			local-mac-address = [00 00 00 00 00 00];
1019			phy-connection-type = "sgmii";
1020			phy-handle = <&sgenet0phy>;
1021		};
1022
1023		sgenet1: ethernet@1f210030 {
1024			compatible = "apm,xgene1-sgenet";
1025			status = "disabled";
1026			reg = <0x0 0x1f210030 0x0 0xd100>,
1027			      <0x0 0x1f200000 0x0 0xc300>,
1028			      <0x0 0x1b000000 0x0 0x8000>;
1029			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1030			interrupts = <0x0 0xac 0x4>,
1031				     <0x0 0xad 0x4>;
1032			port-id = <1>;
1033			dma-coherent;
1034			local-mac-address = [00 00 00 00 00 00];
1035			phy-connection-type = "sgmii";
1036			phy-handle = <&sgenet1phy>;
1037		};
1038
1039		xgenet: ethernet@1f610000 {
1040			compatible = "apm,xgene1-xgenet";
1041			status = "disabled";
1042			reg = <0x0 0x1f610000 0x0 0xd100>,
1043			      <0x0 0x1f600000 0x0 0xc300>,
1044			      <0x0 0x18000000 0x0 0x200>;
1045			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1046			interrupts = <0x0 0x60 0x4>,
1047				     <0x0 0x61 0x4>,
1048				     <0x0 0x62 0x4>,
1049				     <0x0 0x63 0x4>,
1050				     <0x0 0x64 0x4>,
1051				     <0x0 0x65 0x4>,
1052				     <0x0 0x66 0x4>,
1053				     <0x0 0x67 0x4>;
1054			channel = <0>;
1055			dma-coherent;
1056			clocks = <&xge0clk 0>;
1057			/* mac address will be overwritten by the bootloader */
1058			local-mac-address = [00 00 00 00 00 00];
1059			phy-connection-type = "xgmii";
1060		};
1061
1062		xgenet1: ethernet@1f620000 {
1063			compatible = "apm,xgene1-xgenet";
1064			status = "disabled";
1065			reg = <0x0 0x1f620000 0x0 0xd100>,
1066			      <0x0 0x1f600000 0x0 0xc300>,
1067			      <0x0 0x18000000 0x0 0x8000>;
1068			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1069			interrupts = <0x0 0x6c 0x4>,
1070				     <0x0 0x6d 0x4>;
1071			port-id = <1>;
1072			dma-coherent;
1073			clocks = <&xge1clk 0>;
1074			/* mac address will be overwritten by the bootloader */
1075			local-mac-address = [00 00 00 00 00 00];
1076			phy-connection-type = "xgmii";
1077		};
1078
1079		rng: rng@10520000 {
1080			compatible = "apm,xgene-rng";
1081			reg = <0x0 0x10520000 0x0 0x100>;
1082			interrupts = <0x0 0x41 0x4>;
1083			clocks = <&rngpkaclk 0>;
1084		};
1085
1086		dma: dma@1f270000 {
1087			compatible = "apm,xgene-storm-dma";
1088			device_type = "dma";
1089			reg = <0x0 0x1f270000 0x0 0x10000>,
1090			      <0x0 0x1f200000 0x0 0x10000>,
1091			      <0x0 0x1b000000 0x0 0x400000>,
1092			      <0x0 0x1054a000 0x0 0x100>;
1093			interrupts = <0x0 0x82 0x4>,
1094				     <0x0 0xb8 0x4>,
1095				     <0x0 0xb9 0x4>,
1096				     <0x0 0xba 0x4>,
1097				     <0x0 0xbb 0x4>;
1098			dma-coherent;
1099			clocks = <&dmaclk 0>;
1100		};
1101	};
1102};
1103