xref: /linux/drivers/gpu/drm/i915/display/intel_cx0_phy.h (revision 6c7353836a91b1479e6b81791cdc163fb04b4834)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef __INTEL_CX0_PHY_H__
7 #define __INTEL_CX0_PHY_H__
8 
9 #include <linux/types.h>
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 
13 enum icl_port_dpll_id;
14 enum phy;
15 struct drm_i915_private;
16 struct intel_atomic_state;
17 struct intel_c10pll_state;
18 struct intel_c20pll_state;
19 struct intel_cx0pll_state;
20 struct intel_crtc;
21 struct intel_crtc_state;
22 struct intel_encoder;
23 struct intel_hdmi;
24 
25 bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
26 void intel_mtl_pll_enable(struct intel_encoder *encoder,
27 			  const struct intel_crtc_state *crtc_state);
28 void intel_mtl_pll_disable(struct intel_encoder *encoder);
29 enum icl_port_dpll_id
30 intel_mtl_port_pll_type(struct intel_encoder *encoder,
31 			const struct intel_crtc_state *crtc_state);
32 
33 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
34 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
35 				   struct intel_cx0pll_state *pll_state);
36 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
37 				 const struct intel_cx0pll_state *pll_state);
38 
39 void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
40 				const struct intel_c10pll_state *hw_state);
41 void intel_cx0pll_state_verify(struct intel_atomic_state *state,
42 			       struct intel_crtc *crtc);
43 void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
44 				const struct intel_c20pll_state *hw_state);
45 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
46 				     const struct intel_crtc_state *crtc_state);
47 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
48 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
49 
50 #endif /* __INTEL_CX0_PHY_H__ */
51