1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #ifndef __IVPU_DRV_H__ 7 #define __IVPU_DRV_H__ 8 9 #include <drm/drm_device.h> 10 #include <drm/drm_drv.h> 11 #include <drm/drm_managed.h> 12 #include <drm/drm_mm.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/pci.h> 16 #include <linux/xarray.h> 17 #include <uapi/drm/ivpu_accel.h> 18 19 #include "ivpu_mmu_context.h" 20 #include "ivpu_ipc.h" 21 22 #define DRIVER_NAME "intel_vpu" 23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)" 24 #define DRIVER_DATE "20230117" 25 26 #define PCI_DEVICE_ID_MTL 0x7d1d 27 #define PCI_DEVICE_ID_ARL 0xad1d 28 #define PCI_DEVICE_ID_LNL 0x643e 29 30 #define IVPU_HW_37XX 37 31 #define IVPU_HW_40XX 40 32 33 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 34 /* SSID 1 is used by the VPU to represent reserved context */ 35 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1 36 #define IVPU_USER_CONTEXT_MIN_SSID 2 37 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63) 38 39 #define IVPU_NUM_ENGINES 2 40 41 #define IVPU_PLATFORM_SILICON 0 42 #define IVPU_PLATFORM_SIMICS 2 43 #define IVPU_PLATFORM_FPGA 3 44 #define IVPU_PLATFORM_INVALID 8 45 46 #define IVPU_DBG_REG BIT(0) 47 #define IVPU_DBG_IRQ BIT(1) 48 #define IVPU_DBG_MMU BIT(2) 49 #define IVPU_DBG_FILE BIT(3) 50 #define IVPU_DBG_MISC BIT(4) 51 #define IVPU_DBG_FW_BOOT BIT(5) 52 #define IVPU_DBG_PM BIT(6) 53 #define IVPU_DBG_IPC BIT(7) 54 #define IVPU_DBG_BO BIT(8) 55 #define IVPU_DBG_JOB BIT(9) 56 #define IVPU_DBG_JSM BIT(10) 57 #define IVPU_DBG_KREF BIT(11) 58 #define IVPU_DBG_RPM BIT(12) 59 60 #define ivpu_err(vdev, fmt, ...) \ 61 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 62 63 #define ivpu_err_ratelimited(vdev, fmt, ...) \ 64 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 65 66 #define ivpu_warn(vdev, fmt, ...) \ 67 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 68 69 #define ivpu_warn_ratelimited(vdev, fmt, ...) \ 70 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 71 72 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) 73 74 #define ivpu_dbg(vdev, type, fmt, args...) do { \ 75 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \ 76 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \ 77 } while (0) 78 79 #define IVPU_WA(wa_name) (vdev->wa.wa_name) 80 81 #define IVPU_PRINT_WA(wa_name) do { \ 82 if (IVPU_WA(wa_name)) \ 83 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \ 84 } while (0) 85 86 struct ivpu_wa_table { 87 bool punit_disabled; 88 bool clear_runtime_mem; 89 bool d3hot_after_power_off; 90 bool interrupt_clear_with_0; 91 bool disable_clock_relinquish; 92 bool disable_d0i3_msg; 93 }; 94 95 struct ivpu_hw_info; 96 struct ivpu_mmu_info; 97 struct ivpu_fw_info; 98 struct ivpu_ipc_info; 99 struct ivpu_pm_info; 100 101 struct ivpu_device { 102 struct drm_device drm; 103 void __iomem *regb; 104 void __iomem *regv; 105 u32 platform; 106 u32 irq; 107 108 struct ivpu_wa_table wa; 109 struct ivpu_hw_info *hw; 110 struct ivpu_mmu_info *mmu; 111 struct ivpu_fw_info *fw; 112 struct ivpu_ipc_info *ipc; 113 struct ivpu_pm_info *pm; 114 115 struct ivpu_mmu_context gctx; 116 struct ivpu_mmu_context rctx; 117 struct xarray context_xa; 118 struct xa_limit context_xa_limit; 119 120 struct mutex bo_list_lock; /* Protects bo_list */ 121 struct list_head bo_list; 122 123 struct xarray submitted_jobs_xa; 124 struct ivpu_ipc_consumer job_done_consumer; 125 126 atomic64_t unique_id_counter; 127 128 struct { 129 int boot; 130 int jsm; 131 int tdr; 132 int reschedule_suspend; 133 int autosuspend; 134 int d0i3_entry_msg; 135 } timeout; 136 }; 137 138 /* 139 * file_priv has its own refcount (ref) that allows user space to close the fd 140 * without blocking even if VPU is still processing some jobs. 141 */ 142 struct ivpu_file_priv { 143 struct kref ref; 144 struct ivpu_device *vdev; 145 struct mutex lock; /* Protects cmdq */ 146 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES]; 147 struct ivpu_mmu_context ctx; 148 u32 priority; 149 bool has_mmu_faults; 150 }; 151 152 extern int ivpu_dbg_mask; 153 extern u8 ivpu_pll_min_ratio; 154 extern u8 ivpu_pll_max_ratio; 155 extern bool ivpu_disable_mmu_cont_pages; 156 157 #define IVPU_TEST_MODE_FW_TEST BIT(0) 158 #define IVPU_TEST_MODE_NULL_HW BIT(1) 159 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) 160 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) 161 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) 162 extern int ivpu_test_mode; 163 164 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); 165 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id); 166 void ivpu_file_priv_put(struct ivpu_file_priv **link); 167 168 int ivpu_boot(struct ivpu_device *vdev); 169 int ivpu_shutdown(struct ivpu_device *vdev); 170 void ivpu_prepare_for_reset(struct ivpu_device *vdev); 171 172 static inline u8 ivpu_revision(struct ivpu_device *vdev) 173 { 174 return to_pci_dev(vdev->drm.dev)->revision; 175 } 176 177 static inline u16 ivpu_device_id(struct ivpu_device *vdev) 178 { 179 return to_pci_dev(vdev->drm.dev)->device; 180 } 181 182 static inline int ivpu_hw_gen(struct ivpu_device *vdev) 183 { 184 switch (ivpu_device_id(vdev)) { 185 case PCI_DEVICE_ID_MTL: 186 case PCI_DEVICE_ID_ARL: 187 return IVPU_HW_37XX; 188 case PCI_DEVICE_ID_LNL: 189 return IVPU_HW_40XX; 190 default: 191 ivpu_err(vdev, "Unknown VPU device\n"); 192 return 0; 193 } 194 } 195 196 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) 197 { 198 return container_of(dev, struct ivpu_device, drm); 199 } 200 201 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) 202 { 203 struct xa_limit ctx_limit = vdev->context_xa_limit; 204 205 return (ctx_limit.max - ctx_limit.min + 1); 206 } 207 208 static inline u32 ivpu_get_platform(struct ivpu_device *vdev) 209 { 210 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID); 211 return vdev->platform; 212 } 213 214 static inline bool ivpu_is_silicon(struct ivpu_device *vdev) 215 { 216 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON; 217 } 218 219 static inline bool ivpu_is_simics(struct ivpu_device *vdev) 220 { 221 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS; 222 } 223 224 static inline bool ivpu_is_fpga(struct ivpu_device *vdev) 225 { 226 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA; 227 } 228 229 #endif /* __IVPU_DRV_H__ */ 230