1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spinlock.h> 21 22 #include <video/mipi_display.h> 23 24 #include <drm/display/drm_dsc_helper.h> 25 #include <drm/drm_of.h> 26 27 #include "dsi.h" 28 #include "dsi.xml.h" 29 #include "sfpb.xml.h" 30 #include "dsi_cfg.h" 31 #include "msm_kms.h" 32 #include "msm_gem.h" 33 #include "phy/dsi_phy.h" 34 35 #define DSI_RESET_TOGGLE_DELAY_MS 20 36 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40 { 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = msm_readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86 } 87 88 #define DSI_ERR_STATE_ACK 0x0000 89 #define DSI_ERR_STATE_TIMEOUT 0x0001 90 #define DSI_ERR_STATE_DLN0_PHY 0x0002 91 #define DSI_ERR_STATE_FIFO 0x0004 92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96 #define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102 struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_clk_src; 121 struct clk *pixel_clk_src; 122 struct clk *byte_intf_clk; 123 124 unsigned long byte_clk_rate; 125 unsigned long byte_intf_clk_rate; 126 unsigned long pixel_clk_rate; 127 unsigned long esc_clk_rate; 128 129 /* DSI v2 specific clocks */ 130 struct clk *src_clk; 131 struct clk *esc_clk_src; 132 struct clk *dsi_clk_src; 133 134 unsigned long src_clk_rate; 135 136 struct gpio_desc *disp_en_gpio; 137 struct gpio_desc *te_gpio; 138 139 const struct msm_dsi_cfg_handler *cfg_hnd; 140 141 struct completion dma_comp; 142 struct completion video_comp; 143 struct mutex dev_mutex; 144 struct mutex cmd_mutex; 145 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 146 147 u32 err_work_state; 148 struct work_struct err_work; 149 struct workqueue_struct *workqueue; 150 151 /* DSI 6G TX buffer*/ 152 struct drm_gem_object *tx_gem_obj; 153 154 /* DSI v2 TX buffer */ 155 void *tx_buf; 156 dma_addr_t tx_buf_paddr; 157 158 int tx_size; 159 160 u8 *rx_buf; 161 162 struct regmap *sfpb; 163 164 struct drm_display_mode *mode; 165 struct drm_dsc_config *dsc; 166 167 /* connected device info */ 168 unsigned int channel; 169 unsigned int lanes; 170 enum mipi_dsi_pixel_format format; 171 unsigned long mode_flags; 172 173 /* lane data parsed via DT */ 174 int dlane_swap; 175 int num_data_lanes; 176 177 /* from phy DT */ 178 bool cphy_mode; 179 180 u32 dma_cmd_ctrl_restore; 181 182 bool registered; 183 bool power_on; 184 bool enabled; 185 int irq; 186 }; 187 188 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 189 { 190 switch (fmt) { 191 case MIPI_DSI_FMT_RGB565: return 16; 192 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 193 case MIPI_DSI_FMT_RGB666: 194 case MIPI_DSI_FMT_RGB888: 195 default: return 24; 196 } 197 } 198 199 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 200 { 201 return msm_readl(msm_host->ctrl_base + reg); 202 } 203 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 204 { 205 msm_writel(data, msm_host->ctrl_base + reg); 206 } 207 208 static const struct msm_dsi_cfg_handler *dsi_get_config( 209 struct msm_dsi_host *msm_host) 210 { 211 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 212 struct device *dev = &msm_host->pdev->dev; 213 struct clk *ahb_clk; 214 int ret; 215 u32 major = 0, minor = 0; 216 217 cfg_hnd = device_get_match_data(dev); 218 if (cfg_hnd) 219 return cfg_hnd; 220 221 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 222 if (IS_ERR(ahb_clk)) { 223 pr_err("%s: cannot get interface clock\n", __func__); 224 goto exit; 225 } 226 227 pm_runtime_get_sync(dev); 228 229 ret = clk_prepare_enable(ahb_clk); 230 if (ret) { 231 pr_err("%s: unable to enable ahb_clk\n", __func__); 232 goto runtime_put; 233 } 234 235 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 236 if (ret) { 237 pr_err("%s: Invalid version\n", __func__); 238 goto disable_clks; 239 } 240 241 cfg_hnd = msm_dsi_cfg_get(major, minor); 242 243 DBG("%s: Version %x:%x\n", __func__, major, minor); 244 245 disable_clks: 246 clk_disable_unprepare(ahb_clk); 247 runtime_put: 248 pm_runtime_put_sync(dev); 249 exit: 250 return cfg_hnd; 251 } 252 253 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 254 { 255 return container_of(host, struct msm_dsi_host, base); 256 } 257 258 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 259 { 260 struct platform_device *pdev = msm_host->pdev; 261 int ret = 0; 262 263 msm_host->src_clk = msm_clk_get(pdev, "src"); 264 265 if (IS_ERR(msm_host->src_clk)) { 266 ret = PTR_ERR(msm_host->src_clk); 267 pr_err("%s: can't find src clock. ret=%d\n", 268 __func__, ret); 269 msm_host->src_clk = NULL; 270 return ret; 271 } 272 273 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 274 if (!msm_host->esc_clk_src) { 275 ret = -ENODEV; 276 pr_err("%s: can't get esc clock parent. ret=%d\n", 277 __func__, ret); 278 return ret; 279 } 280 281 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 282 if (!msm_host->dsi_clk_src) { 283 ret = -ENODEV; 284 pr_err("%s: can't get src clock parent. ret=%d\n", 285 __func__, ret); 286 } 287 288 return ret; 289 } 290 291 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 292 { 293 struct platform_device *pdev = msm_host->pdev; 294 int ret = 0; 295 296 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 297 if (IS_ERR(msm_host->byte_intf_clk)) { 298 ret = PTR_ERR(msm_host->byte_intf_clk); 299 pr_err("%s: can't find byte_intf clock. ret=%d\n", 300 __func__, ret); 301 } 302 303 return ret; 304 } 305 306 static int dsi_clk_init(struct msm_dsi_host *msm_host) 307 { 308 struct platform_device *pdev = msm_host->pdev; 309 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 310 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 311 int i, ret = 0; 312 313 /* get bus clocks */ 314 for (i = 0; i < cfg->num_bus_clks; i++) 315 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 316 msm_host->num_bus_clks = cfg->num_bus_clks; 317 318 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 319 if (ret < 0) { 320 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); 321 goto exit; 322 } 323 324 /* get link and source clocks */ 325 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 326 if (IS_ERR(msm_host->byte_clk)) { 327 ret = PTR_ERR(msm_host->byte_clk); 328 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 329 __func__, ret); 330 msm_host->byte_clk = NULL; 331 goto exit; 332 } 333 334 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 335 if (IS_ERR(msm_host->pixel_clk)) { 336 ret = PTR_ERR(msm_host->pixel_clk); 337 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 338 __func__, ret); 339 msm_host->pixel_clk = NULL; 340 goto exit; 341 } 342 343 msm_host->esc_clk = msm_clk_get(pdev, "core"); 344 if (IS_ERR(msm_host->esc_clk)) { 345 ret = PTR_ERR(msm_host->esc_clk); 346 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 347 __func__, ret); 348 msm_host->esc_clk = NULL; 349 goto exit; 350 } 351 352 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 353 if (IS_ERR(msm_host->byte_clk_src)) { 354 ret = PTR_ERR(msm_host->byte_clk_src); 355 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 356 goto exit; 357 } 358 359 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 360 if (IS_ERR(msm_host->pixel_clk_src)) { 361 ret = PTR_ERR(msm_host->pixel_clk_src); 362 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 363 goto exit; 364 } 365 366 if (cfg_hnd->ops->clk_init_ver) 367 ret = cfg_hnd->ops->clk_init_ver(msm_host); 368 exit: 369 return ret; 370 } 371 372 int msm_dsi_runtime_suspend(struct device *dev) 373 { 374 struct platform_device *pdev = to_platform_device(dev); 375 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 376 struct mipi_dsi_host *host = msm_dsi->host; 377 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 378 379 if (!msm_host->cfg_hnd) 380 return 0; 381 382 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 383 384 return 0; 385 } 386 387 int msm_dsi_runtime_resume(struct device *dev) 388 { 389 struct platform_device *pdev = to_platform_device(dev); 390 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 391 struct mipi_dsi_host *host = msm_dsi->host; 392 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 393 394 if (!msm_host->cfg_hnd) 395 return 0; 396 397 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 398 } 399 400 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 401 { 402 int ret; 403 404 DBG("Set clk rates: pclk=%d, byteclk=%lu", 405 msm_host->mode->clock, msm_host->byte_clk_rate); 406 407 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 408 msm_host->byte_clk_rate); 409 if (ret) { 410 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 411 return ret; 412 } 413 414 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 415 if (ret) { 416 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 417 return ret; 418 } 419 420 if (msm_host->byte_intf_clk) { 421 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 422 if (ret) { 423 pr_err("%s: Failed to set rate byte intf clk, %d\n", 424 __func__, ret); 425 return ret; 426 } 427 } 428 429 return 0; 430 } 431 432 433 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 434 { 435 int ret; 436 437 ret = clk_prepare_enable(msm_host->esc_clk); 438 if (ret) { 439 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 440 goto error; 441 } 442 443 ret = clk_prepare_enable(msm_host->byte_clk); 444 if (ret) { 445 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 446 goto byte_clk_err; 447 } 448 449 ret = clk_prepare_enable(msm_host->pixel_clk); 450 if (ret) { 451 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 452 goto pixel_clk_err; 453 } 454 455 ret = clk_prepare_enable(msm_host->byte_intf_clk); 456 if (ret) { 457 pr_err("%s: Failed to enable byte intf clk\n", 458 __func__); 459 goto byte_intf_clk_err; 460 } 461 462 return 0; 463 464 byte_intf_clk_err: 465 clk_disable_unprepare(msm_host->pixel_clk); 466 pixel_clk_err: 467 clk_disable_unprepare(msm_host->byte_clk); 468 byte_clk_err: 469 clk_disable_unprepare(msm_host->esc_clk); 470 error: 471 return ret; 472 } 473 474 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 475 { 476 int ret; 477 478 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 479 msm_host->mode->clock, msm_host->byte_clk_rate, 480 msm_host->esc_clk_rate, msm_host->src_clk_rate); 481 482 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 483 if (ret) { 484 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 485 return ret; 486 } 487 488 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 489 if (ret) { 490 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 491 return ret; 492 } 493 494 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 495 if (ret) { 496 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 497 return ret; 498 } 499 500 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 501 if (ret) { 502 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 503 return ret; 504 } 505 506 return 0; 507 } 508 509 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 510 { 511 int ret; 512 513 ret = clk_prepare_enable(msm_host->byte_clk); 514 if (ret) { 515 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 516 goto error; 517 } 518 519 ret = clk_prepare_enable(msm_host->esc_clk); 520 if (ret) { 521 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 522 goto esc_clk_err; 523 } 524 525 ret = clk_prepare_enable(msm_host->src_clk); 526 if (ret) { 527 pr_err("%s: Failed to enable dsi src clk\n", __func__); 528 goto src_clk_err; 529 } 530 531 ret = clk_prepare_enable(msm_host->pixel_clk); 532 if (ret) { 533 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 534 goto pixel_clk_err; 535 } 536 537 return 0; 538 539 pixel_clk_err: 540 clk_disable_unprepare(msm_host->src_clk); 541 src_clk_err: 542 clk_disable_unprepare(msm_host->esc_clk); 543 esc_clk_err: 544 clk_disable_unprepare(msm_host->byte_clk); 545 error: 546 return ret; 547 } 548 549 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 550 { 551 /* Drop the performance state vote */ 552 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 553 clk_disable_unprepare(msm_host->esc_clk); 554 clk_disable_unprepare(msm_host->pixel_clk); 555 clk_disable_unprepare(msm_host->byte_intf_clk); 556 clk_disable_unprepare(msm_host->byte_clk); 557 } 558 559 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 560 { 561 clk_disable_unprepare(msm_host->pixel_clk); 562 clk_disable_unprepare(msm_host->src_clk); 563 clk_disable_unprepare(msm_host->esc_clk); 564 clk_disable_unprepare(msm_host->byte_clk); 565 } 566 567 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool is_bonded_dsi) 568 { 569 unsigned long pclk_rate; 570 571 pclk_rate = mode->clock * 1000; 572 573 /* 574 * For bonded DSI mode, the current DRM mode has the complete width of the 575 * panel. Since, the complete panel is driven by two DSI controllers, 576 * the clock rates have to be split between the two dsi controllers. 577 * Adjust the byte and pixel clock rates for each dsi host accordingly. 578 */ 579 if (is_bonded_dsi) 580 pclk_rate /= 2; 581 582 return pclk_rate; 583 } 584 585 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 586 const struct drm_display_mode *mode) 587 { 588 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 589 u8 lanes = msm_host->lanes; 590 u32 bpp = dsi_get_bpp(msm_host->format); 591 unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi); 592 u64 pclk_bpp = (u64)pclk_rate * bpp; 593 594 if (lanes == 0) { 595 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 596 lanes = 1; 597 } 598 599 /* CPHY "byte_clk" is in units of 16 bits */ 600 if (msm_host->cphy_mode) 601 do_div(pclk_bpp, (16 * lanes)); 602 else 603 do_div(pclk_bpp, (8 * lanes)); 604 605 return pclk_bpp; 606 } 607 608 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 609 { 610 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi); 611 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 612 msm_host->mode); 613 614 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 615 msm_host->byte_clk_rate); 616 617 } 618 619 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 620 { 621 if (!msm_host->mode) { 622 pr_err("%s: mode not set\n", __func__); 623 return -EINVAL; 624 } 625 626 dsi_calc_pclk(msm_host, is_bonded_dsi); 627 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 628 return 0; 629 } 630 631 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 632 { 633 u32 bpp = dsi_get_bpp(msm_host->format); 634 u64 pclk_bpp; 635 unsigned int esc_mhz, esc_div; 636 unsigned long byte_mhz; 637 638 dsi_calc_pclk(msm_host, is_bonded_dsi); 639 640 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp; 641 do_div(pclk_bpp, 8); 642 msm_host->src_clk_rate = pclk_bpp; 643 644 /* 645 * esc clock is byte clock followed by a 4 bit divider, 646 * we need to find an escape clock frequency within the 647 * mipi DSI spec range within the maximum divider limit 648 * We iterate here between an escape clock frequencey 649 * between 20 Mhz to 5 Mhz and pick up the first one 650 * that can be supported by our divider 651 */ 652 653 byte_mhz = msm_host->byte_clk_rate / 1000000; 654 655 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 656 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 657 658 /* 659 * TODO: Ideally, we shouldn't know what sort of divider 660 * is available in mmss_cc, we're just assuming that 661 * it'll always be a 4 bit divider. Need to come up with 662 * a better way here. 663 */ 664 if (esc_div >= 1 && esc_div <= 16) 665 break; 666 } 667 668 if (esc_mhz < 5) 669 return -EINVAL; 670 671 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 672 673 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 674 msm_host->src_clk_rate); 675 676 return 0; 677 } 678 679 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 680 { 681 u32 intr; 682 unsigned long flags; 683 684 spin_lock_irqsave(&msm_host->intr_lock, flags); 685 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 686 687 if (enable) 688 intr |= mask; 689 else 690 intr &= ~mask; 691 692 DBG("intr=%x enable=%d", intr, enable); 693 694 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 695 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 696 } 697 698 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 699 { 700 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 701 return BURST_MODE; 702 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 703 return NON_BURST_SYNCH_PULSE; 704 705 return NON_BURST_SYNCH_EVENT; 706 } 707 708 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 709 const enum mipi_dsi_pixel_format mipi_fmt) 710 { 711 switch (mipi_fmt) { 712 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 713 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 714 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 715 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 716 default: return VID_DST_FORMAT_RGB888; 717 } 718 } 719 720 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 721 const enum mipi_dsi_pixel_format mipi_fmt) 722 { 723 switch (mipi_fmt) { 724 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 725 case MIPI_DSI_FMT_RGB666_PACKED: 726 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 727 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 728 default: return CMD_DST_FORMAT_RGB888; 729 } 730 } 731 732 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 733 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 734 { 735 u32 flags = msm_host->mode_flags; 736 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 737 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 738 u32 data = 0, lane_ctrl = 0; 739 740 if (!enable) { 741 dsi_write(msm_host, REG_DSI_CTRL, 0); 742 return; 743 } 744 745 if (flags & MIPI_DSI_MODE_VIDEO) { 746 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 747 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 748 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 749 data |= DSI_VID_CFG0_HFP_POWER_STOP; 750 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 751 data |= DSI_VID_CFG0_HBP_POWER_STOP; 752 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 753 data |= DSI_VID_CFG0_HSA_POWER_STOP; 754 /* Always set low power stop mode for BLLP 755 * to let command engine send packets 756 */ 757 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 758 DSI_VID_CFG0_BLLP_POWER_STOP; 759 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 760 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 761 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 762 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 763 764 /* Do not swap RGB colors */ 765 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 766 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 767 } else { 768 /* Do not swap RGB colors */ 769 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 770 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 771 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 772 773 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 774 DSI_CMD_CFG1_WR_MEM_CONTINUE( 775 MIPI_DCS_WRITE_MEMORY_CONTINUE); 776 /* Always insert DCS command */ 777 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 778 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 779 } 780 781 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 782 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 783 DSI_CMD_DMA_CTRL_LOW_POWER); 784 785 data = 0; 786 /* Always assume dedicated TE pin */ 787 data |= DSI_TRIG_CTRL_TE; 788 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 789 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 790 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 791 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 792 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 793 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 794 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 795 796 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 797 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 798 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 799 800 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 801 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 802 phy_shared_timings->clk_pre_inc_by_2) 803 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 804 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 805 806 data = 0; 807 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 808 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 809 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 810 811 /* allow only ack-err-status to generate interrupt */ 812 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 813 814 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 815 816 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 817 818 data = DSI_CTRL_CLK_EN; 819 820 DBG("lane number=%d", msm_host->lanes); 821 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 822 823 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 824 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 825 826 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 827 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 828 829 if (msm_dsi_phy_set_continuous_clock(phy, enable)) 830 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 831 832 dsi_write(msm_host, REG_DSI_LANE_CTRL, 833 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 834 } 835 836 data |= DSI_CTRL_ENABLE; 837 838 dsi_write(msm_host, REG_DSI_CTRL, data); 839 840 if (msm_host->cphy_mode) 841 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 842 } 843 844 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) 845 { 846 struct drm_dsc_config *dsc = msm_host->dsc; 847 u32 reg, reg_ctrl, reg_ctrl2; 848 u32 slice_per_intf, total_bytes_per_intf; 849 u32 pkt_per_line; 850 u32 eol_byte_num; 851 852 /* first calculate dsc parameters and then program 853 * compress mode registers 854 */ 855 slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); 856 857 /* 858 * If slice_count is greater than slice_per_intf 859 * then default to 1. This can happen during partial 860 * update. 861 */ 862 if (dsc->slice_count > slice_per_intf) 863 dsc->slice_count = 1; 864 865 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 866 867 eol_byte_num = total_bytes_per_intf % 3; 868 pkt_per_line = slice_per_intf / dsc->slice_count; 869 870 if (is_cmd_mode) /* packet data type */ 871 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 872 else 873 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 874 875 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 876 * registers have similar offsets, so for below common code use 877 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 878 */ 879 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 880 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 881 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 882 883 if (is_cmd_mode) { 884 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 885 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 886 887 reg_ctrl &= ~0xffff; 888 reg_ctrl |= reg; 889 890 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 891 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 892 893 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 894 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 895 } else { 896 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 897 } 898 } 899 900 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 901 { 902 struct drm_display_mode *mode = msm_host->mode; 903 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 904 u32 h_total = mode->htotal; 905 u32 v_total = mode->vtotal; 906 u32 hs_end = mode->hsync_end - mode->hsync_start; 907 u32 vs_end = mode->vsync_end - mode->vsync_start; 908 u32 ha_start = h_total - mode->hsync_start; 909 u32 ha_end = ha_start + mode->hdisplay; 910 u32 va_start = v_total - mode->vsync_start; 911 u32 va_end = va_start + mode->vdisplay; 912 u32 hdisplay = mode->hdisplay; 913 u32 wc; 914 int ret; 915 916 DBG(""); 917 918 /* 919 * For bonded DSI mode, the current DRM mode has 920 * the complete width of the panel. Since, the complete 921 * panel is driven by two DSI controllers, the horizontal 922 * timings have to be split between the two dsi controllers. 923 * Adjust the DSI host timing values accordingly. 924 */ 925 if (is_bonded_dsi) { 926 h_total /= 2; 927 hs_end /= 2; 928 ha_start /= 2; 929 ha_end /= 2; 930 hdisplay /= 2; 931 } 932 933 if (msm_host->dsc) { 934 struct drm_dsc_config *dsc = msm_host->dsc; 935 936 /* update dsc params with timing params */ 937 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 938 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 939 mode->hdisplay, mode->vdisplay); 940 return; 941 } 942 943 dsc->pic_width = mode->hdisplay; 944 dsc->pic_height = mode->vdisplay; 945 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 946 947 /* we do the calculations for dsc parameters here so that 948 * panel can use these parameters 949 */ 950 ret = dsi_populate_dsc_params(msm_host, dsc); 951 if (ret) 952 return; 953 954 /* Divide the display by 3 but keep back/font porch and 955 * pulse width same 956 */ 957 h_total -= hdisplay; 958 hdisplay /= 3; 959 h_total += hdisplay; 960 ha_end = ha_start + hdisplay; 961 } 962 963 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 964 if (msm_host->dsc) 965 dsi_update_dsc_timing(msm_host, false, mode->hdisplay); 966 967 dsi_write(msm_host, REG_DSI_ACTIVE_H, 968 DSI_ACTIVE_H_START(ha_start) | 969 DSI_ACTIVE_H_END(ha_end)); 970 dsi_write(msm_host, REG_DSI_ACTIVE_V, 971 DSI_ACTIVE_V_START(va_start) | 972 DSI_ACTIVE_V_END(va_end)); 973 dsi_write(msm_host, REG_DSI_TOTAL, 974 DSI_TOTAL_H_TOTAL(h_total - 1) | 975 DSI_TOTAL_V_TOTAL(v_total - 1)); 976 977 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 978 DSI_ACTIVE_HSYNC_START(hs_start) | 979 DSI_ACTIVE_HSYNC_END(hs_end)); 980 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 981 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 982 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 983 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 984 } else { /* command mode */ 985 if (msm_host->dsc) 986 dsi_update_dsc_timing(msm_host, true, mode->hdisplay); 987 988 /* image data and 1 byte write_memory_start cmd */ 989 if (!msm_host->dsc) 990 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 991 else 992 wc = msm_host->dsc->slice_chunk_size * msm_host->dsc->slice_count + 1; 993 994 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 995 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 996 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 997 msm_host->channel) | 998 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 999 MIPI_DSI_DCS_LONG_WRITE)); 1000 1001 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1002 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1003 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1004 } 1005 } 1006 1007 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1008 { 1009 u32 ctrl; 1010 1011 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1012 1013 if (ctrl & DSI_CTRL_ENABLE) { 1014 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1015 /* 1016 * dsi controller need to be disabled before 1017 * clocks turned on 1018 */ 1019 wmb(); 1020 } 1021 1022 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1023 wmb(); /* clocks need to be enabled before reset */ 1024 1025 /* dsi controller can only be reset while clocks are running */ 1026 dsi_write(msm_host, REG_DSI_RESET, 1); 1027 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1028 dsi_write(msm_host, REG_DSI_RESET, 0); 1029 wmb(); /* controller out of reset */ 1030 1031 if (ctrl & DSI_CTRL_ENABLE) { 1032 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1033 wmb(); /* make sure dsi controller enabled again */ 1034 } 1035 } 1036 1037 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1038 bool video_mode, bool enable) 1039 { 1040 u32 dsi_ctrl; 1041 1042 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1043 1044 if (!enable) { 1045 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1046 DSI_CTRL_CMD_MODE_EN); 1047 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1048 DSI_IRQ_MASK_VIDEO_DONE, 0); 1049 } else { 1050 if (video_mode) { 1051 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1052 } else { /* command mode */ 1053 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1054 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1055 } 1056 dsi_ctrl |= DSI_CTRL_ENABLE; 1057 } 1058 1059 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1060 } 1061 1062 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1063 { 1064 u32 data; 1065 1066 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1067 1068 if (mode == 0) 1069 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1070 else 1071 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1072 1073 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1074 } 1075 1076 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1077 { 1078 u32 ret = 0; 1079 struct device *dev = &msm_host->pdev->dev; 1080 1081 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1082 1083 reinit_completion(&msm_host->video_comp); 1084 1085 ret = wait_for_completion_timeout(&msm_host->video_comp, 1086 msecs_to_jiffies(70)); 1087 1088 if (ret == 0) 1089 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1090 1091 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1092 } 1093 1094 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1095 { 1096 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1097 return; 1098 1099 if (msm_host->power_on && msm_host->enabled) { 1100 dsi_wait4video_done(msm_host); 1101 /* delay 4 ms to skip BLLP */ 1102 usleep_range(2000, 4000); 1103 } 1104 } 1105 1106 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1107 { 1108 struct drm_device *dev = msm_host->dev; 1109 struct msm_drm_private *priv = dev->dev_private; 1110 uint64_t iova; 1111 u8 *data; 1112 1113 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1114 priv->kms->aspace, 1115 &msm_host->tx_gem_obj, &iova); 1116 1117 if (IS_ERR(data)) { 1118 msm_host->tx_gem_obj = NULL; 1119 return PTR_ERR(data); 1120 } 1121 1122 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1123 1124 msm_host->tx_size = msm_host->tx_gem_obj->size; 1125 1126 return 0; 1127 } 1128 1129 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1130 { 1131 struct drm_device *dev = msm_host->dev; 1132 1133 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1134 &msm_host->tx_buf_paddr, GFP_KERNEL); 1135 if (!msm_host->tx_buf) 1136 return -ENOMEM; 1137 1138 msm_host->tx_size = size; 1139 1140 return 0; 1141 } 1142 1143 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1144 { 1145 struct drm_device *dev = msm_host->dev; 1146 struct msm_drm_private *priv; 1147 1148 /* 1149 * This is possible if we're tearing down before we've had a chance to 1150 * fully initialize. A very real possibility if our probe is deferred, 1151 * in which case we'll hit msm_dsi_host_destroy() without having run 1152 * through the dsi_tx_buf_alloc(). 1153 */ 1154 if (!dev) 1155 return; 1156 1157 priv = dev->dev_private; 1158 if (msm_host->tx_gem_obj) { 1159 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1160 drm_gem_object_put(msm_host->tx_gem_obj); 1161 msm_host->tx_gem_obj = NULL; 1162 } 1163 1164 if (msm_host->tx_buf) 1165 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1166 msm_host->tx_buf_paddr); 1167 } 1168 1169 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1170 { 1171 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1172 } 1173 1174 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1175 { 1176 return msm_host->tx_buf; 1177 } 1178 1179 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1180 { 1181 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1182 } 1183 1184 /* 1185 * prepare cmd buffer to be txed 1186 */ 1187 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1188 const struct mipi_dsi_msg *msg) 1189 { 1190 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1191 struct mipi_dsi_packet packet; 1192 int len; 1193 int ret; 1194 u8 *data; 1195 1196 ret = mipi_dsi_create_packet(&packet, msg); 1197 if (ret) { 1198 pr_err("%s: create packet failed, %d\n", __func__, ret); 1199 return ret; 1200 } 1201 len = (packet.size + 3) & (~0x3); 1202 1203 if (len > msm_host->tx_size) { 1204 pr_err("%s: packet size is too big\n", __func__); 1205 return -EINVAL; 1206 } 1207 1208 data = cfg_hnd->ops->tx_buf_get(msm_host); 1209 if (IS_ERR(data)) { 1210 ret = PTR_ERR(data); 1211 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1212 return ret; 1213 } 1214 1215 /* MSM specific command format in memory */ 1216 data[0] = packet.header[1]; 1217 data[1] = packet.header[2]; 1218 data[2] = packet.header[0]; 1219 data[3] = BIT(7); /* Last packet */ 1220 if (mipi_dsi_packet_format_is_long(msg->type)) 1221 data[3] |= BIT(6); 1222 if (msg->rx_buf && msg->rx_len) 1223 data[3] |= BIT(5); 1224 1225 /* Long packet */ 1226 if (packet.payload && packet.payload_length) 1227 memcpy(data + 4, packet.payload, packet.payload_length); 1228 1229 /* Append 0xff to the end */ 1230 if (packet.size < len) 1231 memset(data + packet.size, 0xff, len - packet.size); 1232 1233 if (cfg_hnd->ops->tx_buf_put) 1234 cfg_hnd->ops->tx_buf_put(msm_host); 1235 1236 return len; 1237 } 1238 1239 /* 1240 * dsi_short_read1_resp: 1 parameter 1241 */ 1242 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1243 { 1244 u8 *data = msg->rx_buf; 1245 if (data && (msg->rx_len >= 1)) { 1246 *data = buf[1]; /* strip out dcs type */ 1247 return 1; 1248 } else { 1249 pr_err("%s: read data does not match with rx_buf len %zu\n", 1250 __func__, msg->rx_len); 1251 return -EINVAL; 1252 } 1253 } 1254 1255 /* 1256 * dsi_short_read2_resp: 2 parameter 1257 */ 1258 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1259 { 1260 u8 *data = msg->rx_buf; 1261 if (data && (msg->rx_len >= 2)) { 1262 data[0] = buf[1]; /* strip out dcs type */ 1263 data[1] = buf[2]; 1264 return 2; 1265 } else { 1266 pr_err("%s: read data does not match with rx_buf len %zu\n", 1267 __func__, msg->rx_len); 1268 return -EINVAL; 1269 } 1270 } 1271 1272 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1273 { 1274 /* strip out 4 byte dcs header */ 1275 if (msg->rx_buf && msg->rx_len) 1276 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1277 1278 return msg->rx_len; 1279 } 1280 1281 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1282 { 1283 struct drm_device *dev = msm_host->dev; 1284 struct msm_drm_private *priv = dev->dev_private; 1285 1286 if (!dma_base) 1287 return -EINVAL; 1288 1289 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1290 priv->kms->aspace, dma_base); 1291 } 1292 1293 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1294 { 1295 if (!dma_base) 1296 return -EINVAL; 1297 1298 *dma_base = msm_host->tx_buf_paddr; 1299 return 0; 1300 } 1301 1302 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1303 { 1304 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1305 int ret; 1306 uint64_t dma_base; 1307 bool triggered; 1308 1309 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1310 if (ret) { 1311 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1312 return ret; 1313 } 1314 1315 reinit_completion(&msm_host->dma_comp); 1316 1317 dsi_wait4video_eng_busy(msm_host); 1318 1319 triggered = msm_dsi_manager_cmd_xfer_trigger( 1320 msm_host->id, dma_base, len); 1321 if (triggered) { 1322 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1323 msecs_to_jiffies(200)); 1324 DBG("ret=%d", ret); 1325 if (ret == 0) 1326 ret = -ETIMEDOUT; 1327 else 1328 ret = len; 1329 } else 1330 ret = len; 1331 1332 return ret; 1333 } 1334 1335 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1336 u8 *buf, int rx_byte, int pkt_size) 1337 { 1338 u32 *temp, data; 1339 int i, j = 0, cnt; 1340 u32 read_cnt; 1341 u8 reg[16]; 1342 int repeated_bytes = 0; 1343 int buf_offset = buf - msm_host->rx_buf; 1344 1345 temp = (u32 *)reg; 1346 cnt = (rx_byte + 3) >> 2; 1347 if (cnt > 4) 1348 cnt = 4; /* 4 x 32 bits registers only */ 1349 1350 if (rx_byte == 4) 1351 read_cnt = 4; 1352 else 1353 read_cnt = pkt_size + 6; 1354 1355 /* 1356 * In case of multiple reads from the panel, after the first read, there 1357 * is possibility that there are some bytes in the payload repeating in 1358 * the RDBK_DATA registers. Since we read all the parameters from the 1359 * panel right from the first byte for every pass. We need to skip the 1360 * repeating bytes and then append the new parameters to the rx buffer. 1361 */ 1362 if (read_cnt > 16) { 1363 int bytes_shifted; 1364 /* Any data more than 16 bytes will be shifted out. 1365 * The temp read buffer should already contain these bytes. 1366 * The remaining bytes in read buffer are the repeated bytes. 1367 */ 1368 bytes_shifted = read_cnt - 16; 1369 repeated_bytes = buf_offset - bytes_shifted; 1370 } 1371 1372 for (i = cnt - 1; i >= 0; i--) { 1373 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1374 *temp++ = ntohl(data); /* to host byte order */ 1375 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1376 } 1377 1378 for (i = repeated_bytes; i < 16; i++) 1379 buf[j++] = reg[i]; 1380 1381 return j; 1382 } 1383 1384 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1385 const struct mipi_dsi_msg *msg) 1386 { 1387 int len, ret; 1388 int bllp_len = msm_host->mode->hdisplay * 1389 dsi_get_bpp(msm_host->format) / 8; 1390 1391 len = dsi_cmd_dma_add(msm_host, msg); 1392 if (len < 0) { 1393 pr_err("%s: failed to add cmd type = 0x%x\n", 1394 __func__, msg->type); 1395 return len; 1396 } 1397 1398 /* for video mode, do not send cmds more than 1399 * one pixel line, since it only transmit it 1400 * during BLLP. 1401 */ 1402 /* TODO: if the command is sent in LP mode, the bit rate is only 1403 * half of esc clk rate. In this case, if the video is already 1404 * actively streaming, we need to check more carefully if the 1405 * command can be fit into one BLLP. 1406 */ 1407 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1408 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1409 __func__, len); 1410 return -EINVAL; 1411 } 1412 1413 ret = dsi_cmd_dma_tx(msm_host, len); 1414 if (ret < 0) { 1415 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1416 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1417 return ret; 1418 } else if (ret < len) { 1419 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1420 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1421 return -EIO; 1422 } 1423 1424 return len; 1425 } 1426 1427 static void dsi_err_worker(struct work_struct *work) 1428 { 1429 struct msm_dsi_host *msm_host = 1430 container_of(work, struct msm_dsi_host, err_work); 1431 u32 status = msm_host->err_work_state; 1432 1433 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1434 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1435 dsi_sw_reset(msm_host); 1436 1437 /* It is safe to clear here because error irq is disabled. */ 1438 msm_host->err_work_state = 0; 1439 1440 /* enable dsi error interrupt */ 1441 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1442 } 1443 1444 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1445 { 1446 u32 status; 1447 1448 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1449 1450 if (status) { 1451 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1452 /* Writing of an extra 0 needed to clear error bits */ 1453 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1454 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1455 } 1456 } 1457 1458 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1459 { 1460 u32 status; 1461 1462 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1463 1464 if (status) { 1465 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1466 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1467 } 1468 } 1469 1470 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1471 { 1472 u32 status; 1473 1474 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1475 1476 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1477 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1478 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1479 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1480 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1481 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1482 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1483 } 1484 } 1485 1486 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1487 { 1488 u32 status; 1489 1490 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1491 1492 /* fifo underflow, overflow */ 1493 if (status) { 1494 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1495 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1496 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1497 msm_host->err_work_state |= 1498 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1499 } 1500 } 1501 1502 static void dsi_status(struct msm_dsi_host *msm_host) 1503 { 1504 u32 status; 1505 1506 status = dsi_read(msm_host, REG_DSI_STATUS0); 1507 1508 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1509 dsi_write(msm_host, REG_DSI_STATUS0, status); 1510 msm_host->err_work_state |= 1511 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1512 } 1513 } 1514 1515 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1516 { 1517 u32 status; 1518 1519 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1520 1521 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1522 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1523 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1524 } 1525 } 1526 1527 static void dsi_error(struct msm_dsi_host *msm_host) 1528 { 1529 /* disable dsi error interrupt */ 1530 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1531 1532 dsi_clk_status(msm_host); 1533 dsi_fifo_status(msm_host); 1534 dsi_ack_err_status(msm_host); 1535 dsi_timeout_status(msm_host); 1536 dsi_status(msm_host); 1537 dsi_dln0_phy_err(msm_host); 1538 1539 queue_work(msm_host->workqueue, &msm_host->err_work); 1540 } 1541 1542 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1543 { 1544 struct msm_dsi_host *msm_host = ptr; 1545 u32 isr; 1546 unsigned long flags; 1547 1548 if (!msm_host->ctrl_base) 1549 return IRQ_HANDLED; 1550 1551 spin_lock_irqsave(&msm_host->intr_lock, flags); 1552 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1553 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1554 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1555 1556 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1557 1558 if (isr & DSI_IRQ_ERROR) 1559 dsi_error(msm_host); 1560 1561 if (isr & DSI_IRQ_VIDEO_DONE) 1562 complete(&msm_host->video_comp); 1563 1564 if (isr & DSI_IRQ_CMD_DMA_DONE) 1565 complete(&msm_host->dma_comp); 1566 1567 return IRQ_HANDLED; 1568 } 1569 1570 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1571 struct device *panel_device) 1572 { 1573 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1574 "disp-enable", 1575 GPIOD_OUT_LOW); 1576 if (IS_ERR(msm_host->disp_en_gpio)) { 1577 DBG("cannot get disp-enable-gpios %ld", 1578 PTR_ERR(msm_host->disp_en_gpio)); 1579 return PTR_ERR(msm_host->disp_en_gpio); 1580 } 1581 1582 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1583 GPIOD_IN); 1584 if (IS_ERR(msm_host->te_gpio)) { 1585 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1586 return PTR_ERR(msm_host->te_gpio); 1587 } 1588 1589 return 0; 1590 } 1591 1592 static int dsi_host_attach(struct mipi_dsi_host *host, 1593 struct mipi_dsi_device *dsi) 1594 { 1595 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1596 int ret; 1597 1598 if (dsi->lanes > msm_host->num_data_lanes) 1599 return -EINVAL; 1600 1601 msm_host->channel = dsi->channel; 1602 msm_host->lanes = dsi->lanes; 1603 msm_host->format = dsi->format; 1604 msm_host->mode_flags = dsi->mode_flags; 1605 if (dsi->dsc) 1606 msm_host->dsc = dsi->dsc; 1607 1608 /* Some gpios defined in panel DT need to be controlled by host */ 1609 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1610 if (ret) 1611 return ret; 1612 1613 ret = dsi_dev_attach(msm_host->pdev); 1614 if (ret) 1615 return ret; 1616 1617 DBG("id=%d", msm_host->id); 1618 1619 return 0; 1620 } 1621 1622 static int dsi_host_detach(struct mipi_dsi_host *host, 1623 struct mipi_dsi_device *dsi) 1624 { 1625 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1626 1627 dsi_dev_detach(msm_host->pdev); 1628 1629 DBG("id=%d", msm_host->id); 1630 1631 return 0; 1632 } 1633 1634 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1635 const struct mipi_dsi_msg *msg) 1636 { 1637 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1638 int ret; 1639 1640 if (!msg || !msm_host->power_on) 1641 return -EINVAL; 1642 1643 mutex_lock(&msm_host->cmd_mutex); 1644 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1645 mutex_unlock(&msm_host->cmd_mutex); 1646 1647 return ret; 1648 } 1649 1650 static const struct mipi_dsi_host_ops dsi_host_ops = { 1651 .attach = dsi_host_attach, 1652 .detach = dsi_host_detach, 1653 .transfer = dsi_host_transfer, 1654 }; 1655 1656 /* 1657 * List of supported physical to logical lane mappings. 1658 * For example, the 2nd entry represents the following mapping: 1659 * 1660 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1661 */ 1662 static const int supported_data_lane_swaps[][4] = { 1663 { 0, 1, 2, 3 }, 1664 { 3, 0, 1, 2 }, 1665 { 2, 3, 0, 1 }, 1666 { 1, 2, 3, 0 }, 1667 { 0, 3, 2, 1 }, 1668 { 1, 0, 3, 2 }, 1669 { 2, 1, 0, 3 }, 1670 { 3, 2, 1, 0 }, 1671 }; 1672 1673 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1674 struct device_node *ep) 1675 { 1676 struct device *dev = &msm_host->pdev->dev; 1677 struct property *prop; 1678 u32 lane_map[4]; 1679 int ret, i, len, num_lanes; 1680 1681 prop = of_find_property(ep, "data-lanes", &len); 1682 if (!prop) { 1683 DRM_DEV_DEBUG(dev, 1684 "failed to find data lane mapping, using default\n"); 1685 /* Set the number of date lanes to 4 by default. */ 1686 msm_host->num_data_lanes = 4; 1687 return 0; 1688 } 1689 1690 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1691 if (num_lanes < 0) { 1692 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1693 return num_lanes; 1694 } 1695 1696 msm_host->num_data_lanes = num_lanes; 1697 1698 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1699 num_lanes); 1700 if (ret) { 1701 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1702 return ret; 1703 } 1704 1705 /* 1706 * compare DT specified physical-logical lane mappings with the ones 1707 * supported by hardware 1708 */ 1709 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1710 const int *swap = supported_data_lane_swaps[i]; 1711 int j; 1712 1713 /* 1714 * the data-lanes array we get from DT has a logical->physical 1715 * mapping. The "data lane swap" register field represents 1716 * supported configurations in a physical->logical mapping. 1717 * Translate the DT mapping to what we understand and find a 1718 * configuration that works. 1719 */ 1720 for (j = 0; j < num_lanes; j++) { 1721 if (lane_map[j] < 0 || lane_map[j] > 3) 1722 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1723 lane_map[j]); 1724 1725 if (swap[lane_map[j]] != j) 1726 break; 1727 } 1728 1729 if (j == num_lanes) { 1730 msm_host->dlane_swap = i; 1731 return 0; 1732 } 1733 } 1734 1735 return -EINVAL; 1736 } 1737 1738 static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { 1739 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 1740 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e 1741 }; 1742 1743 /* only 8bpc, 8bpp added */ 1744 static char min_qp[DSC_NUM_BUF_RANGES] = { 1745 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 1746 }; 1747 1748 static char max_qp[DSC_NUM_BUF_RANGES] = { 1749 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 1750 }; 1751 1752 static char bpg_offset[DSC_NUM_BUF_RANGES] = { 1753 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 1754 }; 1755 1756 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1757 { 1758 int i; 1759 u16 bpp = dsc->bits_per_pixel >> 4; 1760 1761 if (dsc->bits_per_pixel & 0xf) { 1762 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1763 return -EINVAL; 1764 } 1765 1766 if (dsc->bits_per_component != 8) { 1767 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); 1768 return -EOPNOTSUPP; 1769 } 1770 1771 dsc->rc_model_size = 8192; 1772 dsc->first_line_bpg_offset = 12; 1773 dsc->rc_edge_factor = 6; 1774 dsc->rc_tgt_offset_high = 3; 1775 dsc->rc_tgt_offset_low = 3; 1776 dsc->simple_422 = 0; 1777 dsc->convert_rgb = 1; 1778 dsc->vbr_enable = 0; 1779 1780 /* handle only bpp = bpc = 8 */ 1781 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) 1782 dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; 1783 1784 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 1785 dsc->rc_range_params[i].range_min_qp = min_qp[i]; 1786 dsc->rc_range_params[i].range_max_qp = max_qp[i]; 1787 /* 1788 * Range BPG Offset contains two's-complement signed values that fill 1789 * 8 bits, yet the registers and DCS PPS field are only 6 bits wide. 1790 */ 1791 dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK; 1792 } 1793 1794 dsc->initial_offset = 6144; /* Not bpp 12 */ 1795 if (bpp != 8) 1796 dsc->initial_offset = 2048; /* bpp = 12 */ 1797 1798 if (dsc->bits_per_component <= 10) 1799 dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 1800 else 1801 dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 1802 1803 dsc->initial_xmit_delay = 512; 1804 dsc->initial_scale_value = 32; 1805 dsc->first_line_bpg_offset = 12; 1806 dsc->line_buf_depth = dsc->bits_per_component + 1; 1807 1808 /* bpc 8 */ 1809 dsc->flatness_min_qp = 3; 1810 dsc->flatness_max_qp = 12; 1811 dsc->rc_quant_incr_limit0 = 11; 1812 dsc->rc_quant_incr_limit1 = 11; 1813 1814 return drm_dsc_compute_rc_parameters(dsc); 1815 } 1816 1817 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1818 { 1819 struct device *dev = &msm_host->pdev->dev; 1820 struct device_node *np = dev->of_node; 1821 struct device_node *endpoint; 1822 int ret = 0; 1823 1824 /* 1825 * Get the endpoint of the output port of the DSI host. In our case, 1826 * this is mapped to port number with reg = 1. Don't return an error if 1827 * the remote endpoint isn't defined. It's possible that there is 1828 * nothing connected to the dsi output. 1829 */ 1830 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1831 if (!endpoint) { 1832 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1833 return 0; 1834 } 1835 1836 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1837 if (ret) { 1838 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1839 __func__, ret); 1840 ret = -EINVAL; 1841 goto err; 1842 } 1843 1844 if (of_property_read_bool(np, "syscon-sfpb")) { 1845 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1846 "syscon-sfpb"); 1847 if (IS_ERR(msm_host->sfpb)) { 1848 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1849 __func__); 1850 ret = PTR_ERR(msm_host->sfpb); 1851 } 1852 } 1853 1854 err: 1855 of_node_put(endpoint); 1856 1857 return ret; 1858 } 1859 1860 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1861 { 1862 struct platform_device *pdev = msm_host->pdev; 1863 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1864 struct resource *res; 1865 int i; 1866 1867 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1868 if (!res) 1869 return -EINVAL; 1870 1871 for (i = 0; i < cfg->num_dsi; i++) { 1872 if (cfg->io_start[i] == res->start) 1873 return i; 1874 } 1875 1876 return -EINVAL; 1877 } 1878 1879 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1880 { 1881 struct msm_dsi_host *msm_host = NULL; 1882 struct platform_device *pdev = msm_dsi->pdev; 1883 const struct msm_dsi_config *cfg; 1884 int ret; 1885 1886 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1887 if (!msm_host) { 1888 return -ENOMEM; 1889 } 1890 1891 msm_host->pdev = pdev; 1892 msm_dsi->host = &msm_host->base; 1893 1894 ret = dsi_host_parse_dt(msm_host); 1895 if (ret) { 1896 pr_err("%s: failed to parse dt\n", __func__); 1897 return ret; 1898 } 1899 1900 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1901 if (IS_ERR(msm_host->ctrl_base)) { 1902 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1903 return PTR_ERR(msm_host->ctrl_base); 1904 } 1905 1906 pm_runtime_enable(&pdev->dev); 1907 1908 msm_host->cfg_hnd = dsi_get_config(msm_host); 1909 if (!msm_host->cfg_hnd) { 1910 pr_err("%s: get config failed\n", __func__); 1911 return -EINVAL; 1912 } 1913 cfg = msm_host->cfg_hnd->cfg; 1914 1915 msm_host->id = dsi_host_get_id(msm_host); 1916 if (msm_host->id < 0) { 1917 pr_err("%s: unable to identify DSI host index\n", __func__); 1918 return msm_host->id; 1919 } 1920 1921 /* fixup base address by io offset */ 1922 msm_host->ctrl_base += cfg->io_offset; 1923 1924 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 1925 cfg->regulator_data, 1926 &msm_host->supplies); 1927 if (ret) 1928 return ret; 1929 1930 ret = dsi_clk_init(msm_host); 1931 if (ret) { 1932 pr_err("%s: unable to initialize dsi clks\n", __func__); 1933 return ret; 1934 } 1935 1936 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1937 if (!msm_host->rx_buf) { 1938 pr_err("%s: alloc rx temp buf failed\n", __func__); 1939 return -ENOMEM; 1940 } 1941 1942 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 1943 if (ret) 1944 return ret; 1945 /* OPP table is optional */ 1946 ret = devm_pm_opp_of_add_table(&pdev->dev); 1947 if (ret && ret != -ENODEV) { 1948 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1949 return ret; 1950 } 1951 1952 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1953 if (msm_host->irq < 0) { 1954 ret = msm_host->irq; 1955 dev_err(&pdev->dev, "failed to get irq: %d\n", ret); 1956 return ret; 1957 } 1958 1959 /* do not autoenable, will be enabled later */ 1960 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 1961 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 1962 "dsi_isr", msm_host); 1963 if (ret < 0) { 1964 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1965 msm_host->irq, ret); 1966 return ret; 1967 } 1968 1969 init_completion(&msm_host->dma_comp); 1970 init_completion(&msm_host->video_comp); 1971 mutex_init(&msm_host->dev_mutex); 1972 mutex_init(&msm_host->cmd_mutex); 1973 spin_lock_init(&msm_host->intr_lock); 1974 1975 /* setup workqueue */ 1976 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1977 if (!msm_host->workqueue) 1978 return -ENOMEM; 1979 1980 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1981 1982 msm_dsi->id = msm_host->id; 1983 1984 DBG("Dsi Host %d initialized", msm_host->id); 1985 return 0; 1986 } 1987 1988 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1989 { 1990 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1991 1992 DBG(""); 1993 dsi_tx_buf_free(msm_host); 1994 if (msm_host->workqueue) { 1995 destroy_workqueue(msm_host->workqueue); 1996 msm_host->workqueue = NULL; 1997 } 1998 1999 mutex_destroy(&msm_host->cmd_mutex); 2000 mutex_destroy(&msm_host->dev_mutex); 2001 2002 pm_runtime_disable(&msm_host->pdev->dev); 2003 } 2004 2005 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2006 struct drm_device *dev) 2007 { 2008 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2009 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2010 int ret; 2011 2012 msm_host->dev = dev; 2013 2014 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2015 if (ret) { 2016 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2017 return ret; 2018 } 2019 2020 return 0; 2021 } 2022 2023 int msm_dsi_host_register(struct mipi_dsi_host *host) 2024 { 2025 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2026 int ret; 2027 2028 /* Register mipi dsi host */ 2029 if (!msm_host->registered) { 2030 host->dev = &msm_host->pdev->dev; 2031 host->ops = &dsi_host_ops; 2032 ret = mipi_dsi_host_register(host); 2033 if (ret) 2034 return ret; 2035 2036 msm_host->registered = true; 2037 } 2038 2039 return 0; 2040 } 2041 2042 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2043 { 2044 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2045 2046 if (msm_host->registered) { 2047 mipi_dsi_host_unregister(host); 2048 host->dev = NULL; 2049 host->ops = NULL; 2050 msm_host->registered = false; 2051 } 2052 } 2053 2054 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2055 const struct mipi_dsi_msg *msg) 2056 { 2057 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2058 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2059 2060 /* TODO: make sure dsi_cmd_mdp is idle. 2061 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2062 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2063 * How to handle the old versions? Wait for mdp cmd done? 2064 */ 2065 2066 /* 2067 * mdss interrupt is generated in mdp core clock domain 2068 * mdp clock need to be enabled to receive dsi interrupt 2069 */ 2070 pm_runtime_get_sync(&msm_host->pdev->dev); 2071 cfg_hnd->ops->link_clk_set_rate(msm_host); 2072 cfg_hnd->ops->link_clk_enable(msm_host); 2073 2074 /* TODO: vote for bus bandwidth */ 2075 2076 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2077 dsi_set_tx_power_mode(0, msm_host); 2078 2079 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2080 dsi_write(msm_host, REG_DSI_CTRL, 2081 msm_host->dma_cmd_ctrl_restore | 2082 DSI_CTRL_CMD_MODE_EN | 2083 DSI_CTRL_ENABLE); 2084 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2085 2086 return 0; 2087 } 2088 2089 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2090 const struct mipi_dsi_msg *msg) 2091 { 2092 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2093 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2094 2095 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2096 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2097 2098 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2099 dsi_set_tx_power_mode(1, msm_host); 2100 2101 /* TODO: unvote for bus bandwidth */ 2102 2103 cfg_hnd->ops->link_clk_disable(msm_host); 2104 pm_runtime_put(&msm_host->pdev->dev); 2105 } 2106 2107 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2108 const struct mipi_dsi_msg *msg) 2109 { 2110 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2111 2112 return dsi_cmds2buf_tx(msm_host, msg); 2113 } 2114 2115 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2116 const struct mipi_dsi_msg *msg) 2117 { 2118 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2119 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2120 int data_byte, rx_byte, dlen, end; 2121 int short_response, diff, pkt_size, ret = 0; 2122 char cmd; 2123 int rlen = msg->rx_len; 2124 u8 *buf; 2125 2126 if (rlen <= 2) { 2127 short_response = 1; 2128 pkt_size = rlen; 2129 rx_byte = 4; 2130 } else { 2131 short_response = 0; 2132 data_byte = 10; /* first read */ 2133 if (rlen < data_byte) 2134 pkt_size = rlen; 2135 else 2136 pkt_size = data_byte; 2137 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2138 } 2139 2140 buf = msm_host->rx_buf; 2141 end = 0; 2142 while (!end) { 2143 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2144 struct mipi_dsi_msg max_pkt_size_msg = { 2145 .channel = msg->channel, 2146 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2147 .tx_len = 2, 2148 .tx_buf = tx, 2149 }; 2150 2151 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2152 rlen, pkt_size, rx_byte); 2153 2154 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2155 if (ret < 2) { 2156 pr_err("%s: Set max pkt size failed, %d\n", 2157 __func__, ret); 2158 return -EINVAL; 2159 } 2160 2161 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2162 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2163 /* Clear the RDBK_DATA registers */ 2164 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2165 DSI_RDBK_DATA_CTRL_CLR); 2166 wmb(); /* make sure the RDBK registers are cleared */ 2167 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2168 wmb(); /* release cleared status before transfer */ 2169 } 2170 2171 ret = dsi_cmds2buf_tx(msm_host, msg); 2172 if (ret < 0) { 2173 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2174 return ret; 2175 } else if (ret < msg->tx_len) { 2176 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2177 return -ECOMM; 2178 } 2179 2180 /* 2181 * once cmd_dma_done interrupt received, 2182 * return data from client is ready and stored 2183 * at RDBK_DATA register already 2184 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2185 * after that dcs header lost during shift into registers 2186 */ 2187 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2188 2189 if (dlen <= 0) 2190 return 0; 2191 2192 if (short_response) 2193 break; 2194 2195 if (rlen <= data_byte) { 2196 diff = data_byte - rlen; 2197 end = 1; 2198 } else { 2199 diff = 0; 2200 rlen -= data_byte; 2201 } 2202 2203 if (!end) { 2204 dlen -= 2; /* 2 crc */ 2205 dlen -= diff; 2206 buf += dlen; /* next start position */ 2207 data_byte = 14; /* NOT first read */ 2208 if (rlen < data_byte) 2209 pkt_size += rlen; 2210 else 2211 pkt_size += data_byte; 2212 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2213 } 2214 } 2215 2216 /* 2217 * For single Long read, if the requested rlen < 10, 2218 * we need to shift the start position of rx 2219 * data buffer to skip the bytes which are not 2220 * updated. 2221 */ 2222 if (pkt_size < 10 && !short_response) 2223 buf = msm_host->rx_buf + (10 - rlen); 2224 else 2225 buf = msm_host->rx_buf; 2226 2227 cmd = buf[0]; 2228 switch (cmd) { 2229 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2230 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2231 ret = 0; 2232 break; 2233 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2234 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2235 ret = dsi_short_read1_resp(buf, msg); 2236 break; 2237 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2238 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2239 ret = dsi_short_read2_resp(buf, msg); 2240 break; 2241 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2242 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2243 ret = dsi_long_read_resp(buf, msg); 2244 break; 2245 default: 2246 pr_warn("%s:Invalid response cmd\n", __func__); 2247 ret = 0; 2248 } 2249 2250 return ret; 2251 } 2252 2253 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2254 u32 len) 2255 { 2256 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2257 2258 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2259 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2260 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2261 2262 /* Make sure trigger happens */ 2263 wmb(); 2264 } 2265 2266 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2267 struct msm_dsi_phy *src_phy) 2268 { 2269 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2270 2271 msm_host->cphy_mode = src_phy->cphy_mode; 2272 } 2273 2274 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2275 { 2276 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2277 2278 DBG(""); 2279 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2280 /* Make sure fully reset */ 2281 wmb(); 2282 udelay(1000); 2283 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2284 udelay(100); 2285 } 2286 2287 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2288 struct msm_dsi_phy_clk_request *clk_req, 2289 bool is_bonded_dsi) 2290 { 2291 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2292 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2293 int ret; 2294 2295 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2296 if (ret) { 2297 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2298 return; 2299 } 2300 2301 /* CPHY transmits 16 bits over 7 clock cycles 2302 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2303 * so multiply by 7 to get the "bitclk rate" 2304 */ 2305 if (msm_host->cphy_mode) 2306 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2307 else 2308 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2309 clk_req->escclk_rate = msm_host->esc_clk_rate; 2310 } 2311 2312 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2313 { 2314 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2315 2316 enable_irq(msm_host->irq); 2317 } 2318 2319 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2320 { 2321 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2322 2323 disable_irq(msm_host->irq); 2324 } 2325 2326 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2327 { 2328 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2329 2330 dsi_op_mode_config(msm_host, 2331 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2332 2333 /* TODO: clock should be turned off for command mode, 2334 * and only turned on before MDP START. 2335 * This part of code should be enabled once mdp driver support it. 2336 */ 2337 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2338 * dsi_link_clk_disable(msm_host); 2339 * pm_runtime_put(&msm_host->pdev->dev); 2340 * } 2341 */ 2342 msm_host->enabled = true; 2343 return 0; 2344 } 2345 2346 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2347 { 2348 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2349 2350 msm_host->enabled = false; 2351 dsi_op_mode_config(msm_host, 2352 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2353 2354 /* Since we have disabled INTF, the video engine won't stop so that 2355 * the cmd engine will be blocked. 2356 * Reset to disable video engine so that we can send off cmd. 2357 */ 2358 dsi_sw_reset(msm_host); 2359 2360 return 0; 2361 } 2362 2363 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2364 { 2365 enum sfpb_ahb_arb_master_port_en en; 2366 2367 if (!msm_host->sfpb) 2368 return; 2369 2370 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2371 2372 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2373 SFPB_GPREG_MASTER_PORT_EN__MASK, 2374 SFPB_GPREG_MASTER_PORT_EN(en)); 2375 } 2376 2377 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2378 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2379 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2380 { 2381 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2382 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2383 int ret = 0; 2384 2385 mutex_lock(&msm_host->dev_mutex); 2386 if (msm_host->power_on) { 2387 DBG("dsi host already on"); 2388 goto unlock_ret; 2389 } 2390 2391 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2392 if (phy_shared_timings->byte_intf_clk_div_2) 2393 msm_host->byte_intf_clk_rate /= 2; 2394 2395 msm_dsi_sfpb_config(msm_host, true); 2396 2397 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2398 msm_host->supplies); 2399 if (ret) { 2400 pr_err("%s:Failed to enable vregs.ret=%d\n", 2401 __func__, ret); 2402 goto unlock_ret; 2403 } 2404 2405 pm_runtime_get_sync(&msm_host->pdev->dev); 2406 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2407 if (!ret) 2408 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2409 if (ret) { 2410 pr_err("%s: failed to enable link clocks. ret=%d\n", 2411 __func__, ret); 2412 goto fail_disable_reg; 2413 } 2414 2415 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2416 if (ret) { 2417 pr_err("%s: failed to set pinctrl default state, %d\n", 2418 __func__, ret); 2419 goto fail_disable_clk; 2420 } 2421 2422 dsi_timing_setup(msm_host, is_bonded_dsi); 2423 dsi_sw_reset(msm_host); 2424 dsi_ctrl_config(msm_host, true, phy_shared_timings, phy); 2425 2426 if (msm_host->disp_en_gpio) 2427 gpiod_set_value(msm_host->disp_en_gpio, 1); 2428 2429 msm_host->power_on = true; 2430 mutex_unlock(&msm_host->dev_mutex); 2431 2432 return 0; 2433 2434 fail_disable_clk: 2435 cfg_hnd->ops->link_clk_disable(msm_host); 2436 pm_runtime_put(&msm_host->pdev->dev); 2437 fail_disable_reg: 2438 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2439 msm_host->supplies); 2440 unlock_ret: 2441 mutex_unlock(&msm_host->dev_mutex); 2442 return ret; 2443 } 2444 2445 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2446 { 2447 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2448 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2449 2450 mutex_lock(&msm_host->dev_mutex); 2451 if (!msm_host->power_on) { 2452 DBG("dsi host already off"); 2453 goto unlock_ret; 2454 } 2455 2456 dsi_ctrl_config(msm_host, false, NULL, NULL); 2457 2458 if (msm_host->disp_en_gpio) 2459 gpiod_set_value(msm_host->disp_en_gpio, 0); 2460 2461 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2462 2463 cfg_hnd->ops->link_clk_disable(msm_host); 2464 pm_runtime_put(&msm_host->pdev->dev); 2465 2466 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2467 msm_host->supplies); 2468 2469 msm_dsi_sfpb_config(msm_host, false); 2470 2471 DBG("-"); 2472 2473 msm_host->power_on = false; 2474 2475 unlock_ret: 2476 mutex_unlock(&msm_host->dev_mutex); 2477 return 0; 2478 } 2479 2480 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2481 const struct drm_display_mode *mode) 2482 { 2483 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2484 2485 if (msm_host->mode) { 2486 drm_mode_destroy(msm_host->dev, msm_host->mode); 2487 msm_host->mode = NULL; 2488 } 2489 2490 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2491 if (!msm_host->mode) { 2492 pr_err("%s: cannot duplicate mode\n", __func__); 2493 return -ENOMEM; 2494 } 2495 2496 return 0; 2497 } 2498 2499 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2500 const struct drm_display_mode *mode) 2501 { 2502 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2503 struct drm_dsc_config *dsc = msm_host->dsc; 2504 int pic_width = mode->hdisplay; 2505 int pic_height = mode->vdisplay; 2506 2507 if (!msm_host->dsc) 2508 return MODE_OK; 2509 2510 if (pic_width % dsc->slice_width) { 2511 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2512 pic_width, dsc->slice_width); 2513 return MODE_H_ILLEGAL; 2514 } 2515 2516 if (pic_height % dsc->slice_height) { 2517 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2518 pic_height, dsc->slice_height); 2519 return MODE_V_ILLEGAL; 2520 } 2521 2522 return MODE_OK; 2523 } 2524 2525 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2526 { 2527 return to_msm_dsi_host(host)->mode_flags; 2528 } 2529 2530 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2531 { 2532 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2533 2534 pm_runtime_get_sync(&msm_host->pdev->dev); 2535 2536 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2537 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2538 2539 pm_runtime_put_sync(&msm_host->pdev->dev); 2540 } 2541 2542 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2543 { 2544 u32 reg; 2545 2546 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2547 2548 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2549 /* draw checkered rectangle pattern */ 2550 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2551 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2552 /* use 24-bit RGB test pttern */ 2553 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2554 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2555 DSI_TPG_VIDEO_CONFIG_RGB); 2556 2557 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2558 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2559 2560 DBG("Video test pattern setup done\n"); 2561 } 2562 2563 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2564 { 2565 u32 reg; 2566 2567 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2568 2569 /* initial value for test pattern */ 2570 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2571 2572 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2573 2574 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2575 /* draw checkered rectangle pattern */ 2576 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2577 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2578 2579 DBG("Cmd test pattern setup done\n"); 2580 } 2581 2582 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2583 { 2584 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2585 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2586 u32 reg; 2587 2588 if (is_video_mode) 2589 msm_dsi_host_video_test_pattern_setup(msm_host); 2590 else 2591 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2592 2593 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2594 /* enable the test pattern generator */ 2595 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2596 2597 /* for command mode need to trigger one frame from tpg */ 2598 if (!is_video_mode) 2599 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2600 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2601 } 2602 2603 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2604 { 2605 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2606 2607 return msm_host->dsc; 2608 } 2609