1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/interconnect/qcom,sdm660.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/soc/qcom,apr.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 mmc1 = &sdhc_1; 26 mmc2 = &sdhc_2; 27 }; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <19200000>; 36 clock-output-names = "xo_board"; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <32764>; 43 clock-output-names = "sleep_clk"; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 CPU0: cpu@100 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x100>; 55 enable-method = "psci"; 56 cpu-idle-states = <&PERF_CPU_SLEEP_0 57 &PERF_CPU_SLEEP_1 58 &PERF_CLUSTER_SLEEP_0 59 &PERF_CLUSTER_SLEEP_1 60 &PERF_CLUSTER_SLEEP_2>; 61 capacity-dmips-mhz = <1126>; 62 #cooling-cells = <2>; 63 next-level-cache = <&L2_1>; 64 L2_1: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 }; 69 }; 70 71 CPU1: cpu@101 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x0 0x101>; 75 enable-method = "psci"; 76 cpu-idle-states = <&PERF_CPU_SLEEP_0 77 &PERF_CPU_SLEEP_1 78 &PERF_CLUSTER_SLEEP_0 79 &PERF_CLUSTER_SLEEP_1 80 &PERF_CLUSTER_SLEEP_2>; 81 capacity-dmips-mhz = <1126>; 82 #cooling-cells = <2>; 83 next-level-cache = <&L2_1>; 84 }; 85 86 CPU2: cpu@102 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x0 0x102>; 90 enable-method = "psci"; 91 cpu-idle-states = <&PERF_CPU_SLEEP_0 92 &PERF_CPU_SLEEP_1 93 &PERF_CLUSTER_SLEEP_0 94 &PERF_CLUSTER_SLEEP_1 95 &PERF_CLUSTER_SLEEP_2>; 96 capacity-dmips-mhz = <1126>; 97 #cooling-cells = <2>; 98 next-level-cache = <&L2_1>; 99 }; 100 101 CPU3: cpu@103 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x0 0x103>; 105 enable-method = "psci"; 106 cpu-idle-states = <&PERF_CPU_SLEEP_0 107 &PERF_CPU_SLEEP_1 108 &PERF_CLUSTER_SLEEP_0 109 &PERF_CLUSTER_SLEEP_1 110 &PERF_CLUSTER_SLEEP_2>; 111 capacity-dmips-mhz = <1126>; 112 #cooling-cells = <2>; 113 next-level-cache = <&L2_1>; 114 }; 115 116 CPU4: cpu@0 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x0 0x0>; 120 enable-method = "psci"; 121 cpu-idle-states = <&PWR_CPU_SLEEP_0 122 &PWR_CPU_SLEEP_1 123 &PWR_CLUSTER_SLEEP_0 124 &PWR_CLUSTER_SLEEP_1 125 &PWR_CLUSTER_SLEEP_2>; 126 capacity-dmips-mhz = <1024>; 127 #cooling-cells = <2>; 128 next-level-cache = <&L2_0>; 129 L2_0: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 }; 134 }; 135 136 CPU5: cpu@1 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a53"; 139 reg = <0x0 0x1>; 140 enable-method = "psci"; 141 cpu-idle-states = <&PWR_CPU_SLEEP_0 142 &PWR_CPU_SLEEP_1 143 &PWR_CLUSTER_SLEEP_0 144 &PWR_CLUSTER_SLEEP_1 145 &PWR_CLUSTER_SLEEP_2>; 146 capacity-dmips-mhz = <1024>; 147 #cooling-cells = <2>; 148 next-level-cache = <&L2_0>; 149 }; 150 151 CPU6: cpu@2 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a53"; 154 reg = <0x0 0x2>; 155 enable-method = "psci"; 156 cpu-idle-states = <&PWR_CPU_SLEEP_0 157 &PWR_CPU_SLEEP_1 158 &PWR_CLUSTER_SLEEP_0 159 &PWR_CLUSTER_SLEEP_1 160 &PWR_CLUSTER_SLEEP_2>; 161 capacity-dmips-mhz = <1024>; 162 #cooling-cells = <2>; 163 next-level-cache = <&L2_0>; 164 }; 165 166 CPU7: cpu@3 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x0 0x3>; 170 enable-method = "psci"; 171 cpu-idle-states = <&PWR_CPU_SLEEP_0 172 &PWR_CPU_SLEEP_1 173 &PWR_CLUSTER_SLEEP_0 174 &PWR_CLUSTER_SLEEP_1 175 &PWR_CLUSTER_SLEEP_2>; 176 capacity-dmips-mhz = <1024>; 177 #cooling-cells = <2>; 178 next-level-cache = <&L2_0>; 179 }; 180 181 cpu-map { 182 cluster0 { 183 core0 { 184 cpu = <&CPU4>; 185 }; 186 187 core1 { 188 cpu = <&CPU5>; 189 }; 190 191 core2 { 192 cpu = <&CPU6>; 193 }; 194 195 core3 { 196 cpu = <&CPU7>; 197 }; 198 }; 199 200 cluster1 { 201 core0 { 202 cpu = <&CPU0>; 203 }; 204 205 core1 { 206 cpu = <&CPU1>; 207 }; 208 209 core2 { 210 cpu = <&CPU2>; 211 }; 212 213 core3 { 214 cpu = <&CPU3>; 215 }; 216 }; 217 }; 218 219 idle-states { 220 entry-method = "psci"; 221 222 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 223 compatible = "arm,idle-state"; 224 idle-state-name = "pwr-retention"; 225 arm,psci-suspend-param = <0x40000002>; 226 entry-latency-us = <338>; 227 exit-latency-us = <423>; 228 min-residency-us = <200>; 229 }; 230 231 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 232 compatible = "arm,idle-state"; 233 idle-state-name = "pwr-power-collapse"; 234 arm,psci-suspend-param = <0x40000003>; 235 entry-latency-us = <515>; 236 exit-latency-us = <1821>; 237 min-residency-us = <1000>; 238 local-timer-stop; 239 }; 240 241 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 242 compatible = "arm,idle-state"; 243 idle-state-name = "perf-retention"; 244 arm,psci-suspend-param = <0x40000002>; 245 entry-latency-us = <154>; 246 exit-latency-us = <87>; 247 min-residency-us = <200>; 248 }; 249 250 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "perf-power-collapse"; 253 arm,psci-suspend-param = <0x40000003>; 254 entry-latency-us = <262>; 255 exit-latency-us = <301>; 256 min-residency-us = <1000>; 257 local-timer-stop; 258 }; 259 260 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "pwr-cluster-dynamic-retention"; 263 arm,psci-suspend-param = <0x400000F2>; 264 entry-latency-us = <284>; 265 exit-latency-us = <384>; 266 min-residency-us = <9987>; 267 local-timer-stop; 268 }; 269 270 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 271 compatible = "arm,idle-state"; 272 idle-state-name = "pwr-cluster-retention"; 273 arm,psci-suspend-param = <0x400000F3>; 274 entry-latency-us = <338>; 275 exit-latency-us = <423>; 276 min-residency-us = <9987>; 277 local-timer-stop; 278 }; 279 280 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "pwr-cluster-retention"; 283 arm,psci-suspend-param = <0x400000F4>; 284 entry-latency-us = <515>; 285 exit-latency-us = <1821>; 286 min-residency-us = <9987>; 287 local-timer-stop; 288 }; 289 290 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "perf-cluster-dynamic-retention"; 293 arm,psci-suspend-param = <0x400000F2>; 294 entry-latency-us = <272>; 295 exit-latency-us = <329>; 296 min-residency-us = <9987>; 297 local-timer-stop; 298 }; 299 300 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "perf-cluster-retention"; 303 arm,psci-suspend-param = <0x400000F3>; 304 entry-latency-us = <332>; 305 exit-latency-us = <368>; 306 min-residency-us = <9987>; 307 local-timer-stop; 308 }; 309 310 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "perf-cluster-retention"; 313 arm,psci-suspend-param = <0x400000F4>; 314 entry-latency-us = <545>; 315 exit-latency-us = <1609>; 316 min-residency-us = <9987>; 317 local-timer-stop; 318 }; 319 }; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-msm8998", "qcom,scm"; 325 }; 326 }; 327 328 memory@80000000 { 329 device_type = "memory"; 330 /* We expect the bootloader to fill in the reg */ 331 reg = <0x0 0x80000000 0x0 0x0>; 332 }; 333 334 dsi_opp_table: opp-table-dsi { 335 compatible = "operating-points-v2"; 336 337 opp-131250000 { 338 opp-hz = /bits/ 64 <131250000>; 339 required-opps = <&rpmpd_opp_svs>; 340 }; 341 342 opp-210000000 { 343 opp-hz = /bits/ 64 <210000000>; 344 required-opps = <&rpmpd_opp_svs_plus>; 345 }; 346 347 opp-262500000 { 348 opp-hz = /bits/ 64 <262500000>; 349 required-opps = <&rpmpd_opp_nom>; 350 }; 351 }; 352 353 pmu { 354 compatible = "arm,armv8-pmuv3"; 355 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 356 }; 357 358 psci { 359 compatible = "arm,psci-1.0"; 360 method = "smc"; 361 }; 362 363 rpm: remoteproc { 364 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc"; 365 366 glink-edge { 367 compatible = "qcom,glink-rpm"; 368 369 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 370 qcom,rpm-msg-ram = <&rpm_msg_ram>; 371 mboxes = <&apcs_glb 0>; 372 373 rpm_requests: rpm-requests { 374 compatible = "qcom,rpm-sdm660"; 375 qcom,glink-channels = "rpm_requests"; 376 377 rpmcc: clock-controller { 378 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 379 #clock-cells = <1>; 380 }; 381 382 rpmpd: power-controller { 383 compatible = "qcom,sdm660-rpmpd"; 384 #power-domain-cells = <1>; 385 operating-points-v2 = <&rpmpd_opp_table>; 386 387 rpmpd_opp_table: opp-table { 388 compatible = "operating-points-v2"; 389 390 rpmpd_opp_ret: opp1 { 391 opp-level = <RPM_SMD_LEVEL_RETENTION>; 392 }; 393 394 rpmpd_opp_ret_plus: opp2 { 395 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 396 }; 397 398 rpmpd_opp_min_svs: opp3 { 399 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 400 }; 401 402 rpmpd_opp_low_svs: opp4 { 403 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 404 }; 405 406 rpmpd_opp_svs: opp5 { 407 opp-level = <RPM_SMD_LEVEL_SVS>; 408 }; 409 410 rpmpd_opp_svs_plus: opp6 { 411 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 412 }; 413 414 rpmpd_opp_nom: opp7 { 415 opp-level = <RPM_SMD_LEVEL_NOM>; 416 }; 417 418 rpmpd_opp_nom_plus: opp8 { 419 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 420 }; 421 422 rpmpd_opp_turbo: opp9 { 423 opp-level = <RPM_SMD_LEVEL_TURBO>; 424 }; 425 }; 426 }; 427 }; 428 }; 429 }; 430 431 reserved-memory { 432 #address-cells = <2>; 433 #size-cells = <2>; 434 ranges; 435 436 wlan_msa_guard: wlan-msa-guard@85600000 { 437 reg = <0x0 0x85600000 0x0 0x100000>; 438 no-map; 439 }; 440 441 wlan_msa_mem: wlan-msa-mem@85700000 { 442 reg = <0x0 0x85700000 0x0 0x100000>; 443 no-map; 444 }; 445 446 qhee_code: qhee-code@85800000 { 447 reg = <0x0 0x85800000 0x0 0x600000>; 448 no-map; 449 }; 450 451 rmtfs_mem: memory@85e00000 { 452 compatible = "qcom,rmtfs-mem"; 453 reg = <0x0 0x85e00000 0x0 0x200000>; 454 no-map; 455 456 qcom,client-id = <1>; 457 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 458 }; 459 460 smem_region: smem-mem@86000000 { 461 reg = <0 0x86000000 0 0x200000>; 462 no-map; 463 }; 464 465 tz_mem: memory@86200000 { 466 reg = <0x0 0x86200000 0x0 0x3300000>; 467 no-map; 468 }; 469 470 mpss_region: mpss@8ac00000 { 471 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 472 no-map; 473 }; 474 475 adsp_region: adsp@92a00000 { 476 reg = <0x0 0x92a00000 0x0 0x1e00000>; 477 no-map; 478 }; 479 480 mba_region: mba@94800000 { 481 reg = <0x0 0x94800000 0x0 0x200000>; 482 no-map; 483 }; 484 485 buffer_mem: tzbuffer@94a00000 { 486 reg = <0x0 0x94a00000 0x0 0x100000>; 487 no-map; 488 }; 489 490 venus_region: venus@9f800000 { 491 reg = <0x0 0x9f800000 0x0 0x800000>; 492 no-map; 493 }; 494 495 adsp_mem: adsp-region@f6000000 { 496 reg = <0x0 0xf6000000 0x0 0x800000>; 497 no-map; 498 }; 499 500 qseecom_mem: qseecom-region@f6800000 { 501 reg = <0x0 0xf6800000 0x0 0x1400000>; 502 no-map; 503 }; 504 505 zap_shader_region: gpu@fed00000 { 506 compatible = "shared-dma-pool"; 507 reg = <0x0 0xfed00000 0x0 0xa00000>; 508 no-map; 509 }; 510 }; 511 512 smem: smem { 513 compatible = "qcom,smem"; 514 memory-region = <&smem_region>; 515 hwlocks = <&tcsr_mutex 3>; 516 }; 517 518 smp2p-adsp { 519 compatible = "qcom,smp2p"; 520 qcom,smem = <443>, <429>; 521 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 522 mboxes = <&apcs_glb 10>; 523 qcom,local-pid = <0>; 524 qcom,remote-pid = <2>; 525 526 adsp_smp2p_out: master-kernel { 527 qcom,entry-name = "master-kernel"; 528 #qcom,smem-state-cells = <1>; 529 }; 530 531 adsp_smp2p_in: slave-kernel { 532 qcom,entry-name = "slave-kernel"; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 }; 536 }; 537 538 smp2p-mpss { 539 compatible = "qcom,smp2p"; 540 qcom,smem = <435>, <428>; 541 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 542 mboxes = <&apcs_glb 14>; 543 qcom,local-pid = <0>; 544 qcom,remote-pid = <1>; 545 546 modem_smp2p_out: master-kernel { 547 qcom,entry-name = "master-kernel"; 548 #qcom,smem-state-cells = <1>; 549 }; 550 551 modem_smp2p_in: slave-kernel { 552 qcom,entry-name = "slave-kernel"; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 }; 556 }; 557 558 soc@0 { 559 #address-cells = <1>; 560 #size-cells = <1>; 561 ranges = <0 0 0 0xffffffff>; 562 compatible = "simple-bus"; 563 564 gcc: clock-controller@100000 { 565 compatible = "qcom,gcc-sdm630"; 566 #clock-cells = <1>; 567 #reset-cells = <1>; 568 #power-domain-cells = <1>; 569 reg = <0x00100000 0x94000>; 570 571 clock-names = "xo", "sleep_clk"; 572 clocks = <&xo_board>, 573 <&sleep_clk>; 574 }; 575 576 rpm_msg_ram: sram@778000 { 577 compatible = "qcom,rpm-msg-ram"; 578 reg = <0x00778000 0x7000>; 579 }; 580 581 qfprom: qfprom@780000 { 582 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 583 reg = <0x00780000 0x621c>; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 587 qusb2_hstx_trim: hstx-trim@240 { 588 reg = <0x243 0x1>; 589 bits = <1 3>; 590 }; 591 592 gpu_speed_bin: gpu-speed-bin@41a0 { 593 reg = <0x41a2 0x1>; 594 bits = <5 7>; 595 }; 596 }; 597 598 rng: rng@793000 { 599 compatible = "qcom,prng-ee"; 600 reg = <0x00793000 0x1000>; 601 clocks = <&gcc GCC_PRNG_AHB_CLK>; 602 clock-names = "core"; 603 }; 604 605 bimc: interconnect@1008000 { 606 compatible = "qcom,sdm660-bimc"; 607 reg = <0x01008000 0x78000>; 608 #interconnect-cells = <1>; 609 }; 610 611 restart@10ac000 { 612 compatible = "qcom,pshold"; 613 reg = <0x010ac000 0x4>; 614 }; 615 616 cnoc: interconnect@1500000 { 617 compatible = "qcom,sdm660-cnoc"; 618 reg = <0x01500000 0x10000>; 619 #interconnect-cells = <1>; 620 }; 621 622 snoc: interconnect@1626000 { 623 compatible = "qcom,sdm660-snoc"; 624 reg = <0x01626000 0x7090>; 625 #interconnect-cells = <1>; 626 }; 627 628 anoc2_smmu: iommu@16c0000 { 629 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 630 reg = <0x016c0000 0x40000>; 631 #global-interrupts = <2>; 632 #iommu-cells = <1>; 633 634 interrupts = 635 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 637 638 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 640 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 641 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 642 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 643 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 644 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 667 668 status = "disabled"; 669 }; 670 671 a2noc: interconnect@1704000 { 672 compatible = "qcom,sdm660-a2noc"; 673 reg = <0x01704000 0xc100>; 674 #interconnect-cells = <1>; 675 clock-names = "ipa", 676 "ufs_axi", 677 "aggre2_ufs_axi", 678 "aggre2_usb3_axi", 679 "cfg_noc_usb2_axi"; 680 clocks = <&rpmcc RPM_SMD_IPA_CLK>, 681 <&gcc GCC_UFS_AXI_CLK>, 682 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 683 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 684 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 685 }; 686 687 mnoc: interconnect@1745000 { 688 compatible = "qcom,sdm660-mnoc"; 689 reg = <0x01745000 0xa010>; 690 #interconnect-cells = <1>; 691 clock-names = "iface"; 692 clocks = <&mmcc AHB_CLK_SRC>; 693 }; 694 695 tsens: thermal-sensor@10ae000 { 696 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 697 reg = <0x010ae000 0x1000>, /* TM */ 698 <0x010ad000 0x1000>; /* SROT */ 699 #qcom,sensors = <12>; 700 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 702 interrupt-names = "uplow", "critical"; 703 #thermal-sensor-cells = <1>; 704 }; 705 706 tcsr_mutex: hwlock@1f40000 { 707 compatible = "qcom,tcsr-mutex"; 708 reg = <0x01f40000 0x20000>; 709 #hwlock-cells = <1>; 710 }; 711 712 tcsr_regs_1: syscon@1f60000 { 713 compatible = "qcom,sdm630-tcsr", "syscon"; 714 reg = <0x01f60000 0x20000>; 715 }; 716 717 tlmm: pinctrl@3100000 { 718 compatible = "qcom,sdm630-pinctrl"; 719 reg = <0x03100000 0x400000>, 720 <0x03500000 0x400000>, 721 <0x03900000 0x400000>; 722 reg-names = "south", "center", "north"; 723 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 724 gpio-controller; 725 gpio-ranges = <&tlmm 0 0 114>; 726 #gpio-cells = <2>; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 730 blsp1_uart1_default: blsp1-uart1-default-state { 731 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 732 function = "blsp_uart1"; 733 drive-strength = <2>; 734 bias-disable; 735 }; 736 737 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 738 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 739 function = "gpio"; 740 drive-strength = <2>; 741 bias-disable; 742 }; 743 744 blsp1_uart2_default: blsp1-uart2-default-state { 745 pins = "gpio4", "gpio5"; 746 function = "blsp_uart2"; 747 drive-strength = <2>; 748 bias-disable; 749 }; 750 751 blsp2_uart1_default: blsp2-uart1-active-state { 752 tx-rts-pins { 753 pins = "gpio16", "gpio19"; 754 function = "blsp_uart5"; 755 drive-strength = <2>; 756 bias-disable; 757 }; 758 759 rx-pins { 760 /* 761 * Avoid garbage data while BT module 762 * is powered off or not driving signal 763 */ 764 pins = "gpio17"; 765 function = "blsp_uart5"; 766 drive-strength = <2>; 767 bias-pull-up; 768 }; 769 770 cts-pins { 771 /* Match the pull of the BT module */ 772 pins = "gpio18"; 773 function = "blsp_uart5"; 774 drive-strength = <2>; 775 bias-pull-down; 776 }; 777 }; 778 779 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 780 tx-pins { 781 pins = "gpio16"; 782 function = "gpio"; 783 drive-strength = <2>; 784 bias-pull-up; 785 }; 786 787 rx-cts-rts-pins { 788 pins = "gpio17", "gpio18", "gpio19"; 789 function = "gpio"; 790 drive-strength = <2>; 791 bias-disable; 792 }; 793 }; 794 795 i2c1_default: i2c1-default-state { 796 pins = "gpio2", "gpio3"; 797 function = "blsp_i2c1"; 798 drive-strength = <2>; 799 bias-disable; 800 }; 801 802 i2c1_sleep: i2c1-sleep-state { 803 pins = "gpio2", "gpio3"; 804 function = "blsp_i2c1"; 805 drive-strength = <2>; 806 bias-pull-up; 807 }; 808 809 i2c2_default: i2c2-default-state { 810 pins = "gpio6", "gpio7"; 811 function = "blsp_i2c2"; 812 drive-strength = <2>; 813 bias-disable; 814 }; 815 816 i2c2_sleep: i2c2-sleep-state { 817 pins = "gpio6", "gpio7"; 818 function = "blsp_i2c2"; 819 drive-strength = <2>; 820 bias-pull-up; 821 }; 822 823 i2c3_default: i2c3-default-state { 824 pins = "gpio10", "gpio11"; 825 function = "blsp_i2c3"; 826 drive-strength = <2>; 827 bias-disable; 828 }; 829 830 i2c3_sleep: i2c3-sleep-state { 831 pins = "gpio10", "gpio11"; 832 function = "blsp_i2c3"; 833 drive-strength = <2>; 834 bias-pull-up; 835 }; 836 837 i2c4_default: i2c4-default-state { 838 pins = "gpio14", "gpio15"; 839 function = "blsp_i2c4"; 840 drive-strength = <2>; 841 bias-disable; 842 }; 843 844 i2c4_sleep: i2c4-sleep-state { 845 pins = "gpio14", "gpio15"; 846 function = "blsp_i2c4"; 847 drive-strength = <2>; 848 bias-pull-up; 849 }; 850 851 i2c5_default: i2c5-default-state { 852 pins = "gpio18", "gpio19"; 853 function = "blsp_i2c5"; 854 drive-strength = <2>; 855 bias-disable; 856 }; 857 858 i2c5_sleep: i2c5-sleep-state { 859 pins = "gpio18", "gpio19"; 860 function = "blsp_i2c5"; 861 drive-strength = <2>; 862 bias-pull-up; 863 }; 864 865 i2c6_default: i2c6-default-state { 866 pins = "gpio22", "gpio23"; 867 function = "blsp_i2c6"; 868 drive-strength = <2>; 869 bias-disable; 870 }; 871 872 i2c6_sleep: i2c6-sleep-state { 873 pins = "gpio22", "gpio23"; 874 function = "blsp_i2c6"; 875 drive-strength = <2>; 876 bias-pull-up; 877 }; 878 879 i2c7_default: i2c7-default-state { 880 pins = "gpio26", "gpio27"; 881 function = "blsp_i2c7"; 882 drive-strength = <2>; 883 bias-disable; 884 }; 885 886 i2c7_sleep: i2c7-sleep-state { 887 pins = "gpio26", "gpio27"; 888 function = "blsp_i2c7"; 889 drive-strength = <2>; 890 bias-pull-up; 891 }; 892 893 i2c8_default: i2c8-default-state { 894 pins = "gpio30", "gpio31"; 895 function = "blsp_i2c8_a"; 896 drive-strength = <2>; 897 bias-disable; 898 }; 899 900 i2c8_sleep: i2c8-sleep-state { 901 pins = "gpio30", "gpio31"; 902 function = "blsp_i2c8_a"; 903 drive-strength = <2>; 904 bias-pull-up; 905 }; 906 907 cci0_default: cci0-default-state { 908 pins = "gpio36","gpio37"; 909 function = "cci_i2c"; 910 bias-pull-up; 911 drive-strength = <2>; 912 }; 913 914 cci1_default: cci1-default-state { 915 pins = "gpio38","gpio39"; 916 function = "cci_i2c"; 917 bias-pull-up; 918 drive-strength = <2>; 919 }; 920 921 sdc1_state_on: sdc1-on-state { 922 clk-pins { 923 pins = "sdc1_clk"; 924 bias-disable; 925 drive-strength = <16>; 926 }; 927 928 cmd-pins { 929 pins = "sdc1_cmd"; 930 bias-pull-up; 931 drive-strength = <10>; 932 }; 933 934 data-pins { 935 pins = "sdc1_data"; 936 bias-pull-up; 937 drive-strength = <10>; 938 }; 939 940 rclk-pins { 941 pins = "sdc1_rclk"; 942 bias-pull-down; 943 }; 944 }; 945 946 sdc1_state_off: sdc1-off-state { 947 clk-pins { 948 pins = "sdc1_clk"; 949 bias-disable; 950 drive-strength = <2>; 951 }; 952 953 cmd-pins { 954 pins = "sdc1_cmd"; 955 bias-pull-up; 956 drive-strength = <2>; 957 }; 958 959 data-pins { 960 pins = "sdc1_data"; 961 bias-pull-up; 962 drive-strength = <2>; 963 }; 964 965 rclk-pins { 966 pins = "sdc1_rclk"; 967 bias-pull-down; 968 }; 969 }; 970 971 sdc2_state_on: sdc2-on-state { 972 clk-pins { 973 pins = "sdc2_clk"; 974 bias-disable; 975 drive-strength = <16>; 976 }; 977 978 cmd-pins { 979 pins = "sdc2_cmd"; 980 bias-pull-up; 981 drive-strength = <10>; 982 }; 983 984 data-pins { 985 pins = "sdc2_data"; 986 bias-pull-up; 987 drive-strength = <10>; 988 }; 989 }; 990 991 sdc2_state_off: sdc2-off-state { 992 clk-pins { 993 pins = "sdc2_clk"; 994 bias-disable; 995 drive-strength = <2>; 996 }; 997 998 cmd-pins { 999 pins = "sdc2_cmd"; 1000 bias-pull-up; 1001 drive-strength = <2>; 1002 }; 1003 1004 data-pins { 1005 pins = "sdc2_data"; 1006 bias-pull-up; 1007 drive-strength = <2>; 1008 }; 1009 }; 1010 }; 1011 1012 remoteproc_mss: remoteproc@4080000 { 1013 compatible = "qcom,sdm660-mss-pil"; 1014 reg = <0x04080000 0x100>, <0x04180000 0x40>; 1015 reg-names = "qdsp6", "rmb"; 1016 1017 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1018 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1019 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1020 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1021 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1022 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1023 interrupt-names = "wdog", 1024 "fatal", 1025 "ready", 1026 "handover", 1027 "stop-ack", 1028 "shutdown-ack"; 1029 1030 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1031 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1032 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1033 <&gcc GPLL0_OUT_MSSCC>, 1034 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1035 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1036 <&rpmcc RPM_SMD_QDSS_CLK>, 1037 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1038 clock-names = "iface", 1039 "bus", 1040 "mem", 1041 "gpll0_mss", 1042 "snoc_axi", 1043 "mnoc_axi", 1044 "qdss", 1045 "xo"; 1046 1047 qcom,smem-states = <&modem_smp2p_out 0>; 1048 qcom,smem-state-names = "stop"; 1049 1050 resets = <&gcc GCC_MSS_RESTART>; 1051 reset-names = "mss_restart"; 1052 1053 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1054 1055 power-domains = <&rpmpd SDM660_VDDCX>, 1056 <&rpmpd SDM660_VDDMX>; 1057 power-domain-names = "cx", "mx"; 1058 1059 memory-region = <&mba_region>, <&mpss_region>; 1060 1061 status = "disabled"; 1062 1063 glink-edge { 1064 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1065 label = "modem"; 1066 qcom,remote-pid = <1>; 1067 mboxes = <&apcs_glb 15>; 1068 }; 1069 }; 1070 1071 adreno_gpu: gpu@5000000 { 1072 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1073 1074 reg = <0x05000000 0x40000>; 1075 reg-names = "kgsl_3d0_reg_memory"; 1076 1077 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1078 1079 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1080 <&gpucc GPUCC_RBBMTIMER_CLK>, 1081 <&gcc GCC_BIMC_GFX_CLK>, 1082 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1083 <&gpucc GPUCC_RBCPR_CLK>, 1084 <&gpucc GPUCC_GFX3D_CLK>; 1085 1086 clock-names = "iface", 1087 "rbbmtimer", 1088 "mem", 1089 "mem_iface", 1090 "rbcpr", 1091 "core"; 1092 1093 power-domains = <&rpmpd SDM660_VDDMX>; 1094 iommus = <&kgsl_smmu 0>; 1095 1096 nvmem-cells = <&gpu_speed_bin>; 1097 nvmem-cell-names = "speed_bin"; 1098 1099 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1100 interconnect-names = "gfx-mem"; 1101 1102 operating-points-v2 = <&gpu_sdm630_opp_table>; 1103 1104 status = "disabled"; 1105 1106 gpu_sdm630_opp_table: opp-table { 1107 compatible = "operating-points-v2"; 1108 opp-775000000 { 1109 opp-hz = /bits/ 64 <775000000>; 1110 opp-level = <RPM_SMD_LEVEL_TURBO>; 1111 opp-peak-kBps = <5412000>; 1112 opp-supported-hw = <0xa2>; 1113 }; 1114 opp-647000000 { 1115 opp-hz = /bits/ 64 <647000000>; 1116 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1117 opp-peak-kBps = <4068000>; 1118 opp-supported-hw = <0xff>; 1119 }; 1120 opp-588000000 { 1121 opp-hz = /bits/ 64 <588000000>; 1122 opp-level = <RPM_SMD_LEVEL_NOM>; 1123 opp-peak-kBps = <3072000>; 1124 opp-supported-hw = <0xff>; 1125 }; 1126 opp-465000000 { 1127 opp-hz = /bits/ 64 <465000000>; 1128 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1129 opp-peak-kBps = <2724000>; 1130 opp-supported-hw = <0xff>; 1131 }; 1132 opp-370000000 { 1133 opp-hz = /bits/ 64 <370000000>; 1134 opp-level = <RPM_SMD_LEVEL_SVS>; 1135 opp-peak-kBps = <2188000>; 1136 opp-supported-hw = <0xff>; 1137 }; 1138 opp-240000000 { 1139 opp-hz = /bits/ 64 <240000000>; 1140 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1141 opp-peak-kBps = <1648000>; 1142 opp-supported-hw = <0xff>; 1143 }; 1144 opp-160000000 { 1145 opp-hz = /bits/ 64 <160000000>; 1146 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1147 opp-peak-kBps = <1200000>; 1148 opp-supported-hw = <0xff>; 1149 }; 1150 }; 1151 }; 1152 1153 kgsl_smmu: iommu@5040000 { 1154 compatible = "qcom,sdm630-smmu-v2", 1155 "qcom,adreno-smmu", "qcom,smmu-v2"; 1156 reg = <0x05040000 0x10000>; 1157 1158 /* 1159 * GX GDSC parent is CX. We need to bring up CX for SMMU 1160 * but we need both up for Adreno. On the other hand, we 1161 * need to manage the GX rpmpd domain in the adreno driver. 1162 * Enable CX/GX GDSCs here so that we can manage just the GX 1163 * RPM Power Domain in the Adreno driver. 1164 */ 1165 power-domains = <&gpucc GPU_GX_GDSC>; 1166 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1167 <&gcc GCC_BIMC_GFX_CLK>, 1168 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1169 clock-names = "iface", 1170 "mem", 1171 "mem_iface"; 1172 #global-interrupts = <2>; 1173 #iommu-cells = <1>; 1174 1175 interrupts = 1176 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1178 1179 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1187 1188 status = "disabled"; 1189 }; 1190 1191 gpucc: clock-controller@5065000 { 1192 compatible = "qcom,gpucc-sdm630"; 1193 #clock-cells = <1>; 1194 #reset-cells = <1>; 1195 #power-domain-cells = <1>; 1196 reg = <0x05065000 0x9038>; 1197 1198 clocks = <&xo_board>, 1199 <&gcc GCC_GPU_GPLL0_CLK>, 1200 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1201 clock-names = "xo", 1202 "gcc_gpu_gpll0_clk", 1203 "gcc_gpu_gpll0_div_clk"; 1204 status = "disabled"; 1205 }; 1206 1207 lpass_smmu: iommu@5100000 { 1208 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1209 reg = <0x05100000 0x40000>; 1210 #iommu-cells = <1>; 1211 1212 #global-interrupts = <2>; 1213 interrupts = 1214 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1216 1217 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1234 1235 status = "disabled"; 1236 }; 1237 1238 sram@290000 { 1239 compatible = "qcom,rpm-stats"; 1240 reg = <0x00290000 0x10000>; 1241 }; 1242 1243 spmi_bus: spmi@800f000 { 1244 compatible = "qcom,spmi-pmic-arb"; 1245 reg = <0x0800f000 0x1000>, 1246 <0x08400000 0x1000000>, 1247 <0x09400000 0x1000000>, 1248 <0x0a400000 0x220000>, 1249 <0x0800a000 0x3000>; 1250 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1251 interrupt-names = "periph_irq"; 1252 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1253 qcom,ee = <0>; 1254 qcom,channel = <0>; 1255 #address-cells = <2>; 1256 #size-cells = <0>; 1257 interrupt-controller; 1258 #interrupt-cells = <4>; 1259 }; 1260 1261 usb3: usb@a8f8800 { 1262 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1263 reg = <0x0a8f8800 0x400>; 1264 status = "disabled"; 1265 #address-cells = <1>; 1266 #size-cells = <1>; 1267 ranges; 1268 1269 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1270 <&gcc GCC_USB30_MASTER_CLK>, 1271 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1272 <&gcc GCC_USB30_SLEEP_CLK>, 1273 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1274 clock-names = "cfg_noc", 1275 "core", 1276 "iface", 1277 "sleep", 1278 "mock_utmi"; 1279 1280 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1281 <&gcc GCC_USB30_MASTER_CLK>; 1282 assigned-clock-rates = <19200000>, <120000000>; 1283 1284 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1286 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1287 1288 power-domains = <&gcc USB_30_GDSC>; 1289 qcom,select-utmi-as-pipe-clk; 1290 1291 resets = <&gcc GCC_USB_30_BCR>; 1292 1293 usb3_dwc3: usb@a800000 { 1294 compatible = "snps,dwc3"; 1295 reg = <0x0a800000 0xc8d0>; 1296 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1297 snps,dis_u2_susphy_quirk; 1298 snps,dis_enblslpm_quirk; 1299 1300 /* 1301 * SDM630 technically supports USB3 but I 1302 * haven't seen any devices making use of it. 1303 */ 1304 maximum-speed = "high-speed"; 1305 phys = <&qusb2phy0>; 1306 phy-names = "usb2-phy"; 1307 snps,hird-threshold = /bits/ 8 <0>; 1308 }; 1309 }; 1310 1311 qusb2phy0: phy@c012000 { 1312 compatible = "qcom,sdm660-qusb2-phy"; 1313 reg = <0x0c012000 0x180>; 1314 #phy-cells = <0>; 1315 1316 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1317 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1318 clock-names = "cfg_ahb", "ref"; 1319 1320 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1321 nvmem-cells = <&qusb2_hstx_trim>; 1322 status = "disabled"; 1323 }; 1324 1325 qusb2phy1: phy@c014000 { 1326 compatible = "qcom,sdm660-qusb2-phy"; 1327 reg = <0x0c014000 0x180>; 1328 #phy-cells = <0>; 1329 1330 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1331 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1332 clock-names = "cfg_ahb", "ref"; 1333 1334 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1335 nvmem-cells = <&qusb2_hstx_trim>; 1336 status = "disabled"; 1337 }; 1338 1339 sdhc_2: mmc@c084000 { 1340 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1341 reg = <0x0c084000 0x1000>; 1342 reg-names = "hc"; 1343 1344 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1346 interrupt-names = "hc_irq", "pwr_irq"; 1347 1348 bus-width = <4>; 1349 1350 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1351 <&gcc GCC_SDCC2_APPS_CLK>, 1352 <&xo_board>; 1353 clock-names = "iface", "core", "xo"; 1354 1355 1356 interconnects = <&a2noc 3 &a2noc 10>, 1357 <&gnoc 0 &cnoc 28>; 1358 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1359 operating-points-v2 = <&sdhc2_opp_table>; 1360 1361 pinctrl-names = "default", "sleep"; 1362 pinctrl-0 = <&sdc2_state_on>; 1363 pinctrl-1 = <&sdc2_state_off>; 1364 power-domains = <&rpmpd SDM660_VDDCX>; 1365 1366 status = "disabled"; 1367 1368 sdhc2_opp_table: opp-table { 1369 compatible = "operating-points-v2"; 1370 1371 opp-50000000 { 1372 opp-hz = /bits/ 64 <50000000>; 1373 required-opps = <&rpmpd_opp_low_svs>; 1374 opp-peak-kBps = <200000 140000>; 1375 opp-avg-kBps = <130718 133320>; 1376 }; 1377 opp-100000000 { 1378 opp-hz = /bits/ 64 <100000000>; 1379 required-opps = <&rpmpd_opp_svs>; 1380 opp-peak-kBps = <250000 160000>; 1381 opp-avg-kBps = <196078 150000>; 1382 }; 1383 opp-200000000 { 1384 opp-hz = /bits/ 64 <200000000>; 1385 required-opps = <&rpmpd_opp_nom>; 1386 opp-peak-kBps = <4096000 4096000>; 1387 opp-avg-kBps = <1338562 1338562>; 1388 }; 1389 }; 1390 }; 1391 1392 sdhc_1: mmc@c0c4000 { 1393 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1394 reg = <0x0c0c4000 0x1000>, 1395 <0x0c0c5000 0x1000>, 1396 <0x0c0c8000 0x8000>; 1397 reg-names = "hc", "cqhci", "ice"; 1398 1399 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1401 interrupt-names = "hc_irq", "pwr_irq"; 1402 1403 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1404 <&gcc GCC_SDCC1_APPS_CLK>, 1405 <&xo_board>, 1406 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1407 clock-names = "iface", "core", "xo", "ice"; 1408 1409 interconnects = <&a2noc 2 &a2noc 10>, 1410 <&gnoc 0 &cnoc 27>; 1411 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1412 operating-points-v2 = <&sdhc1_opp_table>; 1413 pinctrl-names = "default", "sleep"; 1414 pinctrl-0 = <&sdc1_state_on>; 1415 pinctrl-1 = <&sdc1_state_off>; 1416 power-domains = <&rpmpd SDM660_VDDCX>; 1417 1418 bus-width = <8>; 1419 non-removable; 1420 1421 status = "disabled"; 1422 1423 sdhc1_opp_table: opp-table { 1424 compatible = "operating-points-v2"; 1425 1426 opp-50000000 { 1427 opp-hz = /bits/ 64 <50000000>; 1428 required-opps = <&rpmpd_opp_low_svs>; 1429 opp-peak-kBps = <200000 140000>; 1430 opp-avg-kBps = <130718 133320>; 1431 }; 1432 opp-100000000 { 1433 opp-hz = /bits/ 64 <100000000>; 1434 required-opps = <&rpmpd_opp_svs>; 1435 opp-peak-kBps = <250000 160000>; 1436 opp-avg-kBps = <196078 150000>; 1437 }; 1438 opp-384000000 { 1439 opp-hz = /bits/ 64 <384000000>; 1440 required-opps = <&rpmpd_opp_nom>; 1441 opp-peak-kBps = <4096000 4096000>; 1442 opp-avg-kBps = <1338562 1338562>; 1443 }; 1444 }; 1445 }; 1446 1447 usb2: usb@c2f8800 { 1448 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1449 reg = <0x0c2f8800 0x400>; 1450 status = "disabled"; 1451 #address-cells = <1>; 1452 #size-cells = <1>; 1453 ranges; 1454 1455 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1456 <&gcc GCC_USB20_MASTER_CLK>, 1457 <&gcc GCC_USB20_SLEEP_CLK>, 1458 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 1459 clock-names = "cfg_noc", "core", 1460 "sleep", "mock_utmi"; 1461 1462 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1463 <&gcc GCC_USB20_MASTER_CLK>; 1464 assigned-clock-rates = <19200000>, <60000000>; 1465 1466 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1467 interrupt-names = "hs_phy_irq"; 1468 1469 qcom,select-utmi-as-pipe-clk; 1470 1471 resets = <&gcc GCC_USB_20_BCR>; 1472 1473 usb2_dwc3: usb@c200000 { 1474 compatible = "snps,dwc3"; 1475 reg = <0x0c200000 0xc8d0>; 1476 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1477 snps,dis_u2_susphy_quirk; 1478 snps,dis_enblslpm_quirk; 1479 1480 /* This is the HS-only host */ 1481 maximum-speed = "high-speed"; 1482 phys = <&qusb2phy1>; 1483 phy-names = "usb2-phy"; 1484 snps,hird-threshold = /bits/ 8 <0>; 1485 }; 1486 }; 1487 1488 mmcc: clock-controller@c8c0000 { 1489 compatible = "qcom,mmcc-sdm630"; 1490 reg = <0x0c8c0000 0x40000>; 1491 #clock-cells = <1>; 1492 #reset-cells = <1>; 1493 #power-domain-cells = <1>; 1494 clock-names = "xo", 1495 "sleep_clk", 1496 "gpll0", 1497 "gpll0_div", 1498 "dsi0pll", 1499 "dsi0pllbyte", 1500 "dsi1pll", 1501 "dsi1pllbyte", 1502 "dp_link_2x_clk_divsel_five", 1503 "dp_vco_divided_clk_src_mux"; 1504 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1505 <&sleep_clk>, 1506 <&gcc GCC_MMSS_GPLL0_CLK>, 1507 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1508 <&mdss_dsi0_phy 1>, 1509 <&mdss_dsi0_phy 0>, 1510 <0>, 1511 <0>, 1512 <0>, 1513 <0>; 1514 }; 1515 1516 mdss: display-subsystem@c900000 { 1517 compatible = "qcom,mdss"; 1518 reg = <0x0c900000 0x1000>, 1519 <0x0c9b0000 0x1040>; 1520 reg-names = "mdss_phys", "vbif_phys"; 1521 1522 power-domains = <&mmcc MDSS_GDSC>; 1523 1524 clocks = <&mmcc MDSS_AHB_CLK>, 1525 <&mmcc MDSS_AXI_CLK>, 1526 <&mmcc MDSS_VSYNC_CLK>, 1527 <&mmcc MDSS_MDP_CLK>; 1528 clock-names = "iface", 1529 "bus", 1530 "vsync", 1531 "core"; 1532 1533 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1534 1535 interrupt-controller; 1536 #interrupt-cells = <1>; 1537 1538 #address-cells = <1>; 1539 #size-cells = <1>; 1540 ranges; 1541 status = "disabled"; 1542 1543 mdp: display-controller@c901000 { 1544 compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; 1545 reg = <0x0c901000 0x89000>; 1546 reg-names = "mdp_phys"; 1547 1548 interrupt-parent = <&mdss>; 1549 interrupts = <0>; 1550 1551 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1552 <&mmcc MDSS_VSYNC_CLK>; 1553 assigned-clock-rates = <300000000>, 1554 <19200000>; 1555 clocks = <&mmcc MDSS_AHB_CLK>, 1556 <&mmcc MDSS_AXI_CLK>, 1557 <&mmcc MDSS_MDP_CLK>, 1558 <&mmcc MDSS_VSYNC_CLK>; 1559 clock-names = "iface", 1560 "bus", 1561 "core", 1562 "vsync"; 1563 1564 interconnects = <&mnoc 2 &bimc 5>, 1565 <&mnoc 3 &bimc 5>, 1566 <&gnoc 0 &mnoc 17>; 1567 interconnect-names = "mdp0-mem", 1568 "mdp1-mem", 1569 "rotator-mem"; 1570 iommus = <&mmss_smmu 0>; 1571 operating-points-v2 = <&mdp_opp_table>; 1572 power-domains = <&rpmpd SDM660_VDDCX>; 1573 1574 ports { 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 1578 port@0 { 1579 reg = <0>; 1580 mdp5_intf1_out: endpoint { 1581 remote-endpoint = <&mdss_dsi0_in>; 1582 }; 1583 }; 1584 }; 1585 1586 mdp_opp_table: opp-table { 1587 compatible = "operating-points-v2"; 1588 1589 opp-150000000 { 1590 opp-hz = /bits/ 64 <150000000>; 1591 opp-peak-kBps = <320000 320000 76800>; 1592 required-opps = <&rpmpd_opp_low_svs>; 1593 }; 1594 opp-275000000 { 1595 opp-hz = /bits/ 64 <275000000>; 1596 opp-peak-kBps = <6400000 6400000 160000>; 1597 required-opps = <&rpmpd_opp_svs>; 1598 }; 1599 opp-300000000 { 1600 opp-hz = /bits/ 64 <300000000>; 1601 opp-peak-kBps = <6400000 6400000 190000>; 1602 required-opps = <&rpmpd_opp_svs_plus>; 1603 }; 1604 opp-330000000 { 1605 opp-hz = /bits/ 64 <330000000>; 1606 opp-peak-kBps = <6400000 6400000 240000>; 1607 required-opps = <&rpmpd_opp_nom>; 1608 }; 1609 opp-412500000 { 1610 opp-hz = /bits/ 64 <412500000>; 1611 opp-peak-kBps = <6400000 6400000 320000>; 1612 required-opps = <&rpmpd_opp_turbo>; 1613 }; 1614 }; 1615 }; 1616 1617 mdss_dsi0: dsi@c994000 { 1618 compatible = "qcom,sdm660-dsi-ctrl", 1619 "qcom,mdss-dsi-ctrl"; 1620 reg = <0x0c994000 0x400>; 1621 reg-names = "dsi_ctrl"; 1622 1623 operating-points-v2 = <&dsi_opp_table>; 1624 power-domains = <&rpmpd SDM660_VDDCX>; 1625 1626 interrupt-parent = <&mdss>; 1627 interrupts = <4>; 1628 1629 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1630 <&mmcc PCLK0_CLK_SRC>; 1631 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1632 <&mdss_dsi0_phy 1>; 1633 1634 clocks = <&mmcc MDSS_MDP_CLK>, 1635 <&mmcc MDSS_BYTE0_CLK>, 1636 <&mmcc MDSS_BYTE0_INTF_CLK>, 1637 <&mmcc MNOC_AHB_CLK>, 1638 <&mmcc MDSS_AHB_CLK>, 1639 <&mmcc MDSS_AXI_CLK>, 1640 <&mmcc MISC_AHB_CLK>, 1641 <&mmcc MDSS_PCLK0_CLK>, 1642 <&mmcc MDSS_ESC0_CLK>; 1643 clock-names = "mdp_core", 1644 "byte", 1645 "byte_intf", 1646 "mnoc", 1647 "iface", 1648 "bus", 1649 "core_mmss", 1650 "pixel", 1651 "core"; 1652 1653 phys = <&mdss_dsi0_phy>; 1654 1655 status = "disabled"; 1656 1657 ports { 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 1661 port@0 { 1662 reg = <0>; 1663 mdss_dsi0_in: endpoint { 1664 remote-endpoint = <&mdp5_intf1_out>; 1665 }; 1666 }; 1667 1668 port@1 { 1669 reg = <1>; 1670 mdss_dsi0_out: endpoint { 1671 }; 1672 }; 1673 }; 1674 }; 1675 1676 mdss_dsi0_phy: phy@c994400 { 1677 compatible = "qcom,dsi-phy-14nm-660"; 1678 reg = <0x0c994400 0x100>, 1679 <0x0c994500 0x300>, 1680 <0x0c994800 0x188>; 1681 reg-names = "dsi_phy", 1682 "dsi_phy_lane", 1683 "dsi_pll"; 1684 1685 #clock-cells = <1>; 1686 #phy-cells = <0>; 1687 1688 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1689 clock-names = "iface", "ref"; 1690 status = "disabled"; 1691 }; 1692 }; 1693 1694 blsp1_dma: dma-controller@c144000 { 1695 compatible = "qcom,bam-v1.7.0"; 1696 reg = <0x0c144000 0x1f000>; 1697 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1698 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1699 clock-names = "bam_clk"; 1700 #dma-cells = <1>; 1701 qcom,ee = <0>; 1702 qcom,controlled-remotely; 1703 num-channels = <18>; 1704 qcom,num-ees = <4>; 1705 }; 1706 1707 blsp1_uart1: serial@c16f000 { 1708 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1709 reg = <0x0c16f000 0x200>; 1710 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1711 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1712 <&gcc GCC_BLSP1_AHB_CLK>; 1713 clock-names = "core", "iface"; 1714 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1715 dma-names = "tx", "rx"; 1716 pinctrl-names = "default", "sleep"; 1717 pinctrl-0 = <&blsp1_uart1_default>; 1718 pinctrl-1 = <&blsp1_uart1_sleep>; 1719 status = "disabled"; 1720 }; 1721 1722 blsp1_uart2: serial@c170000 { 1723 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1724 reg = <0x0c170000 0x1000>; 1725 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1726 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1727 <&gcc GCC_BLSP1_AHB_CLK>; 1728 clock-names = "core", "iface"; 1729 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1730 dma-names = "tx", "rx"; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&blsp1_uart2_default>; 1733 status = "disabled"; 1734 }; 1735 1736 blsp_i2c1: i2c@c175000 { 1737 compatible = "qcom,i2c-qup-v2.2.1"; 1738 reg = <0x0c175000 0x600>; 1739 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1740 1741 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1742 <&gcc GCC_BLSP1_AHB_CLK>; 1743 clock-names = "core", "iface"; 1744 clock-frequency = <400000>; 1745 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1746 dma-names = "tx", "rx"; 1747 1748 pinctrl-names = "default", "sleep"; 1749 pinctrl-0 = <&i2c1_default>; 1750 pinctrl-1 = <&i2c1_sleep>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 status = "disabled"; 1754 }; 1755 1756 blsp_i2c2: i2c@c176000 { 1757 compatible = "qcom,i2c-qup-v2.2.1"; 1758 reg = <0x0c176000 0x600>; 1759 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1760 1761 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1762 <&gcc GCC_BLSP1_AHB_CLK>; 1763 clock-names = "core", "iface"; 1764 clock-frequency = <400000>; 1765 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1766 dma-names = "tx", "rx"; 1767 1768 pinctrl-names = "default", "sleep"; 1769 pinctrl-0 = <&i2c2_default>; 1770 pinctrl-1 = <&i2c2_sleep>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 status = "disabled"; 1774 }; 1775 1776 blsp_i2c3: i2c@c177000 { 1777 compatible = "qcom,i2c-qup-v2.2.1"; 1778 reg = <0x0c177000 0x600>; 1779 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1780 1781 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1782 <&gcc GCC_BLSP1_AHB_CLK>; 1783 clock-names = "core", "iface"; 1784 clock-frequency = <400000>; 1785 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1786 dma-names = "tx", "rx"; 1787 1788 pinctrl-names = "default", "sleep"; 1789 pinctrl-0 = <&i2c3_default>; 1790 pinctrl-1 = <&i2c3_sleep>; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 status = "disabled"; 1794 }; 1795 1796 blsp_i2c4: i2c@c178000 { 1797 compatible = "qcom,i2c-qup-v2.2.1"; 1798 reg = <0x0c178000 0x600>; 1799 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1800 1801 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1802 <&gcc GCC_BLSP1_AHB_CLK>; 1803 clock-names = "core", "iface"; 1804 clock-frequency = <400000>; 1805 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1806 dma-names = "tx", "rx"; 1807 1808 pinctrl-names = "default", "sleep"; 1809 pinctrl-0 = <&i2c4_default>; 1810 pinctrl-1 = <&i2c4_sleep>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 status = "disabled"; 1814 }; 1815 1816 blsp2_dma: dma-controller@c184000 { 1817 compatible = "qcom,bam-v1.7.0"; 1818 reg = <0x0c184000 0x1f000>; 1819 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1821 clock-names = "bam_clk"; 1822 #dma-cells = <1>; 1823 qcom,ee = <0>; 1824 qcom,controlled-remotely; 1825 num-channels = <18>; 1826 qcom,num-ees = <4>; 1827 }; 1828 1829 blsp2_uart1: serial@c1af000 { 1830 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1831 reg = <0x0c1af000 0x200>; 1832 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1834 <&gcc GCC_BLSP2_AHB_CLK>; 1835 clock-names = "core", "iface"; 1836 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1837 dma-names = "tx", "rx"; 1838 pinctrl-names = "default", "sleep"; 1839 pinctrl-0 = <&blsp2_uart1_default>; 1840 pinctrl-1 = <&blsp2_uart1_sleep>; 1841 status = "disabled"; 1842 }; 1843 1844 blsp_i2c5: i2c@c1b5000 { 1845 compatible = "qcom,i2c-qup-v2.2.1"; 1846 reg = <0x0c1b5000 0x600>; 1847 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1848 1849 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1850 <&gcc GCC_BLSP2_AHB_CLK>; 1851 clock-names = "core", "iface"; 1852 clock-frequency = <400000>; 1853 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1854 dma-names = "tx", "rx"; 1855 1856 pinctrl-names = "default", "sleep"; 1857 pinctrl-0 = <&i2c5_default>; 1858 pinctrl-1 = <&i2c5_sleep>; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 status = "disabled"; 1862 }; 1863 1864 blsp_i2c6: i2c@c1b6000 { 1865 compatible = "qcom,i2c-qup-v2.2.1"; 1866 reg = <0x0c1b6000 0x600>; 1867 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1868 1869 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1870 <&gcc GCC_BLSP2_AHB_CLK>; 1871 clock-names = "core", "iface"; 1872 clock-frequency = <400000>; 1873 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1874 dma-names = "tx", "rx"; 1875 1876 pinctrl-names = "default", "sleep"; 1877 pinctrl-0 = <&i2c6_default>; 1878 pinctrl-1 = <&i2c6_sleep>; 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 status = "disabled"; 1882 }; 1883 1884 blsp_i2c7: i2c@c1b7000 { 1885 compatible = "qcom,i2c-qup-v2.2.1"; 1886 reg = <0x0c1b7000 0x600>; 1887 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1888 1889 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1890 <&gcc GCC_BLSP2_AHB_CLK>; 1891 clock-names = "core", "iface"; 1892 clock-frequency = <400000>; 1893 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1894 dma-names = "tx", "rx"; 1895 1896 pinctrl-names = "default", "sleep"; 1897 pinctrl-0 = <&i2c7_default>; 1898 pinctrl-1 = <&i2c7_sleep>; 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 status = "disabled"; 1902 }; 1903 1904 blsp_i2c8: i2c@c1b8000 { 1905 compatible = "qcom,i2c-qup-v2.2.1"; 1906 reg = <0x0c1b8000 0x600>; 1907 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1908 1909 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1910 <&gcc GCC_BLSP2_AHB_CLK>; 1911 clock-names = "core", "iface"; 1912 clock-frequency = <400000>; 1913 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1914 dma-names = "tx", "rx"; 1915 1916 pinctrl-names = "default", "sleep"; 1917 pinctrl-0 = <&i2c8_default>; 1918 pinctrl-1 = <&i2c8_sleep>; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 status = "disabled"; 1922 }; 1923 1924 sram@146bf000 { 1925 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1926 reg = <0x146bf000 0x1000>; 1927 1928 #address-cells = <1>; 1929 #size-cells = <1>; 1930 1931 ranges = <0 0x146bf000 0x1000>; 1932 1933 pil-reloc@94c { 1934 compatible = "qcom,pil-reloc-info"; 1935 reg = <0x94c 0xc8>; 1936 }; 1937 }; 1938 1939 camss: camss@ca00020 { 1940 compatible = "qcom,sdm660-camss"; 1941 reg = <0x0ca00020 0x10>, 1942 <0x0ca30000 0x100>, 1943 <0x0ca30400 0x100>, 1944 <0x0ca30800 0x100>, 1945 <0x0ca30c00 0x100>, 1946 <0x0c824000 0x1000>, 1947 <0x0ca00120 0x4>, 1948 <0x0c825000 0x1000>, 1949 <0x0ca00124 0x4>, 1950 <0x0c826000 0x1000>, 1951 <0x0ca00128 0x4>, 1952 <0x0ca31000 0x500>, 1953 <0x0ca10000 0x1000>, 1954 <0x0ca14000 0x1000>; 1955 reg-names = "csi_clk_mux", 1956 "csid0", 1957 "csid1", 1958 "csid2", 1959 "csid3", 1960 "csiphy0", 1961 "csiphy0_clk_mux", 1962 "csiphy1", 1963 "csiphy1_clk_mux", 1964 "csiphy2", 1965 "csiphy2_clk_mux", 1966 "ispif", 1967 "vfe0", 1968 "vfe1"; 1969 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1970 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1971 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1979 interrupt-names = "csid0", 1980 "csid1", 1981 "csid2", 1982 "csid3", 1983 "csiphy0", 1984 "csiphy1", 1985 "csiphy2", 1986 "ispif", 1987 "vfe0", 1988 "vfe1"; 1989 clocks = <&mmcc CAMSS_AHB_CLK>, 1990 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1991 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1992 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1993 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1994 <&mmcc CAMSS_CSI0_AHB_CLK>, 1995 <&mmcc CAMSS_CSI0_CLK>, 1996 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1997 <&mmcc CAMSS_CSI0PIX_CLK>, 1998 <&mmcc CAMSS_CSI0RDI_CLK>, 1999 <&mmcc CAMSS_CSI1_AHB_CLK>, 2000 <&mmcc CAMSS_CSI1_CLK>, 2001 <&mmcc CAMSS_CPHY_CSID1_CLK>, 2002 <&mmcc CAMSS_CSI1PIX_CLK>, 2003 <&mmcc CAMSS_CSI1RDI_CLK>, 2004 <&mmcc CAMSS_CSI2_AHB_CLK>, 2005 <&mmcc CAMSS_CSI2_CLK>, 2006 <&mmcc CAMSS_CPHY_CSID2_CLK>, 2007 <&mmcc CAMSS_CSI2PIX_CLK>, 2008 <&mmcc CAMSS_CSI2RDI_CLK>, 2009 <&mmcc CAMSS_CSI3_AHB_CLK>, 2010 <&mmcc CAMSS_CSI3_CLK>, 2011 <&mmcc CAMSS_CPHY_CSID3_CLK>, 2012 <&mmcc CAMSS_CSI3PIX_CLK>, 2013 <&mmcc CAMSS_CSI3RDI_CLK>, 2014 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2015 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2016 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2017 <&mmcc CSIPHY_AHB2CRIF_CLK>, 2018 <&mmcc CAMSS_CSI_VFE0_CLK>, 2019 <&mmcc CAMSS_CSI_VFE1_CLK>, 2020 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2021 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 2022 <&mmcc CAMSS_TOP_AHB_CLK>, 2023 <&mmcc CAMSS_VFE0_AHB_CLK>, 2024 <&mmcc CAMSS_VFE0_CLK>, 2025 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2026 <&mmcc CAMSS_VFE1_AHB_CLK>, 2027 <&mmcc CAMSS_VFE1_CLK>, 2028 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2029 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 2030 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 2031 clock-names = "ahb", 2032 "cphy_csid0", 2033 "cphy_csid1", 2034 "cphy_csid2", 2035 "cphy_csid3", 2036 "csi0_ahb", 2037 "csi0", 2038 "csi0_phy", 2039 "csi0_pix", 2040 "csi0_rdi", 2041 "csi1_ahb", 2042 "csi1", 2043 "csi1_phy", 2044 "csi1_pix", 2045 "csi1_rdi", 2046 "csi2_ahb", 2047 "csi2", 2048 "csi2_phy", 2049 "csi2_pix", 2050 "csi2_rdi", 2051 "csi3_ahb", 2052 "csi3", 2053 "csi3_phy", 2054 "csi3_pix", 2055 "csi3_rdi", 2056 "csiphy0_timer", 2057 "csiphy1_timer", 2058 "csiphy2_timer", 2059 "csiphy_ahb2crif", 2060 "csi_vfe0", 2061 "csi_vfe1", 2062 "ispif_ahb", 2063 "throttle_axi", 2064 "top_ahb", 2065 "vfe0_ahb", 2066 "vfe0", 2067 "vfe0_stream", 2068 "vfe1_ahb", 2069 "vfe1", 2070 "vfe1_stream", 2071 "vfe_ahb", 2072 "vfe_axi"; 2073 interconnects = <&mnoc 5 &bimc 5>; 2074 interconnect-names = "vfe-mem"; 2075 iommus = <&mmss_smmu 0xc00>, 2076 <&mmss_smmu 0xc01>, 2077 <&mmss_smmu 0xc02>, 2078 <&mmss_smmu 0xc03>; 2079 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2080 <&mmcc CAMSS_VFE1_GDSC>; 2081 status = "disabled"; 2082 2083 ports { 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 }; 2087 }; 2088 2089 cci: cci@ca0c000 { 2090 compatible = "qcom,msm8996-cci"; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 reg = <0x0ca0c000 0x1000>; 2094 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2095 2096 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2097 <&mmcc CAMSS_CCI_CLK>; 2098 assigned-clock-rates = <80800000>, <37500000>; 2099 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2100 <&mmcc CAMSS_CCI_AHB_CLK>, 2101 <&mmcc CAMSS_CCI_CLK>, 2102 <&mmcc CAMSS_AHB_CLK>; 2103 clock-names = "camss_top_ahb", 2104 "cci_ahb", 2105 "cci", 2106 "camss_ahb"; 2107 2108 pinctrl-names = "default"; 2109 pinctrl-0 = <&cci0_default &cci1_default>; 2110 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2111 status = "disabled"; 2112 2113 cci_i2c0: i2c-bus@0 { 2114 reg = <0>; 2115 clock-frequency = <400000>; 2116 #address-cells = <1>; 2117 #size-cells = <0>; 2118 }; 2119 2120 cci_i2c1: i2c-bus@1 { 2121 reg = <1>; 2122 clock-frequency = <400000>; 2123 #address-cells = <1>; 2124 #size-cells = <0>; 2125 }; 2126 }; 2127 2128 venus: video-codec@cc00000 { 2129 compatible = "qcom,sdm660-venus"; 2130 reg = <0x0cc00000 0xff000>; 2131 clocks = <&mmcc VIDEO_CORE_CLK>, 2132 <&mmcc VIDEO_AHB_CLK>, 2133 <&mmcc VIDEO_AXI_CLK>, 2134 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2135 clock-names = "core", "iface", "bus", "bus_throttle"; 2136 interconnects = <&gnoc 0 &mnoc 13>, 2137 <&mnoc 4 &bimc 5>; 2138 interconnect-names = "cpu-cfg", "video-mem"; 2139 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2140 iommus = <&mmss_smmu 0x400>, 2141 <&mmss_smmu 0x401>, 2142 <&mmss_smmu 0x40a>, 2143 <&mmss_smmu 0x407>, 2144 <&mmss_smmu 0x40e>, 2145 <&mmss_smmu 0x40f>, 2146 <&mmss_smmu 0x408>, 2147 <&mmss_smmu 0x409>, 2148 <&mmss_smmu 0x40b>, 2149 <&mmss_smmu 0x40c>, 2150 <&mmss_smmu 0x40d>, 2151 <&mmss_smmu 0x410>, 2152 <&mmss_smmu 0x421>, 2153 <&mmss_smmu 0x428>, 2154 <&mmss_smmu 0x429>, 2155 <&mmss_smmu 0x42b>, 2156 <&mmss_smmu 0x42c>, 2157 <&mmss_smmu 0x42d>, 2158 <&mmss_smmu 0x411>, 2159 <&mmss_smmu 0x431>; 2160 memory-region = <&venus_region>; 2161 power-domains = <&mmcc VENUS_GDSC>; 2162 status = "disabled"; 2163 2164 video-decoder { 2165 compatible = "venus-decoder"; 2166 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2167 clock-names = "vcodec0_core"; 2168 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2169 }; 2170 2171 video-encoder { 2172 compatible = "venus-encoder"; 2173 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2174 clock-names = "vcodec0_core"; 2175 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2176 }; 2177 }; 2178 2179 mmss_smmu: iommu@cd00000 { 2180 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2181 reg = <0x0cd00000 0x40000>; 2182 2183 clocks = <&mmcc MNOC_AHB_CLK>, 2184 <&mmcc BIMC_SMMU_AHB_CLK>, 2185 <&mmcc BIMC_SMMU_AXI_CLK>; 2186 clock-names = "iface-mm", "iface-smmu", 2187 "bus-smmu"; 2188 #global-interrupts = <2>; 2189 #iommu-cells = <1>; 2190 2191 interrupts = 2192 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2194 2195 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2196 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2219 2220 status = "disabled"; 2221 }; 2222 2223 adsp_pil: remoteproc@15700000 { 2224 compatible = "qcom,sdm660-adsp-pas"; 2225 reg = <0x15700000 0x4040>; 2226 2227 interrupts-extended = 2228 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2229 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2230 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2231 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2232 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2233 interrupt-names = "wdog", "fatal", "ready", 2234 "handover", "stop-ack"; 2235 2236 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2237 clock-names = "xo"; 2238 2239 memory-region = <&adsp_region>; 2240 power-domains = <&rpmpd SDM660_VDDCX>; 2241 power-domain-names = "cx"; 2242 2243 qcom,smem-states = <&adsp_smp2p_out 0>; 2244 qcom,smem-state-names = "stop"; 2245 2246 glink-edge { 2247 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2248 2249 label = "lpass"; 2250 mboxes = <&apcs_glb 9>; 2251 qcom,remote-pid = <2>; 2252 2253 apr { 2254 compatible = "qcom,apr-v2"; 2255 qcom,glink-channels = "apr_audio_svc"; 2256 qcom,domain = <APR_DOMAIN_ADSP>; 2257 #address-cells = <1>; 2258 #size-cells = <0>; 2259 2260 service@3 { 2261 reg = <APR_SVC_ADSP_CORE>; 2262 compatible = "qcom,q6core"; 2263 }; 2264 2265 q6afe: service@4 { 2266 compatible = "qcom,q6afe"; 2267 reg = <APR_SVC_AFE>; 2268 q6afedai: dais { 2269 compatible = "qcom,q6afe-dais"; 2270 #address-cells = <1>; 2271 #size-cells = <0>; 2272 #sound-dai-cells = <1>; 2273 }; 2274 }; 2275 2276 q6asm: service@7 { 2277 compatible = "qcom,q6asm"; 2278 reg = <APR_SVC_ASM>; 2279 q6asmdai: dais { 2280 compatible = "qcom,q6asm-dais"; 2281 #address-cells = <1>; 2282 #size-cells = <0>; 2283 #sound-dai-cells = <1>; 2284 iommus = <&lpass_smmu 1>; 2285 }; 2286 }; 2287 2288 q6adm: service@8 { 2289 compatible = "qcom,q6adm"; 2290 reg = <APR_SVC_ADM>; 2291 q6routing: routing { 2292 compatible = "qcom,q6adm-routing"; 2293 #sound-dai-cells = <0>; 2294 }; 2295 }; 2296 }; 2297 }; 2298 }; 2299 2300 gnoc: interconnect@17900000 { 2301 compatible = "qcom,sdm660-gnoc"; 2302 reg = <0x17900000 0xe000>; 2303 #interconnect-cells = <1>; 2304 }; 2305 2306 apcs_glb: mailbox@17911000 { 2307 compatible = "qcom,sdm660-apcs-hmss-global", 2308 "qcom,msm8994-apcs-kpss-global"; 2309 reg = <0x17911000 0x1000>; 2310 2311 #mbox-cells = <1>; 2312 }; 2313 2314 timer@17920000 { 2315 #address-cells = <1>; 2316 #size-cells = <1>; 2317 ranges; 2318 compatible = "arm,armv7-timer-mem"; 2319 reg = <0x17920000 0x1000>; 2320 clock-frequency = <19200000>; 2321 2322 frame@17921000 { 2323 frame-number = <0>; 2324 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2325 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2326 reg = <0x17921000 0x1000>, 2327 <0x17922000 0x1000>; 2328 }; 2329 2330 frame@17923000 { 2331 frame-number = <1>; 2332 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2333 reg = <0x17923000 0x1000>; 2334 status = "disabled"; 2335 }; 2336 2337 frame@17924000 { 2338 frame-number = <2>; 2339 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2340 reg = <0x17924000 0x1000>; 2341 status = "disabled"; 2342 }; 2343 2344 frame@17925000 { 2345 frame-number = <3>; 2346 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2347 reg = <0x17925000 0x1000>; 2348 status = "disabled"; 2349 }; 2350 2351 frame@17926000 { 2352 frame-number = <4>; 2353 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2354 reg = <0x17926000 0x1000>; 2355 status = "disabled"; 2356 }; 2357 2358 frame@17927000 { 2359 frame-number = <5>; 2360 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2361 reg = <0x17927000 0x1000>; 2362 status = "disabled"; 2363 }; 2364 2365 frame@17928000 { 2366 frame-number = <6>; 2367 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2368 reg = <0x17928000 0x1000>; 2369 status = "disabled"; 2370 }; 2371 }; 2372 2373 intc: interrupt-controller@17a00000 { 2374 compatible = "arm,gic-v3"; 2375 reg = <0x17a00000 0x10000>, /* GICD */ 2376 <0x17b00000 0x100000>; /* GICR * 8 */ 2377 #interrupt-cells = <3>; 2378 #address-cells = <1>; 2379 #size-cells = <1>; 2380 ranges; 2381 interrupt-controller; 2382 #redistributor-regions = <1>; 2383 redistributor-stride = <0x0 0x20000>; 2384 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2385 }; 2386 }; 2387 2388 sound: sound { 2389 }; 2390 2391 thermal-zones { 2392 aoss-thermal { 2393 polling-delay-passive = <250>; 2394 polling-delay = <1000>; 2395 2396 thermal-sensors = <&tsens 0>; 2397 2398 trips { 2399 aoss_alert0: trip-point0 { 2400 temperature = <105000>; 2401 hysteresis = <1000>; 2402 type = "hot"; 2403 }; 2404 }; 2405 }; 2406 2407 cpuss0-thermal { 2408 polling-delay-passive = <250>; 2409 polling-delay = <1000>; 2410 2411 thermal-sensors = <&tsens 1>; 2412 2413 trips { 2414 cpuss0_alert0: trip-point0 { 2415 temperature = <125000>; 2416 hysteresis = <1000>; 2417 type = "hot"; 2418 }; 2419 }; 2420 }; 2421 2422 cpuss1-thermal { 2423 polling-delay-passive = <250>; 2424 polling-delay = <1000>; 2425 2426 thermal-sensors = <&tsens 2>; 2427 2428 trips { 2429 cpuss1_alert0: trip-point0 { 2430 temperature = <125000>; 2431 hysteresis = <1000>; 2432 type = "hot"; 2433 }; 2434 }; 2435 }; 2436 2437 cpu0-thermal { 2438 polling-delay-passive = <250>; 2439 polling-delay = <1000>; 2440 2441 thermal-sensors = <&tsens 3>; 2442 2443 trips { 2444 cpu0_alert0: trip-point0 { 2445 temperature = <70000>; 2446 hysteresis = <1000>; 2447 type = "passive"; 2448 }; 2449 2450 cpu0_crit: cpu-crit { 2451 temperature = <110000>; 2452 hysteresis = <1000>; 2453 type = "critical"; 2454 }; 2455 }; 2456 }; 2457 2458 cpu1-thermal { 2459 polling-delay-passive = <250>; 2460 polling-delay = <1000>; 2461 2462 thermal-sensors = <&tsens 4>; 2463 2464 trips { 2465 cpu1_alert0: trip-point0 { 2466 temperature = <70000>; 2467 hysteresis = <1000>; 2468 type = "passive"; 2469 }; 2470 2471 cpu1_crit: cpu-crit { 2472 temperature = <110000>; 2473 hysteresis = <1000>; 2474 type = "critical"; 2475 }; 2476 }; 2477 }; 2478 2479 cpu2-thermal { 2480 polling-delay-passive = <250>; 2481 polling-delay = <1000>; 2482 2483 thermal-sensors = <&tsens 5>; 2484 2485 trips { 2486 cpu2_alert0: trip-point0 { 2487 temperature = <70000>; 2488 hysteresis = <1000>; 2489 type = "passive"; 2490 }; 2491 2492 cpu2_crit: cpu-crit { 2493 temperature = <110000>; 2494 hysteresis = <1000>; 2495 type = "critical"; 2496 }; 2497 }; 2498 }; 2499 2500 cpu3-thermal { 2501 polling-delay-passive = <250>; 2502 polling-delay = <1000>; 2503 2504 thermal-sensors = <&tsens 6>; 2505 2506 trips { 2507 cpu3_alert0: trip-point0 { 2508 temperature = <70000>; 2509 hysteresis = <1000>; 2510 type = "passive"; 2511 }; 2512 2513 cpu3_crit: cpu-crit { 2514 temperature = <110000>; 2515 hysteresis = <1000>; 2516 type = "critical"; 2517 }; 2518 }; 2519 }; 2520 2521 /* 2522 * According to what downstream DTS says, 2523 * the entire power efficient cluster has 2524 * only a single thermal sensor. 2525 */ 2526 2527 pwr-cluster-thermal { 2528 polling-delay-passive = <250>; 2529 polling-delay = <1000>; 2530 2531 thermal-sensors = <&tsens 7>; 2532 2533 trips { 2534 pwr_cluster_alert0: trip-point0 { 2535 temperature = <70000>; 2536 hysteresis = <1000>; 2537 type = "passive"; 2538 }; 2539 2540 pwr_cluster_crit: cpu-crit { 2541 temperature = <110000>; 2542 hysteresis = <1000>; 2543 type = "critical"; 2544 }; 2545 }; 2546 }; 2547 2548 gpu-thermal { 2549 polling-delay-passive = <250>; 2550 polling-delay = <1000>; 2551 2552 thermal-sensors = <&tsens 8>; 2553 2554 trips { 2555 gpu_alert0: trip-point0 { 2556 temperature = <90000>; 2557 hysteresis = <1000>; 2558 type = "hot"; 2559 }; 2560 }; 2561 }; 2562 }; 2563 2564 timer { 2565 compatible = "arm,armv8-timer"; 2566 interrupts = <GIC_PPI 1 0xf08>, 2567 <GIC_PPI 2 0xf08>, 2568 <GIC_PPI 3 0xf08>, 2569 <GIC_PPI 0 0xf08>; 2570 }; 2571}; 2572 2573