1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 capacity-dmips-mhz = <1024>; 46 dynamic-power-coefficient = <100>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 power-domains = <&CPU_PD0>; 51 power-domain-names = "psci"; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 }; 57 }; 58 59 CPU1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "qcom,kryo260"; 62 reg = <0x0 0x1>; 63 clocks = <&cpufreq_hw 0>; 64 capacity-dmips-mhz = <1024>; 65 dynamic-power-coefficient = <100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 power-domains = <&CPU_PD1>; 70 power-domain-names = "psci"; 71 }; 72 73 CPU2: cpu@2 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo260"; 76 reg = <0x0 0x2>; 77 clocks = <&cpufreq_hw 0>; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 power-domains = <&CPU_PD2>; 84 power-domain-names = "psci"; 85 }; 86 87 CPU3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "qcom,kryo260"; 90 reg = <0x0 0x3>; 91 clocks = <&cpufreq_hw 0>; 92 capacity-dmips-mhz = <1024>; 93 dynamic-power-coefficient = <100>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_0>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 power-domains = <&CPU_PD3>; 98 power-domain-names = "psci"; 99 }; 100 101 CPU4: cpu@100 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x100>; 105 clocks = <&cpufreq_hw 1>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1638>; 108 dynamic-power-coefficient = <282>; 109 next-level-cache = <&L2_1>; 110 qcom,freq-domain = <&cpufreq_hw 1>; 111 power-domains = <&CPU_PD4>; 112 power-domain-names = "psci"; 113 L2_1: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 }; 118 }; 119 120 CPU5: cpu@101 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo260"; 123 reg = <0x0 0x101>; 124 clocks = <&cpufreq_hw 1>; 125 capacity-dmips-mhz = <1638>; 126 dynamic-power-coefficient = <282>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_1>; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 power-domains = <&CPU_PD5>; 131 power-domain-names = "psci"; 132 }; 133 134 CPU6: cpu@102 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo260"; 137 reg = <0x0 0x102>; 138 clocks = <&cpufreq_hw 1>; 139 capacity-dmips-mhz = <1638>; 140 dynamic-power-coefficient = <282>; 141 enable-method = "psci"; 142 next-level-cache = <&L2_1>; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 power-domains = <&CPU_PD6>; 145 power-domain-names = "psci"; 146 }; 147 148 CPU7: cpu@103 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo260"; 151 reg = <0x0 0x103>; 152 clocks = <&cpufreq_hw 1>; 153 capacity-dmips-mhz = <1638>; 154 dynamic-power-coefficient = <282>; 155 enable-method = "psci"; 156 next-level-cache = <&L2_1>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 power-domains = <&CPU_PD7>; 159 power-domain-names = "psci"; 160 }; 161 162 cpu-map { 163 cluster0 { 164 core0 { 165 cpu = <&CPU0>; 166 }; 167 168 core1 { 169 cpu = <&CPU1>; 170 }; 171 172 core2 { 173 cpu = <&CPU2>; 174 }; 175 176 core3 { 177 cpu = <&CPU3>; 178 }; 179 }; 180 181 cluster1 { 182 core0 { 183 cpu = <&CPU4>; 184 }; 185 186 core1 { 187 cpu = <&CPU5>; 188 }; 189 190 core2 { 191 cpu = <&CPU6>; 192 }; 193 194 core3 { 195 cpu = <&CPU7>; 196 }; 197 }; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 204 compatible = "arm,idle-state"; 205 idle-state-name = "silver-rail-power-collapse"; 206 arm,psci-suspend-param = <0x40000003>; 207 entry-latency-us = <290>; 208 exit-latency-us = <376>; 209 min-residency-us = <1182>; 210 local-timer-stop; 211 }; 212 213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 214 compatible = "arm,idle-state"; 215 idle-state-name = "gold-rail-power-collapse"; 216 arm,psci-suspend-param = <0x40000003>; 217 entry-latency-us = <297>; 218 exit-latency-us = <324>; 219 min-residency-us = <1110>; 220 local-timer-stop; 221 }; 222 }; 223 224 domain-idle-states { 225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { 226 /* GDHS */ 227 compatible = "domain-idle-state"; 228 arm,psci-suspend-param = <0x40000022>; 229 entry-latency-us = <360>; 230 exit-latency-us = <421>; 231 min-residency-us = <782>; 232 }; 233 234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { 235 /* Power Collapse */ 236 compatible = "domain-idle-state"; 237 arm,psci-suspend-param = <0x41000044>; 238 entry-latency-us = <800>; 239 exit-latency-us = <2118>; 240 min-residency-us = <7376>; 241 }; 242 243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { 244 /* GDHS */ 245 compatible = "domain-idle-state"; 246 arm,psci-suspend-param = <0x40000042>; 247 entry-latency-us = <314>; 248 exit-latency-us = <345>; 249 min-residency-us = <660>; 250 }; 251 252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { 253 /* Power Collapse */ 254 compatible = "domain-idle-state"; 255 arm,psci-suspend-param = <0x41000044>; 256 entry-latency-us = <640>; 257 exit-latency-us = <1654>; 258 min-residency-us = <8094>; 259 }; 260 }; 261 }; 262 263 firmware { 264 scm: scm { 265 compatible = "qcom,scm-sm6115", "qcom,scm"; 266 #reset-cells = <1>; 267 }; 268 }; 269 270 memory@80000000 { 271 device_type = "memory"; 272 /* We expect the bootloader to fill in the size */ 273 reg = <0 0x80000000 0 0>; 274 }; 275 276 pmu { 277 compatible = "arm,armv8-pmuv3"; 278 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 psci { 282 compatible = "arm,psci-1.0"; 283 method = "smc"; 284 285 CPU_PD0: power-domain-cpu0 { 286 #power-domain-cells = <0>; 287 power-domains = <&CLUSTER_0_PD>; 288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 289 }; 290 291 CPU_PD1: power-domain-cpu1 { 292 #power-domain-cells = <0>; 293 power-domains = <&CLUSTER_0_PD>; 294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 295 }; 296 297 CPU_PD2: power-domain-cpu2 { 298 #power-domain-cells = <0>; 299 power-domains = <&CLUSTER_0_PD>; 300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 301 }; 302 303 CPU_PD3: power-domain-cpu3 { 304 #power-domain-cells = <0>; 305 power-domains = <&CLUSTER_0_PD>; 306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 307 }; 308 309 CPU_PD4: power-domain-cpu4 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_1_PD>; 312 domain-idle-states = <&BIG_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD5: power-domain-cpu5 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_1_PD>; 318 domain-idle-states = <&BIG_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD6: power-domain-cpu6 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_1_PD>; 324 domain-idle-states = <&BIG_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD7: power-domain-cpu7 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_1_PD>; 330 domain-idle-states = <&BIG_CPU_SLEEP_0>; 331 }; 332 333 CLUSTER_0_PD: power-domain-cpu-cluster0 { 334 #power-domain-cells = <0>; 335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; 336 }; 337 338 CLUSTER_1_PD: power-domain-cpu-cluster1 { 339 #power-domain-cells = <0>; 340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; 341 }; 342 }; 343 344 rpm: remoteproc { 345 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 346 347 glink-edge { 348 compatible = "qcom,glink-rpm"; 349 350 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 351 qcom,rpm-msg-ram = <&rpm_msg_ram>; 352 mboxes = <&apcs_glb 0>; 353 354 rpm_requests: rpm-requests { 355 compatible = "qcom,rpm-sm6115"; 356 qcom,glink-channels = "rpm_requests"; 357 358 rpmcc: clock-controller { 359 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 360 clocks = <&xo_board>; 361 clock-names = "xo"; 362 #clock-cells = <1>; 363 }; 364 365 rpmpd: power-controller { 366 compatible = "qcom,sm6115-rpmpd"; 367 #power-domain-cells = <1>; 368 operating-points-v2 = <&rpmpd_opp_table>; 369 370 rpmpd_opp_table: opp-table { 371 compatible = "operating-points-v2"; 372 373 rpmpd_opp_min_svs: opp1 { 374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 375 }; 376 377 rpmpd_opp_low_svs: opp2 { 378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 379 }; 380 381 rpmpd_opp_svs: opp3 { 382 opp-level = <RPM_SMD_LEVEL_SVS>; 383 }; 384 385 rpmpd_opp_svs_plus: opp4 { 386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 387 }; 388 389 rpmpd_opp_nom: opp5 { 390 opp-level = <RPM_SMD_LEVEL_NOM>; 391 }; 392 393 rpmpd_opp_nom_plus: opp6 { 394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 395 }; 396 397 rpmpd_opp_turbo: opp7 { 398 opp-level = <RPM_SMD_LEVEL_TURBO>; 399 }; 400 401 rpmpd_opp_turbo_plus: opp8 { 402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 403 }; 404 }; 405 }; 406 }; 407 }; 408 }; 409 410 reserved_memory: reserved-memory { 411 #address-cells = <2>; 412 #size-cells = <2>; 413 ranges; 414 415 hyp_mem: memory@45700000 { 416 reg = <0x0 0x45700000 0x0 0x600000>; 417 no-map; 418 }; 419 420 xbl_aop_mem: memory@45e00000 { 421 reg = <0x0 0x45e00000 0x0 0x140000>; 422 no-map; 423 }; 424 425 sec_apps_mem: memory@45fff000 { 426 reg = <0x0 0x45fff000 0x0 0x1000>; 427 no-map; 428 }; 429 430 smem_mem: memory@46000000 { 431 compatible = "qcom,smem"; 432 reg = <0x0 0x46000000 0x0 0x200000>; 433 no-map; 434 435 hwlocks = <&tcsr_mutex 3>; 436 qcom,rpm-msg-ram = <&rpm_msg_ram>; 437 }; 438 439 cdsp_sec_mem: memory@46200000 { 440 reg = <0x0 0x46200000 0x0 0x1e00000>; 441 no-map; 442 }; 443 444 pil_modem_mem: memory@4ab00000 { 445 reg = <0x0 0x4ab00000 0x0 0x6900000>; 446 no-map; 447 }; 448 449 pil_video_mem: memory@51400000 { 450 reg = <0x0 0x51400000 0x0 0x500000>; 451 no-map; 452 }; 453 454 wlan_msa_mem: memory@51900000 { 455 reg = <0x0 0x51900000 0x0 0x100000>; 456 no-map; 457 }; 458 459 pil_cdsp_mem: memory@51a00000 { 460 reg = <0x0 0x51a00000 0x0 0x1e00000>; 461 no-map; 462 }; 463 464 pil_adsp_mem: memory@53800000 { 465 reg = <0x0 0x53800000 0x0 0x2800000>; 466 no-map; 467 }; 468 469 pil_ipa_fw_mem: memory@56100000 { 470 reg = <0x0 0x56100000 0x0 0x10000>; 471 no-map; 472 }; 473 474 pil_ipa_gsi_mem: memory@56110000 { 475 reg = <0x0 0x56110000 0x0 0x5000>; 476 no-map; 477 }; 478 479 pil_gpu_mem: memory@56115000 { 480 reg = <0x0 0x56115000 0x0 0x2000>; 481 no-map; 482 }; 483 484 cont_splash_memory: memory@5c000000 { 485 reg = <0x0 0x5c000000 0x0 0x00f00000>; 486 no-map; 487 }; 488 489 dfps_data_memory: memory@5cf00000 { 490 reg = <0x0 0x5cf00000 0x0 0x0100000>; 491 no-map; 492 }; 493 494 removed_mem: memory@60000000 { 495 reg = <0x0 0x60000000 0x0 0x3900000>; 496 no-map; 497 }; 498 499 rmtfs_mem: memory@89b01000 { 500 compatible = "qcom,rmtfs-mem"; 501 reg = <0x0 0x89b01000 0x0 0x200000>; 502 no-map; 503 504 qcom,client-id = <1>; 505 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 506 }; 507 }; 508 509 smp2p-adsp { 510 compatible = "qcom,smp2p"; 511 qcom,smem = <443>, <429>; 512 513 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 514 515 mboxes = <&apcs_glb 10>; 516 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <2>; 519 520 adsp_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 adsp_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 }; 531 }; 532 533 smp2p-cdsp { 534 compatible = "qcom,smp2p"; 535 qcom,smem = <94>, <432>; 536 537 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 538 539 mboxes = <&apcs_glb 30>; 540 541 qcom,local-pid = <0>; 542 qcom,remote-pid = <5>; 543 544 cdsp_smp2p_out: master-kernel { 545 qcom,entry-name = "master-kernel"; 546 #qcom,smem-state-cells = <1>; 547 }; 548 549 cdsp_smp2p_in: slave-kernel { 550 qcom,entry-name = "slave-kernel"; 551 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 }; 556 557 smp2p-mpss { 558 compatible = "qcom,smp2p"; 559 qcom,smem = <435>, <428>; 560 561 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 562 563 mboxes = <&apcs_glb 14>; 564 565 qcom,local-pid = <0>; 566 qcom,remote-pid = <1>; 567 568 modem_smp2p_out: master-kernel { 569 qcom,entry-name = "master-kernel"; 570 #qcom,smem-state-cells = <1>; 571 }; 572 573 modem_smp2p_in: slave-kernel { 574 qcom,entry-name = "slave-kernel"; 575 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 }; 580 581 soc: soc@0 { 582 compatible = "simple-bus"; 583 #address-cells = <2>; 584 #size-cells = <2>; 585 ranges = <0 0 0 0 0x10 0>; 586 dma-ranges = <0 0 0 0 0x10 0>; 587 588 tcsr_mutex: hwlock@340000 { 589 compatible = "qcom,tcsr-mutex"; 590 reg = <0x0 0x00340000 0x0 0x20000>; 591 #hwlock-cells = <1>; 592 }; 593 594 tlmm: pinctrl@500000 { 595 compatible = "qcom,sm6115-tlmm"; 596 reg = <0x0 0x00500000 0x0 0x400000>, 597 <0x0 0x00900000 0x0 0x400000>, 598 <0x0 0x00d00000 0x0 0x400000>; 599 reg-names = "west", "south", "east"; 600 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 601 gpio-controller; 602 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 603 #gpio-cells = <2>; 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 607 qup_i2c0_default: qup-i2c0-default-state { 608 pins = "gpio0", "gpio1"; 609 function = "qup0"; 610 drive-strength = <2>; 611 bias-pull-up; 612 }; 613 614 qup_i2c1_default: qup-i2c1-default-state { 615 pins = "gpio4", "gpio5"; 616 function = "qup1"; 617 drive-strength = <2>; 618 bias-pull-up; 619 }; 620 621 qup_i2c2_default: qup-i2c2-default-state { 622 pins = "gpio6", "gpio7"; 623 function = "qup2"; 624 drive-strength = <2>; 625 bias-pull-up; 626 }; 627 628 qup_i2c3_default: qup-i2c3-default-state { 629 pins = "gpio8", "gpio9"; 630 function = "qup3"; 631 drive-strength = <2>; 632 bias-pull-up; 633 }; 634 635 qup_i2c4_default: qup-i2c4-default-state { 636 pins = "gpio12", "gpio13"; 637 function = "qup4"; 638 drive-strength = <2>; 639 bias-pull-up; 640 }; 641 642 qup_i2c5_default: qup-i2c5-default-state { 643 pins = "gpio14", "gpio15"; 644 function = "qup5"; 645 drive-strength = <2>; 646 bias-pull-up; 647 }; 648 649 qup_spi0_default: qup-spi0-default-state { 650 pins = "gpio0", "gpio1","gpio2", "gpio3"; 651 function = "qup0"; 652 drive-strength = <2>; 653 bias-pull-up; 654 }; 655 656 qup_spi1_default: qup-spi1-default-state { 657 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 658 function = "qup1"; 659 drive-strength = <2>; 660 bias-pull-up; 661 }; 662 663 qup_spi2_default: qup-spi2-default-state { 664 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 665 function = "qup2"; 666 drive-strength = <2>; 667 bias-pull-up; 668 }; 669 670 qup_spi3_default: qup-spi3-default-state { 671 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 672 function = "qup3"; 673 drive-strength = <2>; 674 bias-pull-up; 675 }; 676 677 qup_spi4_default: qup-spi4-default-state { 678 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 679 function = "qup4"; 680 drive-strength = <2>; 681 bias-pull-up; 682 }; 683 684 qup_spi5_default: qup-spi5-default-state { 685 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 686 function = "qup5"; 687 drive-strength = <2>; 688 bias-pull-up; 689 }; 690 691 sdc1_state_on: sdc1-on-state { 692 clk-pins { 693 pins = "sdc1_clk"; 694 bias-disable; 695 drive-strength = <16>; 696 }; 697 698 cmd-pins { 699 pins = "sdc1_cmd"; 700 bias-pull-up; 701 drive-strength = <10>; 702 }; 703 704 data-pins { 705 pins = "sdc1_data"; 706 bias-pull-up; 707 drive-strength = <10>; 708 }; 709 710 rclk-pins { 711 pins = "sdc1_rclk"; 712 bias-pull-down; 713 }; 714 }; 715 716 sdc1_state_off: sdc1-off-state { 717 clk-pins { 718 pins = "sdc1_clk"; 719 bias-disable; 720 drive-strength = <2>; 721 }; 722 723 cmd-pins { 724 pins = "sdc1_cmd"; 725 bias-pull-up; 726 drive-strength = <2>; 727 }; 728 729 data-pins { 730 pins = "sdc1_data"; 731 bias-pull-up; 732 drive-strength = <2>; 733 }; 734 735 rclk-pins { 736 pins = "sdc1_rclk"; 737 bias-pull-down; 738 }; 739 }; 740 741 sdc2_state_on: sdc2-on-state { 742 clk-pins { 743 pins = "sdc2_clk"; 744 bias-disable; 745 drive-strength = <16>; 746 }; 747 748 cmd-pins { 749 pins = "sdc2_cmd"; 750 bias-pull-up; 751 drive-strength = <10>; 752 }; 753 754 data-pins { 755 pins = "sdc2_data"; 756 bias-pull-up; 757 drive-strength = <10>; 758 }; 759 }; 760 761 sdc2_state_off: sdc2-off-state { 762 clk-pins { 763 pins = "sdc2_clk"; 764 bias-disable; 765 drive-strength = <2>; 766 }; 767 768 cmd-pins { 769 pins = "sdc2_cmd"; 770 bias-pull-up; 771 drive-strength = <2>; 772 }; 773 774 data-pins { 775 pins = "sdc2_data"; 776 bias-pull-up; 777 drive-strength = <2>; 778 }; 779 }; 780 }; 781 782 gcc: clock-controller@1400000 { 783 compatible = "qcom,gcc-sm6115"; 784 reg = <0x0 0x01400000 0x0 0x1f0000>; 785 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 786 clock-names = "bi_tcxo", "sleep_clk"; 787 #clock-cells = <1>; 788 #reset-cells = <1>; 789 #power-domain-cells = <1>; 790 }; 791 792 usb_hsphy: phy@1613000 { 793 compatible = "qcom,sm6115-qusb2-phy"; 794 reg = <0x0 0x01613000 0x0 0x180>; 795 #phy-cells = <0>; 796 797 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 798 clock-names = "cfg_ahb", "ref"; 799 800 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 801 nvmem-cells = <&qusb2_hstx_trim>; 802 803 status = "disabled"; 804 }; 805 806 cryptobam: dma-controller@1b04000 { 807 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 808 reg = <0x0 0x01b04000 0x0 0x24000>; 809 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 811 clock-names = "bam_clk"; 812 #dma-cells = <1>; 813 qcom,ee = <0>; 814 qcom,controlled-remotely; 815 iommus = <&apps_smmu 0x92 0>, 816 <&apps_smmu 0x94 0x11>, 817 <&apps_smmu 0x96 0x11>, 818 <&apps_smmu 0x98 0x1>, 819 <&apps_smmu 0x9F 0>; 820 }; 821 822 crypto: crypto@1b3a000 { 823 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 824 reg = <0x0 0x01b3a000 0x0 0x6000>; 825 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 826 clock-names = "core"; 827 828 dmas = <&cryptobam 6>, <&cryptobam 7>; 829 dma-names = "rx", "tx"; 830 iommus = <&apps_smmu 0x92 0>, 831 <&apps_smmu 0x94 0x11>, 832 <&apps_smmu 0x96 0x11>, 833 <&apps_smmu 0x98 0x1>, 834 <&apps_smmu 0x9F 0>; 835 }; 836 837 usb_qmpphy: phy@1615000 { 838 compatible = "qcom,sm6115-qmp-usb3-phy"; 839 reg = <0x0 0x01615000 0x0 0x1000>; 840 841 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 842 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 843 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 844 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 845 clock-names = "cfg_ahb", 846 "ref", 847 "com_aux", 848 "pipe"; 849 850 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 851 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 852 reset-names = "phy", "phy_phy"; 853 854 #clock-cells = <0>; 855 clock-output-names = "usb3_phy_pipe_clk_src"; 856 857 #phy-cells = <0>; 858 859 status = "disabled"; 860 }; 861 862 qfprom@1b40000 { 863 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 864 reg = <0x0 0x01b40000 0x0 0x7000>; 865 #address-cells = <1>; 866 #size-cells = <1>; 867 868 qusb2_hstx_trim: hstx-trim@25b { 869 reg = <0x25b 0x1>; 870 bits = <1 4>; 871 }; 872 873 gpu_speed_bin: gpu-speed-bin@6006 { 874 reg = <0x6006 0x2>; 875 bits = <5 8>; 876 }; 877 }; 878 879 rng: rng@1b53000 { 880 compatible = "qcom,prng-ee"; 881 reg = <0x0 0x01b53000 0x0 0x1000>; 882 clocks = <&gcc GCC_PRNG_AHB_CLK>; 883 clock-names = "core"; 884 }; 885 886 spmi_bus: spmi@1c40000 { 887 compatible = "qcom,spmi-pmic-arb"; 888 reg = <0x0 0x01c40000 0x0 0x1100>, 889 <0x0 0x01e00000 0x0 0x2000000>, 890 <0x0 0x03e00000 0x0 0x100000>, 891 <0x0 0x03f00000 0x0 0xa0000>, 892 <0x0 0x01c0a000 0x0 0x26000>; 893 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 894 interrupt-names = "periph_irq"; 895 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 896 qcom,ee = <0>; 897 qcom,channel = <0>; 898 #address-cells = <2>; 899 #size-cells = <0>; 900 interrupt-controller; 901 #interrupt-cells = <4>; 902 }; 903 904 tsens0: thermal-sensor@4411000 { 905 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 906 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 907 <0x0 0x04410000 0x0 0x8>; /* SROT */ 908 #qcom,sensors = <16>; 909 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 911 interrupt-names = "uplow", "critical"; 912 #thermal-sensor-cells = <1>; 913 }; 914 915 rpm_msg_ram: sram@45f0000 { 916 compatible = "qcom,rpm-msg-ram"; 917 reg = <0x0 0x045f0000 0x0 0x7000>; 918 }; 919 920 sram@4690000 { 921 compatible = "qcom,rpm-stats"; 922 reg = <0x0 0x04690000 0x0 0x10000>; 923 }; 924 925 sdhc_1: mmc@4744000 { 926 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 927 reg = <0x0 0x04744000 0x0 0x1000>, 928 <0x0 0x04745000 0x0 0x1000>, 929 <0x0 0x04748000 0x0 0x8000>; 930 reg-names = "hc", "cqhci", "ice"; 931 932 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "hc_irq", "pwr_irq"; 935 936 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 937 <&gcc GCC_SDCC1_APPS_CLK>, 938 <&rpmcc RPM_SMD_XO_CLK_SRC>, 939 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 940 clock-names = "iface", "core", "xo", "ice"; 941 942 bus-width = <8>; 943 status = "disabled"; 944 }; 945 946 sdhc_2: mmc@4784000 { 947 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 948 reg = <0x0 0x04784000 0x0 0x1000>; 949 reg-names = "hc"; 950 951 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "hc_irq", "pwr_irq"; 954 955 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 956 <&gcc GCC_SDCC2_APPS_CLK>, 957 <&rpmcc RPM_SMD_XO_CLK_SRC>; 958 clock-names = "iface", "core", "xo"; 959 960 power-domains = <&rpmpd SM6115_VDDCX>; 961 operating-points-v2 = <&sdhc2_opp_table>; 962 iommus = <&apps_smmu 0x00a0 0x0>; 963 resets = <&gcc GCC_SDCC2_BCR>; 964 965 bus-width = <4>; 966 qcom,dll-config = <0x0007642c>; 967 qcom,ddr-config = <0x80040868>; 968 status = "disabled"; 969 970 sdhc2_opp_table: opp-table { 971 compatible = "operating-points-v2"; 972 973 opp-100000000 { 974 opp-hz = /bits/ 64 <100000000>; 975 required-opps = <&rpmpd_opp_low_svs>; 976 }; 977 978 opp-202000000 { 979 opp-hz = /bits/ 64 <202000000>; 980 required-opps = <&rpmpd_opp_nom>; 981 }; 982 }; 983 }; 984 985 ufs_mem_hc: ufs@4804000 { 986 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 987 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 988 reg-names = "std", "ice"; 989 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 990 phys = <&ufs_mem_phy_lanes>; 991 phy-names = "ufsphy"; 992 lanes-per-direction = <1>; 993 #reset-cells = <1>; 994 resets = <&gcc GCC_UFS_PHY_BCR>; 995 reset-names = "rst"; 996 997 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 998 iommus = <&apps_smmu 0x100 0>; 999 1000 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1001 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1002 <&gcc GCC_UFS_PHY_AHB_CLK>, 1003 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1004 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1005 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1006 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1007 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1008 clock-names = "core_clk", 1009 "bus_aggr_clk", 1010 "iface_clk", 1011 "core_clk_unipro", 1012 "ref_clk", 1013 "tx_lane0_sync_clk", 1014 "rx_lane0_sync_clk", 1015 "ice_core_clk"; 1016 1017 freq-table-hz = <50000000 200000000>, 1018 <0 0>, 1019 <0 0>, 1020 <37500000 150000000>, 1021 <0 0>, 1022 <0 0>, 1023 <0 0>, 1024 <75000000 300000000>; 1025 1026 status = "disabled"; 1027 }; 1028 1029 ufs_mem_phy: phy@4807000 { 1030 compatible = "qcom,sm6115-qmp-ufs-phy"; 1031 reg = <0x0 0x04807000 0x0 0x1c4>; 1032 #address-cells = <2>; 1033 #size-cells = <2>; 1034 ranges; 1035 1036 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1037 clock-names = "ref", "ref_aux"; 1038 1039 resets = <&ufs_mem_hc 0>; 1040 reset-names = "ufsphy"; 1041 status = "disabled"; 1042 1043 ufs_mem_phy_lanes: phy@4807400 { 1044 reg = <0x0 0x04807400 0x0 0x098>, 1045 <0x0 0x04807600 0x0 0x130>, 1046 <0x0 0x04807c00 0x0 0x16c>; 1047 #phy-cells = <0>; 1048 }; 1049 }; 1050 1051 gpi_dma0: dma-controller@4a00000 { 1052 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1053 reg = <0x0 0x04a00000 0x0 0x60000>; 1054 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1064 dma-channels = <10>; 1065 dma-channel-mask = <0xf>; 1066 iommus = <&apps_smmu 0xf6 0x0>; 1067 #dma-cells = <3>; 1068 status = "disabled"; 1069 }; 1070 1071 qupv3_id_0: geniqup@4ac0000 { 1072 compatible = "qcom,geni-se-qup"; 1073 reg = <0x0 0x04ac0000 0x0 0x2000>; 1074 clock-names = "m-ahb", "s-ahb"; 1075 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1076 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1077 #address-cells = <2>; 1078 #size-cells = <2>; 1079 iommus = <&apps_smmu 0xe3 0x0>; 1080 ranges; 1081 status = "disabled"; 1082 1083 i2c0: i2c@4a80000 { 1084 compatible = "qcom,geni-i2c"; 1085 reg = <0x0 0x04a80000 0x0 0x4000>; 1086 clock-names = "se"; 1087 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_i2c0_default>; 1090 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1091 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1092 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1093 dma-names = "tx", "rx"; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 spi0: spi@4a80000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0x0 0x04a80000 0x0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_spi0_default>; 1106 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1107 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1108 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1109 dma-names = "tx", "rx"; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 i2c1: i2c@4a84000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0x0 0x04a84000 0x0 0x4000>; 1118 clock-names = "se"; 1119 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&qup_i2c1_default>; 1122 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1123 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1124 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1125 dma-names = "tx", "rx"; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 status = "disabled"; 1129 }; 1130 1131 spi1: spi@4a84000 { 1132 compatible = "qcom,geni-spi"; 1133 reg = <0x0 0x04a84000 0x0 0x4000>; 1134 clock-names = "se"; 1135 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&qup_spi1_default>; 1138 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1139 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1140 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1141 dma-names = "tx", "rx"; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 i2c2: i2c@4a88000 { 1148 compatible = "qcom,geni-i2c"; 1149 reg = <0x0 0x04a88000 0x0 0x4000>; 1150 clock-names = "se"; 1151 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_i2c2_default>; 1154 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1155 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1156 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1157 dma-names = "tx", "rx"; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 spi2: spi@4a88000 { 1164 compatible = "qcom,geni-spi"; 1165 reg = <0x0 0x04a88000 0x0 0x4000>; 1166 clock-names = "se"; 1167 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_spi2_default>; 1170 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1171 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1172 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1173 dma-names = "tx", "rx"; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 status = "disabled"; 1177 }; 1178 1179 i2c3: i2c@4a8c000 { 1180 compatible = "qcom,geni-i2c"; 1181 reg = <0x0 0x04a8c000 0x0 0x4000>; 1182 clock-names = "se"; 1183 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&qup_i2c3_default>; 1186 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1187 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1188 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1189 dma-names = "tx", "rx"; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 spi3: spi@4a8c000 { 1196 compatible = "qcom,geni-spi"; 1197 reg = <0x0 0x04a8c000 0x0 0x4000>; 1198 clock-names = "se"; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_spi3_default>; 1202 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1203 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1204 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1205 dma-names = "tx", "rx"; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c4: i2c@4a90000 { 1212 compatible = "qcom,geni-i2c"; 1213 reg = <0x0 0x04a90000 0x0 0x4000>; 1214 clock-names = "se"; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_i2c4_default>; 1218 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1219 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1220 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1221 dma-names = "tx", "rx"; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 1227 spi4: spi@4a90000 { 1228 compatible = "qcom,geni-spi"; 1229 reg = <0x0 0x04a90000 0x0 0x4000>; 1230 clock-names = "se"; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_spi4_default>; 1234 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1235 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1236 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1237 dma-names = "tx", "rx"; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 status = "disabled"; 1241 }; 1242 1243 uart4: serial@4a90000 { 1244 compatible = "qcom,geni-debug-uart"; 1245 reg = <0x0 0x04a90000 0x0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1248 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1249 status = "disabled"; 1250 }; 1251 1252 i2c5: i2c@4a94000 { 1253 compatible = "qcom,geni-i2c"; 1254 reg = <0x0 0x04a94000 0x0 0x4000>; 1255 clock-names = "se"; 1256 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&qup_i2c5_default>; 1259 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1260 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1261 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 status = "disabled"; 1266 }; 1267 1268 spi5: spi@4a94000 { 1269 compatible = "qcom,geni-spi"; 1270 reg = <0x0 0x04a94000 0x0 0x4000>; 1271 clock-names = "se"; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_spi5_default>; 1275 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1276 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1277 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1278 dma-names = "tx", "rx"; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 }; 1284 1285 usb: usb@4ef8800 { 1286 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1287 reg = <0x0 0x04ef8800 0x0 0x400>; 1288 #address-cells = <2>; 1289 #size-cells = <2>; 1290 ranges; 1291 1292 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1293 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1294 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1295 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1296 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1297 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1298 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1299 1300 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1301 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1302 assigned-clock-rates = <19200000>, <66666667>; 1303 1304 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1306 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1307 1308 resets = <&gcc GCC_USB30_PRIM_BCR>; 1309 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1310 qcom,select-utmi-as-pipe-clk; 1311 status = "disabled"; 1312 1313 usb_dwc3: usb@4e00000 { 1314 compatible = "snps,dwc3"; 1315 reg = <0x0 0x04e00000 0x0 0xcd00>; 1316 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1317 phys = <&usb_hsphy>, <&usb_qmpphy>; 1318 phy-names = "usb2-phy", "usb3-phy"; 1319 iommus = <&apps_smmu 0x120 0x0>; 1320 snps,dis_u2_susphy_quirk; 1321 snps,dis_enblslpm_quirk; 1322 snps,has-lpm-erratum; 1323 snps,hird-threshold = /bits/ 8 <0x10>; 1324 snps,usb3_lpm_capable; 1325 }; 1326 }; 1327 1328 gpu: gpu@5900000 { 1329 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1330 reg = <0x0 0x05900000 0x0 0x40000>; 1331 reg-names = "kgsl_3d0_reg_memory"; 1332 1333 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1334 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1335 <&gpucc GPU_CC_AHB_CLK>, 1336 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1337 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1338 <&gpucc GPU_CC_CX_GMU_CLK>, 1339 <&gpucc GPU_CC_CXO_CLK>; 1340 clock-names = "core", 1341 "iface", 1342 "mem_iface", 1343 "alt_mem_iface", 1344 "gmu", 1345 "xo"; 1346 1347 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1348 1349 iommus = <&adreno_smmu 0 1>; 1350 operating-points-v2 = <&gpu_opp_table>; 1351 power-domains = <&rpmpd SM6115_VDDCX>; 1352 qcom,gmu = <&gmu_wrapper>; 1353 1354 nvmem-cells = <&gpu_speed_bin>; 1355 nvmem-cell-names = "speed_bin"; 1356 1357 status = "disabled"; 1358 1359 zap-shader { 1360 memory-region = <&pil_gpu_mem>; 1361 }; 1362 1363 gpu_opp_table: opp-table { 1364 compatible = "operating-points-v2"; 1365 1366 opp-320000000 { 1367 opp-hz = /bits/ 64 <320000000>; 1368 required-opps = <&rpmpd_opp_low_svs>; 1369 opp-supported-hw = <0x1f>; 1370 }; 1371 1372 opp-465000000 { 1373 opp-hz = /bits/ 64 <465000000>; 1374 required-opps = <&rpmpd_opp_svs>; 1375 opp-supported-hw = <0x1f>; 1376 }; 1377 1378 opp-600000000 { 1379 opp-hz = /bits/ 64 <600000000>; 1380 required-opps = <&rpmpd_opp_svs_plus>; 1381 opp-supported-hw = <0x1f>; 1382 }; 1383 1384 opp-745000000 { 1385 opp-hz = /bits/ 64 <745000000>; 1386 required-opps = <&rpmpd_opp_nom>; 1387 opp-supported-hw = <0xf>; 1388 }; 1389 1390 opp-820000000 { 1391 opp-hz = /bits/ 64 <820000000>; 1392 required-opps = <&rpmpd_opp_nom_plus>; 1393 opp-supported-hw = <0x7>; 1394 }; 1395 1396 opp-900000000 { 1397 opp-hz = /bits/ 64 <900000000>; 1398 required-opps = <&rpmpd_opp_turbo>; 1399 opp-supported-hw = <0x7>; 1400 }; 1401 1402 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1403 opp-950000000 { 1404 opp-hz = /bits/ 64 <950000000>; 1405 required-opps = <&rpmpd_opp_turbo_plus>; 1406 opp-supported-hw = <0x4>; 1407 }; 1408 1409 opp-980000000 { 1410 opp-hz = /bits/ 64 <980000000>; 1411 required-opps = <&rpmpd_opp_turbo_plus>; 1412 opp-supported-hw = <0x3>; 1413 }; 1414 }; 1415 }; 1416 1417 gmu_wrapper: gmu@596a000 { 1418 compatible = "qcom,adreno-gmu-wrapper"; 1419 reg = <0x0 0x0596a000 0x0 0x30000>; 1420 reg-names = "gmu"; 1421 power-domains = <&gpucc GPU_CX_GDSC>, 1422 <&gpucc GPU_GX_GDSC>; 1423 power-domain-names = "cx", "gx"; 1424 }; 1425 1426 gpucc: clock-controller@5990000 { 1427 compatible = "qcom,sm6115-gpucc"; 1428 reg = <0x0 0x05990000 0x0 0x9000>; 1429 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1430 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1431 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1432 #clock-cells = <1>; 1433 #reset-cells = <1>; 1434 #power-domain-cells = <1>; 1435 }; 1436 1437 adreno_smmu: iommu@59a0000 { 1438 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1439 "qcom,smmu-500", "arm,mmu-500"; 1440 reg = <0x0 0x059a0000 0x0 0x10000>; 1441 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1450 1451 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1452 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1453 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1454 clock-names = "mem", 1455 "hlos", 1456 "iface"; 1457 power-domains = <&gpucc GPU_CX_GDSC>; 1458 1459 #global-interrupts = <1>; 1460 #iommu-cells = <2>; 1461 }; 1462 1463 mdss: display-subsystem@5e00000 { 1464 compatible = "qcom,sm6115-mdss"; 1465 reg = <0x0 0x05e00000 0x0 0x1000>; 1466 reg-names = "mdss"; 1467 1468 power-domains = <&dispcc MDSS_GDSC>; 1469 1470 clocks = <&gcc GCC_DISP_AHB_CLK>, 1471 <&gcc GCC_DISP_HF_AXI_CLK>, 1472 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1473 1474 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1475 interrupt-controller; 1476 #interrupt-cells = <1>; 1477 1478 iommus = <&apps_smmu 0x420 0x2>, 1479 <&apps_smmu 0x421 0x0>; 1480 1481 #address-cells = <2>; 1482 #size-cells = <2>; 1483 ranges; 1484 1485 status = "disabled"; 1486 1487 mdp: display-controller@5e01000 { 1488 compatible = "qcom,sm6115-dpu"; 1489 reg = <0x0 0x05e01000 0x0 0x8f000>, 1490 <0x0 0x05eb0000 0x0 0x2008>; 1491 reg-names = "mdp", "vbif"; 1492 1493 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1494 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1495 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1496 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1497 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1498 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1499 clock-names = "bus", 1500 "iface", 1501 "core", 1502 "lut", 1503 "rot", 1504 "vsync"; 1505 1506 operating-points-v2 = <&mdp_opp_table>; 1507 power-domains = <&rpmpd SM6115_VDDCX>; 1508 1509 interrupt-parent = <&mdss>; 1510 interrupts = <0>; 1511 1512 ports { 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 1516 port@0 { 1517 reg = <0>; 1518 dpu_intf1_out: endpoint { 1519 remote-endpoint = <&mdss_dsi0_in>; 1520 }; 1521 }; 1522 }; 1523 1524 mdp_opp_table: opp-table { 1525 compatible = "operating-points-v2"; 1526 1527 opp-19200000 { 1528 opp-hz = /bits/ 64 <19200000>; 1529 required-opps = <&rpmpd_opp_min_svs>; 1530 }; 1531 1532 opp-192000000 { 1533 opp-hz = /bits/ 64 <192000000>; 1534 required-opps = <&rpmpd_opp_low_svs>; 1535 }; 1536 1537 opp-256000000 { 1538 opp-hz = /bits/ 64 <256000000>; 1539 required-opps = <&rpmpd_opp_svs>; 1540 }; 1541 1542 opp-307200000 { 1543 opp-hz = /bits/ 64 <307200000>; 1544 required-opps = <&rpmpd_opp_svs_plus>; 1545 }; 1546 1547 opp-384000000 { 1548 opp-hz = /bits/ 64 <384000000>; 1549 required-opps = <&rpmpd_opp_nom>; 1550 }; 1551 }; 1552 }; 1553 1554 mdss_dsi0: dsi@5e94000 { 1555 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1556 reg = <0x0 0x05e94000 0x0 0x400>; 1557 reg-names = "dsi_ctrl"; 1558 1559 interrupt-parent = <&mdss>; 1560 interrupts = <4>; 1561 1562 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1563 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1564 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1565 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1566 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1567 <&gcc GCC_DISP_HF_AXI_CLK>; 1568 clock-names = "byte", 1569 "byte_intf", 1570 "pixel", 1571 "core", 1572 "iface", 1573 "bus"; 1574 1575 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1576 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1577 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1578 1579 operating-points-v2 = <&dsi_opp_table>; 1580 power-domains = <&rpmpd SM6115_VDDCX>; 1581 phys = <&mdss_dsi0_phy>; 1582 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 1586 status = "disabled"; 1587 1588 ports { 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 1592 port@0 { 1593 reg = <0>; 1594 mdss_dsi0_in: endpoint { 1595 remote-endpoint = <&dpu_intf1_out>; 1596 }; 1597 }; 1598 1599 port@1 { 1600 reg = <1>; 1601 mdss_dsi0_out: endpoint { 1602 }; 1603 }; 1604 }; 1605 1606 dsi_opp_table: opp-table { 1607 compatible = "operating-points-v2"; 1608 1609 opp-19200000 { 1610 opp-hz = /bits/ 64 <19200000>; 1611 required-opps = <&rpmpd_opp_min_svs>; 1612 }; 1613 1614 opp-164000000 { 1615 opp-hz = /bits/ 64 <164000000>; 1616 required-opps = <&rpmpd_opp_low_svs>; 1617 }; 1618 1619 opp-187500000 { 1620 opp-hz = /bits/ 64 <187500000>; 1621 required-opps = <&rpmpd_opp_svs>; 1622 }; 1623 }; 1624 }; 1625 1626 mdss_dsi0_phy: phy@5e94400 { 1627 compatible = "qcom,dsi-phy-14nm-2290"; 1628 reg = <0x0 0x05e94400 0x0 0x100>, 1629 <0x0 0x05e94500 0x0 0x300>, 1630 <0x0 0x05e94800 0x0 0x188>; 1631 reg-names = "dsi_phy", 1632 "dsi_phy_lane", 1633 "dsi_pll"; 1634 1635 #clock-cells = <1>; 1636 #phy-cells = <0>; 1637 1638 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1639 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1640 clock-names = "iface", "ref"; 1641 1642 status = "disabled"; 1643 }; 1644 }; 1645 1646 dispcc: clock-controller@5f00000 { 1647 compatible = "qcom,sm6115-dispcc"; 1648 reg = <0x0 0x05f00000 0 0x20000>; 1649 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1650 <&sleep_clk>, 1651 <&mdss_dsi0_phy 0>, 1652 <&mdss_dsi0_phy 1>, 1653 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1654 #clock-cells = <1>; 1655 #reset-cells = <1>; 1656 #power-domain-cells = <1>; 1657 }; 1658 1659 remoteproc_mpss: remoteproc@6080000 { 1660 compatible = "qcom,sm6115-mpss-pas"; 1661 reg = <0x0 0x06080000 0x0 0x100>; 1662 1663 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1664 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1665 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1666 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1667 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1668 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1669 interrupt-names = "wdog", "fatal", "ready", "handover", 1670 "stop-ack", "shutdown-ack"; 1671 1672 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1673 clock-names = "xo"; 1674 1675 power-domains = <&rpmpd SM6115_VDDCX>; 1676 1677 memory-region = <&pil_modem_mem>; 1678 1679 qcom,smem-states = <&modem_smp2p_out 0>; 1680 qcom,smem-state-names = "stop"; 1681 1682 status = "disabled"; 1683 1684 glink-edge { 1685 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1686 label = "mpss"; 1687 qcom,remote-pid = <1>; 1688 mboxes = <&apcs_glb 12>; 1689 }; 1690 }; 1691 1692 stm@8002000 { 1693 compatible = "arm,coresight-stm", "arm,primecell"; 1694 reg = <0x0 0x08002000 0x0 0x1000>, 1695 <0x0 0x0e280000 0x0 0x180000>; 1696 reg-names = "stm-base", "stm-stimulus-base"; 1697 1698 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1699 clock-names = "apb_pclk"; 1700 1701 status = "disabled"; 1702 1703 out-ports { 1704 port { 1705 stm_out: endpoint { 1706 remote-endpoint = <&funnel_in0_in>; 1707 }; 1708 }; 1709 }; 1710 }; 1711 1712 cti0: cti@8010000 { 1713 compatible = "arm,coresight-cti", "arm,primecell"; 1714 reg = <0x0 0x08010000 0x0 0x1000>; 1715 1716 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1717 clock-names = "apb_pclk"; 1718 1719 status = "disabled"; 1720 }; 1721 1722 cti1: cti@8011000 { 1723 compatible = "arm,coresight-cti", "arm,primecell"; 1724 reg = <0x0 0x08011000 0x0 0x1000>; 1725 1726 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1727 clock-names = "apb_pclk"; 1728 1729 status = "disabled"; 1730 }; 1731 1732 cti2: cti@8012000 { 1733 compatible = "arm,coresight-cti", "arm,primecell"; 1734 reg = <0x0 0x08012000 0x0 0x1000>; 1735 1736 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1737 clock-names = "apb_pclk"; 1738 1739 status = "disabled"; 1740 }; 1741 1742 cti3: cti@8013000 { 1743 compatible = "arm,coresight-cti", "arm,primecell"; 1744 reg = <0x0 0x08013000 0x0 0x1000>; 1745 1746 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1747 clock-names = "apb_pclk"; 1748 1749 status = "disabled"; 1750 }; 1751 1752 cti4: cti@8014000 { 1753 compatible = "arm,coresight-cti", "arm,primecell"; 1754 reg = <0x0 0x08014000 0x0 0x1000>; 1755 1756 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1757 clock-names = "apb_pclk"; 1758 1759 status = "disabled"; 1760 }; 1761 1762 cti5: cti@8015000 { 1763 compatible = "arm,coresight-cti", "arm,primecell"; 1764 reg = <0x0 0x08015000 0x0 0x1000>; 1765 1766 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1767 clock-names = "apb_pclk"; 1768 1769 status = "disabled"; 1770 }; 1771 1772 cti6: cti@8016000 { 1773 compatible = "arm,coresight-cti", "arm,primecell"; 1774 reg = <0x0 0x08016000 0x0 0x1000>; 1775 1776 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1777 clock-names = "apb_pclk"; 1778 1779 status = "disabled"; 1780 }; 1781 1782 cti7: cti@8017000 { 1783 compatible = "arm,coresight-cti", "arm,primecell"; 1784 reg = <0x0 0x08017000 0x0 0x1000>; 1785 1786 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1787 clock-names = "apb_pclk"; 1788 1789 status = "disabled"; 1790 }; 1791 1792 cti8: cti@8018000 { 1793 compatible = "arm,coresight-cti", "arm,primecell"; 1794 reg = <0x0 0x08018000 0x0 0x1000>; 1795 1796 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1797 clock-names = "apb_pclk"; 1798 1799 status = "disabled"; 1800 }; 1801 1802 cti9: cti@8019000 { 1803 compatible = "arm,coresight-cti", "arm,primecell"; 1804 reg = <0x0 0x08019000 0x0 0x1000>; 1805 1806 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1807 clock-names = "apb_pclk"; 1808 1809 status = "disabled"; 1810 }; 1811 1812 cti10: cti@801a000 { 1813 compatible = "arm,coresight-cti", "arm,primecell"; 1814 reg = <0x0 0x0801a000 0x0 0x1000>; 1815 1816 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1817 clock-names = "apb_pclk"; 1818 1819 status = "disabled"; 1820 }; 1821 1822 cti11: cti@801b000 { 1823 compatible = "arm,coresight-cti", "arm,primecell"; 1824 reg = <0x0 0x0801b000 0x0 0x1000>; 1825 1826 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1827 clock-names = "apb_pclk"; 1828 1829 status = "disabled"; 1830 }; 1831 1832 cti12: cti@801c000 { 1833 compatible = "arm,coresight-cti", "arm,primecell"; 1834 reg = <0x0 0x0801c000 0x0 0x1000>; 1835 1836 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1837 clock-names = "apb_pclk"; 1838 1839 status = "disabled"; 1840 }; 1841 1842 cti13: cti@801d000 { 1843 compatible = "arm,coresight-cti", "arm,primecell"; 1844 reg = <0x0 0x0801d000 0x0 0x1000>; 1845 1846 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1847 clock-names = "apb_pclk"; 1848 1849 status = "disabled"; 1850 }; 1851 1852 cti14: cti@801e000 { 1853 compatible = "arm,coresight-cti", "arm,primecell"; 1854 reg = <0x0 0x0801e000 0x0 0x1000>; 1855 1856 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1857 clock-names = "apb_pclk"; 1858 1859 status = "disabled"; 1860 }; 1861 1862 cti15: cti@801f000 { 1863 compatible = "arm,coresight-cti", "arm,primecell"; 1864 reg = <0x0 0x0801f000 0x0 0x1000>; 1865 1866 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1867 clock-names = "apb_pclk"; 1868 1869 status = "disabled"; 1870 }; 1871 1872 replicator@8046000 { 1873 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1874 reg = <0x0 0x08046000 0x0 0x1000>; 1875 1876 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1877 clock-names = "apb_pclk"; 1878 1879 status = "disabled"; 1880 1881 out-ports { 1882 port { 1883 replicator_out: endpoint { 1884 remote-endpoint = <&etr_in>; 1885 }; 1886 }; 1887 }; 1888 1889 in-ports { 1890 port { 1891 replicator_in: endpoint { 1892 remote-endpoint = <&etf_out>; 1893 }; 1894 }; 1895 }; 1896 }; 1897 1898 etf@8047000 { 1899 compatible = "arm,coresight-tmc", "arm,primecell"; 1900 reg = <0x0 0x08047000 0x0 0x1000>; 1901 1902 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1903 clock-names = "apb_pclk"; 1904 1905 status = "disabled"; 1906 1907 in-ports { 1908 port { 1909 etf_in: endpoint { 1910 remote-endpoint = <&merge_funnel_out>; 1911 }; 1912 }; 1913 }; 1914 1915 out-ports { 1916 port { 1917 etf_out: endpoint { 1918 remote-endpoint = <&replicator_in>; 1919 }; 1920 }; 1921 }; 1922 }; 1923 1924 etr@8048000 { 1925 compatible = "arm,coresight-tmc", "arm,primecell"; 1926 reg = <0x0 0x08048000 0x0 0x1000>; 1927 1928 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1929 clock-names = "apb_pclk"; 1930 1931 status = "disabled"; 1932 1933 in-ports { 1934 port { 1935 etr_in: endpoint { 1936 remote-endpoint = <&replicator_out>; 1937 }; 1938 }; 1939 }; 1940 }; 1941 1942 funnel@8041000 { 1943 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1944 reg = <0x0 0x08041000 0x0 0x1000>; 1945 1946 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1947 clock-names = "apb_pclk"; 1948 1949 status = "disabled"; 1950 1951 out-ports { 1952 port { 1953 funnel_in0_out: endpoint { 1954 remote-endpoint = <&merge_funnel_in0>; 1955 }; 1956 }; 1957 }; 1958 1959 in-ports { 1960 port { 1961 funnel_in0_in: endpoint { 1962 remote-endpoint = <&stm_out>; 1963 }; 1964 }; 1965 }; 1966 }; 1967 1968 funnel@8042000 { 1969 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1970 reg = <0x0 0x08042000 0x0 0x1000>; 1971 1972 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1973 clock-names = "apb_pclk"; 1974 1975 status = "disabled"; 1976 1977 out-ports { 1978 port { 1979 funnel_in1_out: endpoint { 1980 remote-endpoint = <&merge_funnel_in1>; 1981 }; 1982 }; 1983 }; 1984 1985 in-ports { 1986 port { 1987 funnel_in1_in: endpoint { 1988 remote-endpoint = <&funnel_apss1_out>; 1989 }; 1990 }; 1991 }; 1992 }; 1993 1994 funnel@8045000 { 1995 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1996 reg = <0x0 0x08045000 0x0 0x1000>; 1997 1998 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1999 clock-names = "apb_pclk"; 2000 2001 status = "disabled"; 2002 2003 out-ports { 2004 port { 2005 merge_funnel_out: endpoint { 2006 remote-endpoint = <&etf_in>; 2007 }; 2008 }; 2009 }; 2010 2011 in-ports { 2012 #address-cells = <1>; 2013 #size-cells = <0>; 2014 2015 port@0 { 2016 reg = <0>; 2017 merge_funnel_in0: endpoint { 2018 remote-endpoint = <&funnel_in0_out>; 2019 }; 2020 }; 2021 2022 port@1 { 2023 reg = <1>; 2024 merge_funnel_in1: endpoint { 2025 remote-endpoint = <&funnel_in1_out>; 2026 }; 2027 }; 2028 }; 2029 }; 2030 2031 etm@9040000 { 2032 compatible = "arm,coresight-etm4x", "arm,primecell"; 2033 reg = <0x0 0x09040000 0x0 0x1000>; 2034 2035 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2036 clock-names = "apb_pclk"; 2037 arm,coresight-loses-context-with-cpu; 2038 2039 cpu = <&CPU0>; 2040 2041 status = "disabled"; 2042 2043 out-ports { 2044 port { 2045 etm0_out: endpoint { 2046 remote-endpoint = <&funnel_apss0_in0>; 2047 }; 2048 }; 2049 }; 2050 }; 2051 2052 etm@9140000 { 2053 compatible = "arm,coresight-etm4x", "arm,primecell"; 2054 reg = <0x0 0x09140000 0x0 0x1000>; 2055 2056 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2057 clock-names = "apb_pclk"; 2058 arm,coresight-loses-context-with-cpu; 2059 2060 cpu = <&CPU1>; 2061 2062 status = "disabled"; 2063 2064 out-ports { 2065 port { 2066 etm1_out: endpoint { 2067 remote-endpoint = <&funnel_apss0_in1>; 2068 }; 2069 }; 2070 }; 2071 }; 2072 2073 etm@9240000 { 2074 compatible = "arm,coresight-etm4x", "arm,primecell"; 2075 reg = <0x0 0x09240000 0x0 0x1000>; 2076 2077 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2078 clock-names = "apb_pclk"; 2079 arm,coresight-loses-context-with-cpu; 2080 2081 cpu = <&CPU2>; 2082 2083 status = "disabled"; 2084 2085 out-ports { 2086 port { 2087 etm2_out: endpoint { 2088 remote-endpoint = <&funnel_apss0_in2>; 2089 }; 2090 }; 2091 }; 2092 }; 2093 2094 etm@9340000 { 2095 compatible = "arm,coresight-etm4x", "arm,primecell"; 2096 reg = <0x0 0x09340000 0x0 0x1000>; 2097 2098 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2099 clock-names = "apb_pclk"; 2100 arm,coresight-loses-context-with-cpu; 2101 2102 cpu = <&CPU3>; 2103 2104 status = "disabled"; 2105 2106 out-ports { 2107 port { 2108 etm3_out: endpoint { 2109 remote-endpoint = <&funnel_apss0_in3>; 2110 }; 2111 }; 2112 }; 2113 }; 2114 2115 etm@9440000 { 2116 compatible = "arm,coresight-etm4x", "arm,primecell"; 2117 reg = <0x0 0x09440000 0x0 0x1000>; 2118 2119 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2120 clock-names = "apb_pclk"; 2121 arm,coresight-loses-context-with-cpu; 2122 2123 cpu = <&CPU4>; 2124 2125 status = "disabled"; 2126 2127 out-ports { 2128 port { 2129 etm4_out: endpoint { 2130 remote-endpoint = <&funnel_apss0_in4>; 2131 }; 2132 }; 2133 }; 2134 }; 2135 2136 etm@9540000 { 2137 compatible = "arm,coresight-etm4x", "arm,primecell"; 2138 reg = <0x0 0x09540000 0x0 0x1000>; 2139 2140 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2141 clock-names = "apb_pclk"; 2142 arm,coresight-loses-context-with-cpu; 2143 2144 cpu = <&CPU5>; 2145 2146 status = "disabled"; 2147 2148 out-ports { 2149 port { 2150 etm5_out: endpoint { 2151 remote-endpoint = <&funnel_apss0_in5>; 2152 }; 2153 }; 2154 }; 2155 }; 2156 2157 etm@9640000 { 2158 compatible = "arm,coresight-etm4x", "arm,primecell"; 2159 reg = <0x0 0x09640000 0x0 0x1000>; 2160 2161 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2162 clock-names = "apb_pclk"; 2163 arm,coresight-loses-context-with-cpu; 2164 2165 cpu = <&CPU6>; 2166 2167 status = "disabled"; 2168 2169 out-ports { 2170 port { 2171 etm6_out: endpoint { 2172 remote-endpoint = <&funnel_apss0_in6>; 2173 }; 2174 }; 2175 }; 2176 }; 2177 2178 etm@9740000 { 2179 compatible = "arm,coresight-etm4x", "arm,primecell"; 2180 reg = <0x0 0x09740000 0x0 0x1000>; 2181 2182 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2183 clock-names = "apb_pclk"; 2184 arm,coresight-loses-context-with-cpu; 2185 2186 cpu = <&CPU7>; 2187 2188 status = "disabled"; 2189 2190 out-ports { 2191 port { 2192 etm7_out: endpoint { 2193 remote-endpoint = <&funnel_apss0_in7>; 2194 }; 2195 }; 2196 }; 2197 }; 2198 2199 funnel@9800000 { 2200 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2201 reg = <0x0 0x09800000 0x0 0x1000>; 2202 2203 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2204 clock-names = "apb_pclk"; 2205 2206 status = "disabled"; 2207 2208 out-ports { 2209 port { 2210 funnel_apss0_out: endpoint { 2211 remote-endpoint = <&funnel_apss1_in>; 2212 }; 2213 }; 2214 }; 2215 2216 in-ports { 2217 #address-cells = <1>; 2218 #size-cells = <0>; 2219 2220 port@0 { 2221 reg = <0>; 2222 funnel_apss0_in0: endpoint { 2223 remote-endpoint = <&etm0_out>; 2224 }; 2225 }; 2226 2227 port@1 { 2228 reg = <1>; 2229 funnel_apss0_in1: endpoint { 2230 remote-endpoint = <&etm1_out>; 2231 }; 2232 }; 2233 2234 port@2 { 2235 reg = <2>; 2236 funnel_apss0_in2: endpoint { 2237 remote-endpoint = <&etm2_out>; 2238 }; 2239 }; 2240 2241 port@3 { 2242 reg = <3>; 2243 funnel_apss0_in3: endpoint { 2244 remote-endpoint = <&etm3_out>; 2245 }; 2246 }; 2247 2248 port@4 { 2249 reg = <4>; 2250 funnel_apss0_in4: endpoint { 2251 remote-endpoint = <&etm4_out>; 2252 }; 2253 }; 2254 2255 port@5 { 2256 reg = <5>; 2257 funnel_apss0_in5: endpoint { 2258 remote-endpoint = <&etm5_out>; 2259 }; 2260 }; 2261 2262 port@6 { 2263 reg = <6>; 2264 funnel_apss0_in6: endpoint { 2265 remote-endpoint = <&etm6_out>; 2266 }; 2267 }; 2268 2269 port@7 { 2270 reg = <7>; 2271 funnel_apss0_in7: endpoint { 2272 remote-endpoint = <&etm7_out>; 2273 }; 2274 }; 2275 }; 2276 }; 2277 2278 funnel@9810000 { 2279 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2280 reg = <0x0 0x09810000 0x0 0x1000>; 2281 2282 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2283 clock-names = "apb_pclk"; 2284 2285 status = "disabled"; 2286 2287 out-ports { 2288 port { 2289 funnel_apss1_out: endpoint { 2290 remote-endpoint = <&funnel_in1_in>; 2291 }; 2292 }; 2293 }; 2294 2295 in-ports { 2296 port { 2297 funnel_apss1_in: endpoint { 2298 remote-endpoint = <&funnel_apss0_out>; 2299 }; 2300 }; 2301 }; 2302 }; 2303 2304 remoteproc_adsp: remoteproc@ab00000 { 2305 compatible = "qcom,sm6115-adsp-pas"; 2306 reg = <0x0 0x0ab00000 0x0 0x100>; 2307 2308 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2309 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2310 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2311 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2312 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2313 interrupt-names = "wdog", "fatal", "ready", 2314 "handover", "stop-ack"; 2315 2316 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2317 clock-names = "xo"; 2318 2319 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2320 <&rpmpd SM6115_VDD_LPI_MX>; 2321 2322 memory-region = <&pil_adsp_mem>; 2323 2324 qcom,smem-states = <&adsp_smp2p_out 0>; 2325 qcom,smem-state-names = "stop"; 2326 2327 status = "disabled"; 2328 2329 glink-edge { 2330 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2331 label = "lpass"; 2332 qcom,remote-pid = <2>; 2333 mboxes = <&apcs_glb 8>; 2334 2335 fastrpc { 2336 compatible = "qcom,fastrpc"; 2337 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2338 label = "adsp"; 2339 qcom,non-secure-domain; 2340 #address-cells = <1>; 2341 #size-cells = <0>; 2342 2343 compute-cb@3 { 2344 compatible = "qcom,fastrpc-compute-cb"; 2345 reg = <3>; 2346 iommus = <&apps_smmu 0x01c3 0x0>; 2347 }; 2348 2349 compute-cb@4 { 2350 compatible = "qcom,fastrpc-compute-cb"; 2351 reg = <4>; 2352 iommus = <&apps_smmu 0x01c4 0x0>; 2353 }; 2354 2355 compute-cb@5 { 2356 compatible = "qcom,fastrpc-compute-cb"; 2357 reg = <5>; 2358 iommus = <&apps_smmu 0x01c5 0x0>; 2359 }; 2360 2361 compute-cb@6 { 2362 compatible = "qcom,fastrpc-compute-cb"; 2363 reg = <6>; 2364 iommus = <&apps_smmu 0x01c6 0x0>; 2365 }; 2366 2367 compute-cb@7 { 2368 compatible = "qcom,fastrpc-compute-cb"; 2369 reg = <7>; 2370 iommus = <&apps_smmu 0x01c7 0x0>; 2371 }; 2372 }; 2373 }; 2374 }; 2375 2376 remoteproc_cdsp: remoteproc@b300000 { 2377 compatible = "qcom,sm6115-cdsp-pas"; 2378 reg = <0x0 0x0b300000 0x0 0x100000>; 2379 2380 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2381 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2382 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2383 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2384 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2385 interrupt-names = "wdog", "fatal", "ready", 2386 "handover", "stop-ack"; 2387 2388 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2389 clock-names = "xo"; 2390 2391 power-domains = <&rpmpd SM6115_VDDCX>; 2392 2393 memory-region = <&pil_cdsp_mem>; 2394 2395 qcom,smem-states = <&cdsp_smp2p_out 0>; 2396 qcom,smem-state-names = "stop"; 2397 2398 status = "disabled"; 2399 2400 glink-edge { 2401 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2402 label = "cdsp"; 2403 qcom,remote-pid = <5>; 2404 mboxes = <&apcs_glb 28>; 2405 2406 fastrpc { 2407 compatible = "qcom,fastrpc"; 2408 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2409 label = "cdsp"; 2410 qcom,non-secure-domain; 2411 #address-cells = <1>; 2412 #size-cells = <0>; 2413 2414 compute-cb@1 { 2415 compatible = "qcom,fastrpc-compute-cb"; 2416 reg = <1>; 2417 iommus = <&apps_smmu 0x0c01 0x0>; 2418 }; 2419 2420 compute-cb@2 { 2421 compatible = "qcom,fastrpc-compute-cb"; 2422 reg = <2>; 2423 iommus = <&apps_smmu 0x0c02 0x0>; 2424 }; 2425 2426 compute-cb@3 { 2427 compatible = "qcom,fastrpc-compute-cb"; 2428 reg = <3>; 2429 iommus = <&apps_smmu 0x0c03 0x0>; 2430 }; 2431 2432 compute-cb@4 { 2433 compatible = "qcom,fastrpc-compute-cb"; 2434 reg = <4>; 2435 iommus = <&apps_smmu 0x0c04 0x0>; 2436 }; 2437 2438 compute-cb@5 { 2439 compatible = "qcom,fastrpc-compute-cb"; 2440 reg = <5>; 2441 iommus = <&apps_smmu 0x0c05 0x0>; 2442 }; 2443 2444 compute-cb@6 { 2445 compatible = "qcom,fastrpc-compute-cb"; 2446 reg = <6>; 2447 iommus = <&apps_smmu 0x0c06 0x0>; 2448 }; 2449 2450 /* note: secure cb9 in downstream */ 2451 }; 2452 }; 2453 }; 2454 2455 apps_smmu: iommu@c600000 { 2456 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2457 reg = <0x0 0x0c600000 0x0 0x80000>; 2458 #iommu-cells = <2>; 2459 #global-interrupts = <1>; 2460 2461 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2526 }; 2527 2528 wifi: wifi@c800000 { 2529 compatible = "qcom,wcn3990-wifi"; 2530 reg = <0x0 0x0c800000 0x0 0x800000>; 2531 reg-names = "membase"; 2532 memory-region = <&wlan_msa_mem>; 2533 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2534 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2535 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2538 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2539 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2541 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2545 iommus = <&apps_smmu 0x1a0 0x1>; 2546 qcom,msa-fixed-perm; 2547 status = "disabled"; 2548 }; 2549 2550 watchdog@f017000 { 2551 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2552 reg = <0x0 0x0f017000 0x0 0x1000>; 2553 clocks = <&sleep_clk>; 2554 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2555 }; 2556 2557 apcs_glb: mailbox@f111000 { 2558 compatible = "qcom,sm6115-apcs-hmss-global", 2559 "qcom,msm8994-apcs-kpss-global"; 2560 reg = <0x0 0x0f111000 0x0 0x1000>; 2561 2562 #mbox-cells = <1>; 2563 }; 2564 2565 timer@f120000 { 2566 compatible = "arm,armv7-timer-mem"; 2567 reg = <0x0 0x0f120000 0x0 0x1000>; 2568 #address-cells = <2>; 2569 #size-cells = <2>; 2570 ranges; 2571 clock-frequency = <19200000>; 2572 2573 frame@f121000 { 2574 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2575 frame-number = <0>; 2576 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2577 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2578 }; 2579 2580 frame@f123000 { 2581 reg = <0x0 0x0f123000 0x0 0x1000>; 2582 frame-number = <1>; 2583 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2584 status = "disabled"; 2585 }; 2586 2587 frame@f124000 { 2588 reg = <0x0 0x0f124000 0x0 0x1000>; 2589 frame-number = <2>; 2590 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2591 status = "disabled"; 2592 }; 2593 2594 frame@f125000 { 2595 reg = <0x0 0x0f125000 0x0 0x1000>; 2596 frame-number = <3>; 2597 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2598 status = "disabled"; 2599 }; 2600 2601 frame@f126000 { 2602 reg = <0x0 0x0f126000 0x0 0x1000>; 2603 frame-number = <4>; 2604 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2605 status = "disabled"; 2606 }; 2607 2608 frame@f127000 { 2609 reg = <0x0 0x0f127000 0x0 0x1000>; 2610 frame-number = <5>; 2611 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2612 status = "disabled"; 2613 }; 2614 2615 frame@f128000 { 2616 reg = <0x0 0x0f128000 0x0 0x1000>; 2617 frame-number = <6>; 2618 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2619 status = "disabled"; 2620 }; 2621 }; 2622 2623 intc: interrupt-controller@f200000 { 2624 compatible = "arm,gic-v3"; 2625 reg = <0x0 0x0f200000 0x0 0x10000>, 2626 <0x0 0x0f300000 0x0 0x100000>; 2627 #interrupt-cells = <3>; 2628 interrupt-controller; 2629 interrupt-parent = <&intc>; 2630 #redistributor-regions = <1>; 2631 redistributor-stride = <0x0 0x20000>; 2632 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2633 }; 2634 2635 cpufreq_hw: cpufreq@f521000 { 2636 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2637 reg = <0x0 0x0f521000 0x0 0x1000>, 2638 <0x0 0x0f523000 0x0 0x1000>; 2639 2640 reg-names = "freq-domain0", "freq-domain1"; 2641 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2642 clock-names = "xo", "alternate"; 2643 2644 #freq-domain-cells = <1>; 2645 #clock-cells = <1>; 2646 }; 2647 }; 2648 2649 thermal-zones { 2650 mapss-thermal { 2651 polling-delay-passive = <0>; 2652 polling-delay = <0>; 2653 thermal-sensors = <&tsens0 0>; 2654 2655 trips { 2656 trip-point0 { 2657 temperature = <115000>; 2658 hysteresis = <5000>; 2659 type = "passive"; 2660 }; 2661 2662 trip-point1 { 2663 temperature = <125000>; 2664 hysteresis = <1000>; 2665 type = "passive"; 2666 }; 2667 }; 2668 }; 2669 2670 cdsp-hvx-thermal { 2671 polling-delay-passive = <0>; 2672 polling-delay = <0>; 2673 thermal-sensors = <&tsens0 1>; 2674 2675 trips { 2676 trip-point0 { 2677 temperature = <115000>; 2678 hysteresis = <5000>; 2679 type = "passive"; 2680 }; 2681 2682 trip-point1 { 2683 temperature = <125000>; 2684 hysteresis = <1000>; 2685 type = "passive"; 2686 }; 2687 }; 2688 }; 2689 2690 wlan-thermal { 2691 polling-delay-passive = <0>; 2692 polling-delay = <0>; 2693 thermal-sensors = <&tsens0 2>; 2694 2695 trips { 2696 trip-point0 { 2697 temperature = <115000>; 2698 hysteresis = <5000>; 2699 type = "passive"; 2700 }; 2701 2702 trip-point1 { 2703 temperature = <125000>; 2704 hysteresis = <1000>; 2705 type = "passive"; 2706 }; 2707 }; 2708 }; 2709 2710 camera-thermal { 2711 polling-delay-passive = <0>; 2712 polling-delay = <0>; 2713 thermal-sensors = <&tsens0 3>; 2714 2715 trips { 2716 trip-point0 { 2717 temperature = <115000>; 2718 hysteresis = <5000>; 2719 type = "passive"; 2720 }; 2721 2722 trip-point1 { 2723 temperature = <125000>; 2724 hysteresis = <1000>; 2725 type = "passive"; 2726 }; 2727 }; 2728 }; 2729 2730 video-thermal { 2731 polling-delay-passive = <0>; 2732 polling-delay = <0>; 2733 thermal-sensors = <&tsens0 4>; 2734 2735 trips { 2736 trip-point0 { 2737 temperature = <115000>; 2738 hysteresis = <5000>; 2739 type = "passive"; 2740 }; 2741 2742 trip-point1 { 2743 temperature = <125000>; 2744 hysteresis = <1000>; 2745 type = "passive"; 2746 }; 2747 }; 2748 }; 2749 2750 modem1-thermal { 2751 polling-delay-passive = <0>; 2752 polling-delay = <0>; 2753 thermal-sensors = <&tsens0 5>; 2754 2755 trips { 2756 trip-point0 { 2757 temperature = <115000>; 2758 hysteresis = <5000>; 2759 type = "passive"; 2760 }; 2761 2762 trip-point1 { 2763 temperature = <125000>; 2764 hysteresis = <1000>; 2765 type = "passive"; 2766 }; 2767 }; 2768 }; 2769 2770 cpu4-thermal { 2771 polling-delay-passive = <0>; 2772 polling-delay = <0>; 2773 thermal-sensors = <&tsens0 6>; 2774 2775 trips { 2776 cpu4_alert0: trip-point0 { 2777 temperature = <90000>; 2778 hysteresis = <2000>; 2779 type = "passive"; 2780 }; 2781 2782 cpu4_alert1: trip-point1 { 2783 temperature = <95000>; 2784 hysteresis = <2000>; 2785 type = "passive"; 2786 }; 2787 2788 cpu4_crit: cpu_crit { 2789 temperature = <110000>; 2790 hysteresis = <1000>; 2791 type = "critical"; 2792 }; 2793 }; 2794 }; 2795 2796 cpu5-thermal { 2797 polling-delay-passive = <0>; 2798 polling-delay = <0>; 2799 thermal-sensors = <&tsens0 7>; 2800 2801 trips { 2802 cpu5_alert0: trip-point0 { 2803 temperature = <90000>; 2804 hysteresis = <2000>; 2805 type = "passive"; 2806 }; 2807 2808 cpu5_alert1: trip-point1 { 2809 temperature = <95000>; 2810 hysteresis = <2000>; 2811 type = "passive"; 2812 }; 2813 2814 cpu5_crit: cpu_crit { 2815 temperature = <110000>; 2816 hysteresis = <1000>; 2817 type = "critical"; 2818 }; 2819 }; 2820 }; 2821 2822 cpu6-thermal { 2823 polling-delay-passive = <0>; 2824 polling-delay = <0>; 2825 thermal-sensors = <&tsens0 8>; 2826 2827 trips { 2828 cpu6_alert0: trip-point0 { 2829 temperature = <90000>; 2830 hysteresis = <2000>; 2831 type = "passive"; 2832 }; 2833 2834 cpu6_alert1: trip-point1 { 2835 temperature = <95000>; 2836 hysteresis = <2000>; 2837 type = "passive"; 2838 }; 2839 2840 cpu6_crit: cpu_crit { 2841 temperature = <110000>; 2842 hysteresis = <1000>; 2843 type = "critical"; 2844 }; 2845 }; 2846 }; 2847 2848 cpu7-thermal { 2849 polling-delay-passive = <0>; 2850 polling-delay = <0>; 2851 thermal-sensors = <&tsens0 9>; 2852 2853 trips { 2854 cpu7_alert0: trip-point0 { 2855 temperature = <90000>; 2856 hysteresis = <2000>; 2857 type = "passive"; 2858 }; 2859 2860 cpu7_alert1: trip-point1 { 2861 temperature = <95000>; 2862 hysteresis = <2000>; 2863 type = "passive"; 2864 }; 2865 2866 cpu7_crit: cpu_crit { 2867 temperature = <110000>; 2868 hysteresis = <1000>; 2869 type = "critical"; 2870 }; 2871 }; 2872 }; 2873 2874 cpu45-thermal { 2875 polling-delay-passive = <0>; 2876 polling-delay = <0>; 2877 thermal-sensors = <&tsens0 10>; 2878 2879 trips { 2880 cpu45_alert0: trip-point0 { 2881 temperature = <90000>; 2882 hysteresis = <2000>; 2883 type = "passive"; 2884 }; 2885 2886 cpu45_alert1: trip-point1 { 2887 temperature = <95000>; 2888 hysteresis = <2000>; 2889 type = "passive"; 2890 }; 2891 2892 cpu45_crit: cpu_crit { 2893 temperature = <110000>; 2894 hysteresis = <1000>; 2895 type = "critical"; 2896 }; 2897 }; 2898 }; 2899 2900 cpu67-thermal { 2901 polling-delay-passive = <0>; 2902 polling-delay = <0>; 2903 thermal-sensors = <&tsens0 11>; 2904 2905 trips { 2906 cpu67_alert0: trip-point0 { 2907 temperature = <90000>; 2908 hysteresis = <2000>; 2909 type = "passive"; 2910 }; 2911 2912 cpu67_alert1: trip-point1 { 2913 temperature = <95000>; 2914 hysteresis = <2000>; 2915 type = "passive"; 2916 }; 2917 2918 cpu67_crit: cpu_crit { 2919 temperature = <110000>; 2920 hysteresis = <1000>; 2921 type = "critical"; 2922 }; 2923 }; 2924 }; 2925 2926 cpu0123-thermal { 2927 polling-delay-passive = <0>; 2928 polling-delay = <0>; 2929 thermal-sensors = <&tsens0 12>; 2930 2931 trips { 2932 cpu0123_alert0: trip-point0 { 2933 temperature = <90000>; 2934 hysteresis = <2000>; 2935 type = "passive"; 2936 }; 2937 2938 cpu0123_alert1: trip-point1 { 2939 temperature = <95000>; 2940 hysteresis = <2000>; 2941 type = "passive"; 2942 }; 2943 2944 cpu0123_crit: cpu_crit { 2945 temperature = <110000>; 2946 hysteresis = <1000>; 2947 type = "critical"; 2948 }; 2949 }; 2950 }; 2951 2952 modem0-thermal { 2953 polling-delay-passive = <0>; 2954 polling-delay = <0>; 2955 thermal-sensors = <&tsens0 13>; 2956 2957 trips { 2958 trip-point0 { 2959 temperature = <115000>; 2960 hysteresis = <5000>; 2961 type = "passive"; 2962 }; 2963 2964 trip-point1 { 2965 temperature = <125000>; 2966 hysteresis = <1000>; 2967 type = "passive"; 2968 }; 2969 }; 2970 }; 2971 2972 display-thermal { 2973 polling-delay-passive = <0>; 2974 polling-delay = <0>; 2975 thermal-sensors = <&tsens0 14>; 2976 2977 trips { 2978 trip-point0 { 2979 temperature = <115000>; 2980 hysteresis = <5000>; 2981 type = "passive"; 2982 }; 2983 2984 trip-point1 { 2985 temperature = <125000>; 2986 hysteresis = <1000>; 2987 type = "passive"; 2988 }; 2989 }; 2990 }; 2991 2992 gpu-thermal { 2993 polling-delay-passive = <0>; 2994 polling-delay = <0>; 2995 thermal-sensors = <&tsens0 15>; 2996 2997 trips { 2998 trip-point0 { 2999 temperature = <115000>; 3000 hysteresis = <5000>; 3001 type = "passive"; 3002 }; 3003 3004 trip-point1 { 3005 temperature = <125000>; 3006 hysteresis = <1000>; 3007 type = "passive"; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 timer { 3014 compatible = "arm,armv8-timer"; 3015 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3016 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3017 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3018 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3019 }; 3020}; 3021