1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Atish Patra <atish.patra@wdc.com> 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/err.h> 11 #include <linux/kvm_host.h> 12 #include <asm/sbi.h> 13 #include <asm/kvm_vcpu_timer.h> 14 #include <asm/kvm_vcpu_sbi.h> 15 16 static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, 17 unsigned long *out_val, 18 struct kvm_cpu_trap *utrap, 19 bool *exit) 20 { 21 ulong hmask; 22 int i, ret = 0; 23 u64 next_cycle; 24 struct kvm_vcpu *rvcpu; 25 struct kvm *kvm = vcpu->kvm; 26 struct kvm_cpu_context *cp = &vcpu->arch.guest_context; 27 28 switch (cp->a7) { 29 case SBI_EXT_0_1_CONSOLE_GETCHAR: 30 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 31 /* 32 * The CONSOLE_GETCHAR/CONSOLE_PUTCHAR SBI calls cannot be 33 * handled in kernel so we forward these to user-space 34 */ 35 kvm_riscv_vcpu_sbi_forward(vcpu, run); 36 *exit = true; 37 break; 38 case SBI_EXT_0_1_SET_TIMER: 39 #if __riscv_xlen == 32 40 next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; 41 #else 42 next_cycle = (u64)cp->a0; 43 #endif 44 ret = kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); 45 break; 46 case SBI_EXT_0_1_CLEAR_IPI: 47 ret = kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_SOFT); 48 break; 49 case SBI_EXT_0_1_SEND_IPI: 50 if (cp->a0) 51 hmask = kvm_riscv_vcpu_unpriv_read(vcpu, false, cp->a0, 52 utrap); 53 else 54 hmask = (1UL << atomic_read(&kvm->online_vcpus)) - 1; 55 if (utrap->scause) 56 break; 57 58 for_each_set_bit(i, &hmask, BITS_PER_LONG) { 59 rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); 60 ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); 61 if (ret < 0) 62 break; 63 } 64 break; 65 case SBI_EXT_0_1_SHUTDOWN: 66 kvm_riscv_vcpu_sbi_system_reset(vcpu, run, 67 KVM_SYSTEM_EVENT_SHUTDOWN, 0); 68 *exit = true; 69 break; 70 case SBI_EXT_0_1_REMOTE_FENCE_I: 71 case SBI_EXT_0_1_REMOTE_SFENCE_VMA: 72 case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID: 73 if (cp->a0) 74 hmask = kvm_riscv_vcpu_unpriv_read(vcpu, false, cp->a0, 75 utrap); 76 else 77 hmask = (1UL << atomic_read(&kvm->online_vcpus)) - 1; 78 if (utrap->scause) 79 break; 80 81 if (cp->a7 == SBI_EXT_0_1_REMOTE_FENCE_I) 82 kvm_riscv_fence_i(vcpu->kvm, 0, hmask); 83 else if (cp->a7 == SBI_EXT_0_1_REMOTE_SFENCE_VMA) { 84 if (cp->a1 == 0 && cp->a2 == 0) 85 kvm_riscv_hfence_vvma_all(vcpu->kvm, 86 0, hmask); 87 else 88 kvm_riscv_hfence_vvma_gva(vcpu->kvm, 89 0, hmask, 90 cp->a1, cp->a2, 91 PAGE_SHIFT); 92 } else { 93 if (cp->a1 == 0 && cp->a2 == 0) 94 kvm_riscv_hfence_vvma_asid_all(vcpu->kvm, 95 0, hmask, 96 cp->a3); 97 else 98 kvm_riscv_hfence_vvma_asid_gva(vcpu->kvm, 99 0, hmask, 100 cp->a1, cp->a2, 101 PAGE_SHIFT, 102 cp->a3); 103 } 104 break; 105 default: 106 ret = -EINVAL; 107 break; 108 } 109 110 return ret; 111 } 112 113 const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = { 114 .extid_start = SBI_EXT_0_1_SET_TIMER, 115 .extid_end = SBI_EXT_0_1_SHUTDOWN, 116 .handler = kvm_sbi_ext_v01_handler, 117 }; 118