1.. SPDX-License-Identifier: GPL-2.0 2 3RISC-V Hardware Probing Interface 4--------------------------------- 5 6The RISC-V hardware probing interface is based around a single syscall, which 7is defined in <asm/hwprobe.h>:: 8 9 struct riscv_hwprobe { 10 __s64 key; 11 __u64 value; 12 }; 13 14 long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, 15 size_t cpu_count, cpu_set_t *cpus, 16 unsigned int flags); 17 18The arguments are split into three groups: an array of key-value pairs, a CPU 19set, and some flags. The key-value pairs are supplied with a count. Userspace 20must prepopulate the key field for each element, and the kernel will fill in the 21value if the key is recognized. If a key is unknown to the kernel, its key field 22will be cleared to -1, and its value set to 0. The CPU set is defined by 23CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will 24be only be valid if all CPUs in the given set have the same value. Otherwise -1 25will be returned. For boolean-like keys, the value returned will be a logical 26AND of the values for the specified CPUs. Usermode can supply NULL for cpus and 270 for cpu_count as a shortcut for all online CPUs. There are currently no flags, 28this value must be zero for future compatibility. 29 30On success 0 is returned, on failure a negative error code is returned. 31 32The following keys are defined: 33 34* :c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``, 35 as defined by the RISC-V privileged architecture specification. 36 37* :c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as 38 defined by the RISC-V privileged architecture specification. 39 40* :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as 41 defined by the RISC-V privileged architecture specification. 42 43* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base 44 user-visible behavior that this kernel supports. The following base user ABIs 45 are defined: 46 47 * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or 48 rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the 49 privileged ISA, with the following known exceptions (more exceptions may be 50 added, but only if it can be demonstrated that the user ABI is not broken): 51 52 * The ``fence.i`` instruction cannot be directly executed by userspace 53 programs (it may still be executed in userspace via a 54 kernel-controlled mechanism such as the vDSO). 55 56* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions 57 that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: 58 base system behavior. 59 60 * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as 61 defined by commit cd20cee ("FMIN/FMAX now implement 62 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. 63 64 * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined 65 by version 2.2 of the RISC-V ISA manual. 66 67 * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by 68 version 1.0 of the RISC-V Vector extension manual. 69 70 * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is 71 supported, as defined in version 1.0 of the Bit-Manipulation ISA 72 extensions. 73 74 * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined 75 in version 1.0 of the Bit-Manipulation ISA extensions. 76 77 * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined 78 in version 1.0 of the Bit-Manipulation ISA extensions. 79 80 * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as 81 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 82 83* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance 84 information about the selected set of processors. 85 86 * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned 87 accesses is unknown. 88 89 * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are 90 emulated via software, either in or below the kernel. These accesses are 91 always extremely slow. 92 93 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower 94 than equivalent byte accesses. Misaligned accesses may be supported 95 directly in hardware, or trapped and emulated by software. 96 97 * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster 98 than equivalent byte accesses. 99 100 * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are 101 not supported at all and will generate a misaligned address fault. 102 103* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which 104 represents the size of the Zicboz block in bytes. 105