1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qdu1000-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen: chosen { }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 CPU0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a55"; 29 reg = <0x0 0x0>; 30 enable-method = "psci"; 31 power-domains = <&CPU_PD0>; 32 power-domain-names = "psci"; 33 qcom,freq-domains = <&cpufreq_hw 0>; 34 next-level-cache = <&L2_0>; 35 L2_0: l2-cache { 36 compatible = "cache"; 37 next-level-cache = <&L3_0>; 38 L3_0: l3-cache { 39 compatible = "cache"; 40 }; 41 }; 42 }; 43 44 CPU1: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a55"; 47 reg = <0x0 0x100>; 48 enable-method = "psci"; 49 power-domains = <&CPU_PD1>; 50 power-domain-names = "psci"; 51 qcom,freq-domains = <&cpufreq_hw 0>; 52 next-level-cache = <&L2_100>; 53 L2_100: l2-cache { 54 compatible = "cache"; 55 next-level-cache = <&L3_0>; 56 }; 57 }; 58 59 CPU2: cpu@200 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x0 0x200>; 63 enable-method = "psci"; 64 power-domains = <&CPU_PD2>; 65 power-domain-names = "psci"; 66 qcom,freq-domains = <&cpufreq_hw 0>; 67 next-level-cache = <&L2_200>; 68 L2_200: l2-cache { 69 compatible = "cache"; 70 next-level-cache = <&L3_0>; 71 }; 72 }; 73 74 CPU3: cpu@300 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a55"; 77 reg = <0x0 0x300>; 78 enable-method = "psci"; 79 power-domains = <&CPU_PD3>; 80 power-domain-names = "psci"; 81 qcom,freq-domains = <&cpufreq_hw 0>; 82 next-level-cache = <&L2_300>; 83 L2_300: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 cpu-map { 90 cluster0 { 91 core0 { 92 cpu = <&CPU0>; 93 }; 94 95 core1 { 96 cpu = <&CPU1>; 97 }; 98 99 core2 { 100 cpu = <&CPU2>; 101 }; 102 103 core3 { 104 cpu = <&CPU3>; 105 }; 106 }; 107 }; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 113 CPU_OFF: cpu-sleep-0 { 114 compatible = "arm,idle-state"; 115 entry-latency-us = <274>; 116 exit-latency-us = <480>; 117 min-residency-us = <3934>; 118 arm,psci-suspend-param = <0x40000004>; 119 local-timer-stop; 120 }; 121 }; 122 123 domain-idle-states { 124 CLUSTER_SLEEP_0: cluster-sleep-0 { 125 compatible = "domain-idle-state"; 126 entry-latency-us = <584>; 127 exit-latency-us = <2332>; 128 min-residency-us = <6118>; 129 arm,psci-suspend-param = <0x41000044>; 130 }; 131 132 CLUSTER_SLEEP_1: cluster-sleep-1 { 133 compatible = "domain-idle-state"; 134 entry-latency-us = <2893>; 135 exit-latency-us = <4023>; 136 min-residency-us = <9987>; 137 arm,psci-suspend-param = <0x41003344>; 138 }; 139 }; 140 141 firmware { 142 scm { 143 compatible = "qcom,scm-qdu1000", "qcom,scm"; 144 }; 145 }; 146 147 mc_virt: interconnect-0 { 148 compatible = "qcom,qdu1000-mc-virt"; 149 qcom,bcm-voters = <&apps_bcm_voter>; 150 #interconnect-cells = <2>; 151 }; 152 153 clk_virt: interconnect-1 { 154 compatible = "qcom,qdu1000-clk-virt"; 155 qcom,bcm-voters = <&apps_bcm_voter>; 156 #interconnect-cells = <2>; 157 }; 158 159 memory@80000000 { 160 device_type = "memory"; 161 /* We expect the bootloader to fill in the size */ 162 reg = <0x0 0x80000000 0x0 0x0>; 163 }; 164 165 pmu { 166 compatible = "arm,armv8-pmuv3"; 167 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 168 }; 169 170 psci { 171 compatible = "arm,psci-1.0"; 172 method = "smc"; 173 174 CPU_PD0: power-domain-cpu0 { 175 #power-domain-cells = <0>; 176 power-domains = <&CLUSTER_PD>; 177 domain-idle-states = <&CPU_OFF>; 178 }; 179 180 CPU_PD1: power-domain-cpu1 { 181 #power-domain-cells = <0>; 182 power-domains = <&CLUSTER_PD>; 183 domain-idle-states = <&CPU_OFF>; 184 }; 185 186 CPU_PD2: power-domain-cpu2 { 187 #power-domain-cells = <0>; 188 power-domains = <&CLUSTER_PD>; 189 domain-idle-states = <&CPU_OFF>; 190 }; 191 192 CPU_PD3: power-domain-cpu3 { 193 #power-domain-cells = <0>; 194 power-domains = <&CLUSTER_PD>; 195 domain-idle-states = <&CPU_OFF>; 196 }; 197 198 CLUSTER_PD: power-domain-cluster { 199 #power-domain-cells = <0>; 200 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; 201 }; 202 }; 203 204 reserved_memory: reserved-memory { 205 #address-cells = <2>; 206 #size-cells = <2>; 207 ranges; 208 209 hyp_mem: hyp@80000000 { 210 reg = <0x0 0x80000000 0x0 0x600000>; 211 no-map; 212 }; 213 214 xbl_dt_log_mem: xbl-dt-log@80600000 { 215 reg = <0x0 0x80600000 0x0 0x40000>; 216 no-map; 217 }; 218 219 xbl_ramdump_mem: xbl-ramdump@80640000 { 220 reg = <0x0 0x80640000 0x0 0x1c0000>; 221 no-map; 222 }; 223 224 aop_image_mem: aop-image@80800000 { 225 reg = <0x0 0x80800000 0x0 0x60000>; 226 no-map; 227 }; 228 229 aop_cmd_db_mem: aop-cmd-db@80860000 { 230 compatible = "qcom,cmd-db"; 231 reg = <0x0 0x80860000 0x0 0x20000>; 232 no-map; 233 }; 234 235 aop_config_mem: aop-config@80880000 { 236 reg = <0x0 0x80880000 0x0 0x20000>; 237 no-map; 238 }; 239 240 tme_crash_dump_mem: tme-crash-dump@808a0000 { 241 reg = <0x0 0x808a0000 0x0 0x40000>; 242 no-map; 243 }; 244 245 tme_log_mem: tme-log@808e0000 { 246 reg = <0x0 0x808e0000 0x0 0x4000>; 247 no-map; 248 }; 249 250 uefi_log_mem: uefi-log@808e4000 { 251 reg = <0x0 0x808e4000 0x0 0x10000>; 252 no-map; 253 }; 254 255 smem_mem: smem@80900000 { 256 compatible = "qcom,smem"; 257 reg = <0x0 0x80900000 0x0 0x200000>; 258 no-map; 259 hwlocks = <&tcsr_mutex 3>; 260 }; 261 262 cpucp_fw_mem: cpucp-fw@80b00000 { 263 reg = <0x0 0x80b00000 0x0 0x100000>; 264 no-map; 265 }; 266 267 xbl_sc_mem: memory@80c00000 { 268 reg = <0x0 0x80c00000 0x0 0x40000>; 269 no-map; 270 }; 271 272 tz_stat_mem: tz-stat@81d00000 { 273 reg = <0x0 0x81d00000 0x0 0x100000>; 274 no-map; 275 }; 276 277 tags_mem: tags@81e00000 { 278 reg = <0x0 0x81e00000 0x0 0x500000>; 279 no-map; 280 }; 281 282 qtee_mem: qtee@82300000 { 283 reg = <0x0 0x82300000 0x0 0x500000>; 284 no-map; 285 }; 286 287 ta_mem: ta@82800000 { 288 reg = <0x0 0x82800000 0x0 0xa00000>; 289 no-map; 290 }; 291 292 fs1_mem: fs1@83200000 { 293 reg = <0x0 0x83200000 0x0 0x400000>; 294 no-map; 295 }; 296 297 fs2_mem: fs2@83600000 { 298 reg = <0x0 0x83600000 0x0 0x400000>; 299 no-map; 300 }; 301 302 fs3_mem: fs3@83a00000 { 303 reg = <0x0 0x83a00000 0x0 0x400000>; 304 no-map; 305 }; 306 307 /* Linux kernel image is loaded at 0x83e00000 */ 308 309 ipa_fw_mem: ipa-fw@8be00000 { 310 reg = <0x0 0x8be00000 0x0 0x10000>; 311 no-map; 312 }; 313 314 ipa_gsi_mem: ipa-gsi@8be10000 { 315 reg = <0x0 0x8be10000 0x0 0x14000>; 316 no-map; 317 }; 318 319 mpss_mem: mpss@8c000000 { 320 reg = <0x0 0x8c000000 0x0 0x12c00000>; 321 no-map; 322 }; 323 324 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 { 325 reg = <0x0 0x9ec00000 0x0 0x80000>; 326 no-map; 327 }; 328 329 tenx_mem: tenx@a0000000 { 330 reg = <0x0 0xa0000000 0x0 0x19600000>; 331 no-map; 332 }; 333 334 oem_tenx_mem: oem-tenx@b9600000 { 335 reg = <0x0 0xb9600000 0x0 0x6a00000>; 336 no-map; 337 }; 338 339 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 { 340 reg = <0x0 0xc0000000 0x0 0x3200000>; 341 no-map; 342 }; 343 344 ipa_buffer_mem: ipa-buffer@c3200000 { 345 reg = <0x0 0xc3200000 0x0 0x12c00000>; 346 no-map; 347 }; 348 }; 349 350 soc: soc@0 { 351 compatible = "simple-bus"; 352 #address-cells = <2>; 353 #size-cells = <2>; 354 ranges = <0 0 0 0 0x10 0>; 355 dma-ranges = <0 0 0 0 0x10 0>; 356 357 gcc: clock-controller@80000 { 358 compatible = "qcom,qdu1000-gcc"; 359 reg = <0x0 0x80000 0x0 0x1f4200>; 360 clocks = <&rpmhcc RPMH_CXO_CLK>, 361 <&sleep_clk>, 362 <0>, 363 <0>, 364 <0>; 365 #clock-cells = <1>; 366 #reset-cells = <1>; 367 #power-domain-cells = <1>; 368 }; 369 370 gpi_dma0: dma-controller@900000 { 371 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; 372 reg = <0x0 0x900000 0x0 0x60000>; 373 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 385 dma-channels = <12>; 386 dma-channel-mask = <0x3f>; 387 iommus = <&apps_smmu 0xf6 0x0>; 388 #dma-cells = <3>; 389 }; 390 391 qupv3_id_0: geniqup@9c0000 { 392 compatible = "qcom,geni-se-qup"; 393 reg = <0x0 0x9c0000 0x0 0x2000>; 394 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 395 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 396 clock-names = "m-ahb", "s-ahb"; 397 iommus = <&apps_smmu 0xe3 0x0>; 398 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 399 &clk_virt SLAVE_QUP_CORE_0 0>; 400 interconnect-names = "qup-core"; 401 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges; 405 status = "disabled"; 406 407 uart0: serial@980000 { 408 compatible = "qcom,geni-uart"; 409 reg = <0x0 0x980000 0x0 0x4000>; 410 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 411 clock-names = "se"; 412 pinctrl-0 = <&qup_uart0_default>; 413 pinctrl-names = "default"; 414 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 i2c1: i2c@984000 { 421 compatible = "qcom,geni-i2c"; 422 reg = <0x0 0x984000 0x0 0x4000>; 423 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 424 clock-names = "se"; 425 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 426 pinctrl-0 = <&qup_i2c1_data_clk>; 427 pinctrl-names = "default"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 status = "disabled"; 431 }; 432 433 spi1: spi@984000 { 434 compatible = "qcom,geni-spi"; 435 reg = <0x0 0x984000 0x0 0x4000>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 440 clock-names = "se"; 441 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 442 pinctrl-names = "default"; 443 status = "disabled"; 444 }; 445 446 i2c2: i2c@988000 { 447 compatible = "qcom,geni-i2c"; 448 reg = <0x0 0x988000 0x0 0x4000>; 449 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 450 clock-names = "se"; 451 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 452 pinctrl-0 = <&qup_i2c2_data_clk>; 453 pinctrl-names = "default"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 }; 458 459 spi2: spi@988000 { 460 compatible = "qcom,geni-spi"; 461 reg = <0x0 0x988000 0x0 0x4000>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 466 clock-names = "se"; 467 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 468 pinctrl-names = "default"; 469 status = "disabled"; 470 }; 471 472 i2c3: i2c@98c000 { 473 compatible = "qcom,geni-i2c"; 474 reg = <0x0 0x98c000 0x0 0x4000>; 475 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 476 clock-names = "se"; 477 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 478 pinctrl-0 = <&qup_i2c3_data_clk>; 479 pinctrl-names = "default"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 spi3: spi@98c000 { 486 compatible = "qcom,geni-spi"; 487 reg = <0x0 0x98c000 0x0 0x4000>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 492 clock-names = "se"; 493 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 494 pinctrl-names = "default"; 495 status = "disabled"; 496 }; 497 498 i2c4: i2c@990000 { 499 compatible = "qcom,geni-i2c"; 500 reg = <0x0 0x990000 0x0 0x4000>; 501 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 502 clock-names = "se"; 503 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 504 pinctrl-0 = <&qup_i2c4_data_clk>; 505 pinctrl-names = "default"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 spi4: spi@990000 { 512 compatible = "qcom,geni-spi"; 513 reg = <0x0 0x990000 0x0 0x4000>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 518 clock-names = "se"; 519 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 520 pinctrl-names = "default"; 521 status = "disabled"; 522 }; 523 524 i2c5: i2c@994000 { 525 compatible = "qcom,geni-i2c"; 526 reg = <0x0 0x994000 0x0 0x4000>; 527 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 528 clock-names = "se"; 529 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 530 pinctrl-0 = <&qup_i2c5_data_clk>; 531 pinctrl-names = "default"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 status = "disabled"; 535 }; 536 537 spi5: spi@994000 { 538 compatible = "qcom,geni-spi"; 539 reg = <0x0 0x994000 0x0 0x4000>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 544 clock-names = "se"; 545 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 546 pinctrl-names = "default"; 547 status = "disabled"; 548 }; 549 550 i2c6: i2c@998000 { 551 compatible = "qcom,geni-i2c"; 552 reg = <0x0 0x998000 0x0 0x4000>; 553 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 554 clock-names = "se"; 555 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 556 pinctrl-0 = <&qup_i2c6_data_clk>; 557 pinctrl-names = "default"; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 563 spi6: spi@998000 { 564 compatible = "qcom,geni-spi"; 565 reg = <0x0 0x998000 0x0 0x4000>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 570 clock-names = "se"; 571 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 572 pinctrl-names = "default"; 573 status = "disabled"; 574 }; 575 576 uart7: serial@99c000 { 577 compatible = "qcom,geni-debug-uart"; 578 reg = <0x0 0x99c000 0x0 0x4000>; 579 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 580 clock-names = "se"; 581 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 582 pinctrl-names = "default"; 583 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 }; 589 590 gpi_dma1: dma-controller@a00000 { 591 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; 592 reg = <0x0 0xa00000 0x0 0x60000>; 593 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 605 dma-channels = <12>; 606 dma-channel-mask = <0x3f>; 607 iommus = <&apps_smmu 0x116 0x0>; 608 #dma-cells = <3>; 609 }; 610 611 qupv3_id_1: geniqup@ac0000 { 612 compatible = "qcom,geni-se-qup"; 613 reg = <0x0 0xac0000 0x0 0x2000>; 614 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 615 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 616 clock-names = "m-ahb", "s-ahb"; 617 iommus = <&apps_smmu 0x103 0x0>; 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges; 621 status = "disabled"; 622 623 uart8: serial@a80000 { 624 compatible = "qcom,geni-uart"; 625 reg = <0x0 0xa80000 0x0 0x4000>; 626 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 627 clock-names = "se"; 628 pinctrl-0 = <&qup_uart8_default>; 629 pinctrl-names = "default"; 630 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 status = "disabled"; 634 }; 635 636 i2c9: i2c@a84000 { 637 compatible = "qcom,geni-i2c"; 638 reg = <0x0 0xa84000 0x0 0x4000>; 639 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 640 clock-names = "se"; 641 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 642 pinctrl-0 = <&qup_i2c9_data_clk>; 643 pinctrl-names = "default"; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 status = "disabled"; 647 }; 648 649 spi9: spi@a84000 { 650 compatible = "qcom,geni-spi"; 651 reg = <0x0 0xa84000 0x0 0x4000>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 656 clock-names = "se"; 657 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 658 pinctrl-names = "default"; 659 status = "disabled"; 660 }; 661 662 i2c10: i2c@a88000 { 663 compatible = "qcom,geni-i2c"; 664 reg = <0x0 0xa88000 0x0 0x4000>; 665 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 666 clock-names = "se"; 667 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 668 pinctrl-0 = <&qup_i2c10_data_clk>; 669 pinctrl-names = "default"; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 status = "disabled"; 673 }; 674 675 spi10: spi@a88000 { 676 compatible = "qcom,geni-spi"; 677 reg = <0x0 0xa88000 0x0 0x4000>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 682 clock-names = "se"; 683 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 684 pinctrl-names = "default"; 685 status = "disabled"; 686 }; 687 688 i2c11: i2c@a8c000 { 689 compatible = "qcom,geni-i2c"; 690 reg = <0x0 0xa8c000 0x0 0x4000>; 691 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 692 clock-names = "se"; 693 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 694 pinctrl-0 = <&qup_i2c11_data_clk>; 695 pinctrl-names = "default"; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 status = "disabled"; 699 }; 700 701 spi11: spi@a8c000 { 702 compatible = "qcom,geni-spi"; 703 reg = <0x0 0xa8c000 0x0 0x4000>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 708 clock-names = "se"; 709 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 710 pinctrl-names = "default"; 711 status = "disabled"; 712 }; 713 714 i2c12: i2c@a90000 { 715 compatible = "qcom,geni-i2c"; 716 reg = <0x0 0xa90000 0x0 0x4000>; 717 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 718 clock-names = "se"; 719 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 720 pinctrl-0 = <&qup_i2c12_data_clk>; 721 pinctrl-names = "default"; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 status = "disabled"; 725 }; 726 727 spi12: spi@a90000 { 728 compatible = "qcom,geni-spi"; 729 reg = <0x0 0xa90000 0x0 0x4000>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 734 clock-names = "se"; 735 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 736 pinctrl-names = "default"; 737 status = "disabled"; 738 }; 739 740 i2c13: i2c@a94000 { 741 compatible = "qcom,geni-i2c"; 742 reg = <0x0 0xa94000 0x0 0x4000>; 743 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 744 clock-names = "se"; 745 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 746 pinctrl-0 = <&qup_i2c13_data_clk>; 747 pinctrl-names = "default"; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 status = "disabled"; 751 }; 752 753 uart13: serial@a94000 { 754 compatible = "qcom,geni-uart"; 755 reg = <0x0 0xa94000 0x0 0x4000>; 756 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 757 clock-names = "se"; 758 pinctrl-0 = <&qup_uart13_default>; 759 pinctrl-names = "default"; 760 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 766 spi13: spi@a94000 { 767 compatible = "qcom,geni-spi"; 768 reg = <0x0 0xa94000 0x0 0x4000>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 773 clock-names = "se"; 774 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 775 pinctrl-names = "default"; 776 status = "disabled"; 777 }; 778 779 i2c14: i2c@a98000 { 780 compatible = "qcom,geni-i2c"; 781 reg = <0x0 0xa98000 0x0 0x4000>; 782 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 783 clock-names = "se"; 784 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 785 pinctrl-0 = <&qup_i2c14_data_clk>; 786 pinctrl-names = "default"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 spi14: spi@a98000 { 793 compatible = "qcom,geni-spi"; 794 reg = <0x0 0xa98000 0x0 0x4000>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 799 clock-names = "se"; 800 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 801 pinctrl-names = "default"; 802 status = "disabled"; 803 }; 804 805 i2c15: i2c@a9c000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0x0 0xa9c000 0x0 0x4000>; 808 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 809 clock-names = "se"; 810 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 811 pinctrl-0 = <&qup_i2c15_data_clk>; 812 pinctrl-names = "default"; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 status = "disabled"; 816 }; 817 818 spi15: spi@a9c000 { 819 compatible = "qcom,geni-spi"; 820 reg = <0x0 0xa9c000 0x0 0x4000>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 825 clock-names = "se"; 826 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 827 pinctrl-names = "default"; 828 status = "disabled"; 829 }; 830 }; 831 832 system_noc: interconnect@1640000 { 833 compatible = "qcom,qdu1000-system-noc"; 834 reg = <0x0 0x1640000 0x0 0x45080>; 835 qcom,bcm-voters = <&apps_bcm_voter>; 836 #interconnect-cells = <2>; 837 }; 838 839 tcsr_mutex: hwlock@1f40000 { 840 compatible = "qcom,tcsr-mutex"; 841 reg = <0x0 0x1f40000 0x0 0x20000>; 842 #hwlock-cells = <1>; 843 }; 844 845 pdc: interrupt-controller@b220000 { 846 compatible = "qcom,qdu1000-pdc", "qcom,pdc"; 847 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 848 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 849 <94 609 31>, <125 63 1>; 850 #interrupt-cells = <2>; 851 interrupt-parent = <&intc>; 852 interrupt-controller; 853 }; 854 855 spmi_bus: spmi@c400000 { 856 compatible = "qcom,spmi-pmic-arb"; 857 reg = <0x0 0xc400000 0x0 0x3000>, 858 <0x0 0xc500000 0x0 0x400000>, 859 <0x0 0xc440000 0x0 0x80000>, 860 <0x0 0xc4c0000 0x0 0x10000>, 861 <0x0 0xc42d000 0x0 0x4000>; 862 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 863 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-names = "periph_irq"; 865 qcom,ee = <0>; 866 qcom,channel = <0>; 867 #address-cells = <2>; 868 #size-cells = <0>; 869 interrupt-controller; 870 #interrupt-cells = <4>; 871 }; 872 873 tlmm: pinctrl@f000000 { 874 compatible = "qcom,qdu1000-tlmm"; 875 reg = <0x0 0xf000000 0x0 0x1000000>; 876 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 877 gpio-controller; 878 #gpio-cells = <2>; 879 interrupt-controller; 880 #interrupt-cells = <2>; 881 gpio-ranges = <&tlmm 0 0 151>; 882 wakeup-parent = <&pdc>; 883 884 qup_uart0_default: qup-uart0-default-state { 885 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 886 function = "qup00"; 887 }; 888 889 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 890 pins = "gpio10", "gpio11"; 891 function = "qup01"; 892 }; 893 894 qup_spi1_data_clk: qup-spi1-data-clk-state { 895 pins = "gpio10", "gpio11", "gpio12"; 896 function = "qup01"; 897 }; 898 899 qup_spi1_cs: qup-spi1-cs-state { 900 pins = "gpio13"; 901 function = "gpio"; 902 }; 903 904 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 905 pins = "gpio12", "gpio13"; 906 function = "qup02"; 907 }; 908 909 qup_spi2_data_clk: qup-spi2-data-clk-state { 910 pins = "gpio12", "gpio13", "gpio10"; 911 function = "qup02"; 912 }; 913 914 qup_spi2_cs: qup-spi2-cs-state { 915 pins = "gpio11"; 916 function = "gpio"; 917 }; 918 919 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 920 pins = "gpio14", "gpio15"; 921 function = "qup03"; 922 }; 923 924 qup_spi3_data_clk: qup-spi3-data-clk-state { 925 pins = "gpio14", "gpio15", "gpio16"; 926 function = "qup03"; 927 }; 928 929 qup_spi3_cs: qup-spi3-cs-state { 930 pins = "gpio17"; 931 function = "gpio"; 932 }; 933 934 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 935 pins = "gpio16", "gpio17"; 936 function = "qup04"; 937 }; 938 939 qup_spi4_data_clk: qup-spi4-data-clk-state { 940 pins = "gpio16", "gpio17", "gpio14"; 941 function = "qup04"; 942 }; 943 944 qup_spi4_cs: qup-spi4-cs-state { 945 pins = "gpio15"; 946 function = "gpio"; 947 }; 948 949 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 950 pins = "gpio130", "gpio131"; 951 function = "qup05"; 952 }; 953 954 qup_spi5_data_clk: qup-spi5-data-clk-state { 955 pins = "gpio130", "gpio131", "gpio132"; 956 function = "qup05"; 957 }; 958 959 qup_spi5_cs: qup-spi5-cs-state { 960 pins = "gpio133"; 961 function = "gpio"; 962 }; 963 964 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 965 pins = "gpio132", "gpio133"; 966 function = "qup06"; 967 }; 968 969 qup_spi6_data_clk: qup-spi6-data-clk-state { 970 pins = "gpio132", "gpio133", "gpio130"; 971 function = "qup06"; 972 }; 973 974 qup_spi6_cs: qup-spi6-cs-state { 975 pins = "gpio131"; 976 function = "gpio"; 977 }; 978 979 qup_uart7_rx: qup-uart7-rx-state { 980 pins = "gpio135"; 981 function = "qup07"; 982 }; 983 984 qup_uart7_tx: qup-uart7-tx-state { 985 pins = "gpio134"; 986 function = "qup07"; 987 }; 988 989 qup_uart8_default: qup-uart8-default-state { 990 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 991 function = "qup10"; 992 }; 993 994 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 995 pins = "gpio22", "gpio23"; 996 function = "qup11"; 997 }; 998 999 qup_spi9_data_clk: qup-spi9-data-clk-state { 1000 pins = "gpio22", "gpio23", "gpio24"; 1001 function = "qup11"; 1002 }; 1003 1004 qup_spi9_cs: qup-spi9-cs-state { 1005 pins = "gpio25"; 1006 function = "gpio"; 1007 }; 1008 1009 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 1010 pins = "gpio24", "gpio25"; 1011 function = "qup12"; 1012 }; 1013 1014 qup_spi10_data_clk: qup-spi10-data-clk-state { 1015 pins = "gpio24", "gpio25", "gpio22"; 1016 function = "qup12"; 1017 }; 1018 1019 qup_spi10_cs: qup-spi10-cs-state { 1020 pins = "gpio23"; 1021 function = "gpio"; 1022 }; 1023 1024 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 1025 pins = "gpio26", "gpio27"; 1026 function = "qup13"; 1027 }; 1028 1029 qup_spi11_data_clk: qup-spi11-data-clk-state { 1030 pins = "gpio26", "gpio27", "gpio28"; 1031 function = "qup13"; 1032 }; 1033 1034 qup_spi11_cs: qup-spi11-cs-state { 1035 pins = "gpio29"; 1036 function = "gpio"; 1037 }; 1038 1039 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 1040 pins = "gpio28", "gpio29"; 1041 function = "qup14"; 1042 }; 1043 1044 qup_spi12_data_clk: qup-spi12-data-clk-state { 1045 pins = "gpio28", "gpio29", "gpio26"; 1046 function = "qup14"; 1047 }; 1048 1049 qup_spi12_cs: qup-spi12-cs-state { 1050 pins = "gpio27"; 1051 function = "gpio"; 1052 }; 1053 1054 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 1055 pins = "gpio30", "gpio31"; 1056 function = "qup15"; 1057 }; 1058 1059 qup_spi13_data_clk: qup-spi13-data-clk-state { 1060 pins = "gpio30", "gpio31", "gpio32"; 1061 function = "qup15"; 1062 }; 1063 1064 qup_spi13_cs: qup-spi13-cs-state { 1065 pins = "gpio33"; 1066 function = "gpio"; 1067 }; 1068 1069 qup_uart13_default: qup-uart13-default-state { 1070 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 1071 function = "qup15"; 1072 }; 1073 1074 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 1075 pins = "gpio34", "gpio35"; 1076 function = "qup16"; 1077 }; 1078 1079 qup_spi14_data_clk: qup-spi14-data-clk-state { 1080 pins = "gpio34", "gpio35", "gpio36"; 1081 function = "qup16"; 1082 }; 1083 1084 qup_spi14_cs: qup-spi14-cs-state { 1085 pins = "gpio37", "gpio38"; 1086 function = "gpio"; 1087 }; 1088 1089 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 1090 pins = "gpio40", "gpio41"; 1091 function = "qup17"; 1092 }; 1093 1094 qup_spi15_data_clk: qup-spi15-data-clk-state { 1095 pins = "gpio40", "gpio41", "gpio30"; 1096 function = "qup17"; 1097 }; 1098 1099 qup_spi15_cs: qup-spi15-cs-state { 1100 pins = "gpio31"; 1101 function = "gpio"; 1102 }; 1103 }; 1104 1105 apps_smmu: iommu@15000000 { 1106 compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500"; 1107 reg = <0x0 0x15000000 0x0 0x100000>; 1108 #iommu-cells = <2>; 1109 #global-interrupts = <2>; 1110 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1159 }; 1160 1161 intc: interrupt-controller@17200000 { 1162 compatible = "arm,gic-v3"; 1163 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ 1164 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ 1165 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1166 #interrupt-cells = <3>; 1167 interrupt-controller; 1168 #redistributor-regions = <1>; 1169 redistributor-stride = <0x0 0x20000>; 1170 }; 1171 1172 timer@17420000 { 1173 compatible = "arm,armv7-timer-mem"; 1174 reg = <0x0 0x17420000 0x0 0x1000>; 1175 #address-cells = <1>; 1176 #size-cells = <1>; 1177 ranges = <0x0 0x0 0x0 0x20000000>; 1178 1179 frame@17421000 { 1180 reg = <0x17421000 0x1000>, 1181 <0x17422000 0x1000>; 1182 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1184 frame-number = <0>; 1185 }; 1186 1187 frame@17423000 { 1188 reg = <0x17423000 0x1000>; 1189 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1190 frame-number = <1>; 1191 status = "disabled"; 1192 }; 1193 1194 frame@17425000 { 1195 reg = <0x17425000 0x1000>, 1196 <0x17426000 0x1000>; 1197 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1198 frame-number = <2>; 1199 status = "disabled"; 1200 }; 1201 1202 frame@17427000 { 1203 reg = <0x17427000 0x1000>; 1204 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1205 frame-number = <3>; 1206 status = "disabled"; 1207 }; 1208 1209 frame@17429000 { 1210 reg = <0x17429000 0x1000>; 1211 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1212 frame-number = <4>; 1213 status = "disabled"; 1214 }; 1215 1216 frame@1742b000 { 1217 reg = <0x1742b000 0x1000>; 1218 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1219 frame-number = <5>; 1220 status = "disabled"; 1221 }; 1222 1223 frame@1742d000 { 1224 reg = <0x1742d000 0x1000>; 1225 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1226 frame-number = <6>; 1227 status = "disabled"; 1228 }; 1229 }; 1230 1231 apps_rsc: rsc@17a00000 { 1232 compatible = "qcom,rpmh-rsc"; 1233 reg = <0x0 0x17a00000 0x0 0x10000>, 1234 <0x0 0x17a10000 0x0 0x10000>, 1235 <0x0 0x17a20000 0x0 0x10000>; 1236 reg-names = "drv-0", "drv-1", "drv-2"; 1237 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1240 qcom,tcs-offset = <0xd00>; 1241 qcom,drv-id = <2>; 1242 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1243 <WAKE_TCS 3>, <CONTROL_TCS 0>; 1244 label = "apps_rsc"; 1245 1246 apps_bcm_voter: bcm-voter { 1247 compatible = "qcom,bcm-voter"; 1248 }; 1249 1250 rpmhcc: clock-controller { 1251 compatible = "qcom,qdu1000-rpmh-clk"; 1252 clocks = <&xo_board>; 1253 clock-names = "xo"; 1254 #clock-cells = <1>; 1255 }; 1256 1257 rpmhpd: power-controller { 1258 compatible = "qcom,qdu1000-rpmhpd"; 1259 #power-domain-cells = <1>; 1260 operating-points-v2 = <&rpmhpd_opp_table>; 1261 1262 rpmhpd_opp_table: opp-table { 1263 compatible = "operating-points-v2"; 1264 1265 rpmhpd_opp_ret: opp1 { 1266 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1267 }; 1268 1269 rpmhpd_opp_min_svs: opp2 { 1270 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1271 }; 1272 1273 rpmhpd_opp_low_svs: opp3 { 1274 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1275 }; 1276 1277 rpmhpd_opp_svs: opp4 { 1278 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1279 }; 1280 1281 rpmhpd_opp_svs_l1: opp5 { 1282 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1283 }; 1284 1285 rpmhpd_opp_nom: opp6 { 1286 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1287 }; 1288 1289 rpmhpd_opp_nom_l1: opp7 { 1290 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1291 }; 1292 1293 rpmhpd_opp_nom_l2: opp8 { 1294 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1295 }; 1296 1297 rpmhpd_opp_turbo: opp9 { 1298 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1299 }; 1300 1301 rpmhpd_opp_turbo_l1: opp10 { 1302 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1303 }; 1304 }; 1305 }; 1306 }; 1307 1308 cpufreq_hw: cpufreq@17d90000 { 1309 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss"; 1310 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>; 1311 reg-names = "freq-domain0", "freq-domain1"; 1312 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1313 clock-names = "xo", "alternate"; 1314 #freq-domain-cells = <1>; 1315 }; 1316 1317 gem_noc: interconnect@19100000 { 1318 compatible = "qcom,qdu1000-gem-noc"; 1319 reg = <0x0 0x19100000 0x0 0xB8080>; 1320 qcom,bcm-voters = <&apps_bcm_voter>; 1321 #interconnect-cells = <2>; 1322 }; 1323 }; 1324 1325 timer { 1326 compatible = "arm,armv8-timer"; 1327 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1328 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1329 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1330 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1331 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1332 }; 1333}; 1334