1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef __LINUX_MTD_SFDP_H 8 #define __LINUX_MTD_SFDP_H 9 10 /* SFDP revisions */ 11 #define SFDP_JESD216_MAJOR 1 12 #define SFDP_JESD216_MINOR 0 13 #define SFDP_JESD216A_MINOR 5 14 #define SFDP_JESD216B_MINOR 6 15 16 /* SFDP DWORDS are indexed from 1 but C arrays are indexed from 0. */ 17 #define SFDP_DWORD(i) ((i) - 1) 18 19 /* Basic Flash Parameter Table */ 20 21 /* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. */ 22 #define BFPT_DWORD_MAX 20 23 24 struct sfdp_bfpt { 25 u32 dwords[BFPT_DWORD_MAX]; 26 }; 27 28 /* The first version of JESD216 defined only 9 DWORDs. */ 29 #define BFPT_DWORD_MAX_JESD216 9 30 #define BFPT_DWORD_MAX_JESD216B 16 31 32 /* 1st DWORD. */ 33 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 34 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 35 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 36 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 37 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 38 #define BFPT_DWORD1_DTR BIT(19) 39 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 40 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 41 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 42 43 /* 5th DWORD. */ 44 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 45 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 46 47 /* 11th DWORD. */ 48 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 49 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 50 51 /* 15th DWORD. */ 52 53 /* 54 * (from JESD216 rev B) 55 * Quad Enable Requirements (QER): 56 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 57 * reads based on instruction. DQ3/HOLD# functions are hold during 58 * instruction phase. 59 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 60 * two data bytes where bit 1 of the second byte is one. 61 * [...] 62 * Writing only one byte to the status register has the side-effect of 63 * clearing status register 2, including the QE bit. The 100b code is 64 * used if writing one byte to the status register does not modify 65 * status register 2. 66 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 67 * one data byte where bit 6 is one. 68 * [...] 69 * - 011b: QE is bit 7 of status register 2. It is set via Write status 70 * register 2 instruction 3Eh with one data byte where bit 7 is one. 71 * [...] 72 * The status register 2 is read using instruction 3Fh. 73 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 74 * two data bytes where bit 1 of the second byte is one. 75 * [...] 76 * In contrast to the 001b code, writing one byte to the status 77 * register does not modify status register 2. 78 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 79 * Read Status instruction 05h. Status register2 is read using 80 * instruction 35h. QE is set via Write Status instruction 01h with 81 * two data bytes where bit 1 of the second byte is one. 82 * [...] 83 */ 84 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 85 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 86 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 87 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 88 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 89 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 90 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 91 92 #define BFPT_DWORD16_SWRST_EN_RST BIT(12) 93 94 #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) 95 #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ 96 #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ 97 #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ 98 #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ 99 100 struct sfdp_parameter_header { 101 u8 id_lsb; 102 u8 minor; 103 u8 major; 104 u8 length; /* in double words */ 105 u8 parameter_table_pointer[3]; /* byte address */ 106 u8 id_msb; 107 }; 108 109 #endif /* __LINUX_MTD_SFDP_H */ 110