1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/iopoll.h> 9 #include <linux/irq.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/phy/phy.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset.h> 15 16 #include <video/mipi_display.h> 17 #include <video/videomode.h> 18 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_bridge.h> 21 #include <drm/drm_bridge_connector.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_simple_kms_helper.h> 28 29 #include "mtk_disp_drv.h" 30 #include "mtk_drm_ddp_comp.h" 31 32 #define DSI_START 0x00 33 34 #define DSI_INTEN 0x08 35 36 #define DSI_INTSTA 0x0c 37 #define LPRX_RD_RDY_INT_FLAG BIT(0) 38 #define CMD_DONE_INT_FLAG BIT(1) 39 #define TE_RDY_INT_FLAG BIT(2) 40 #define VM_DONE_INT_FLAG BIT(3) 41 #define EXT_TE_RDY_INT_FLAG BIT(4) 42 #define DSI_BUSY BIT(31) 43 44 #define DSI_CON_CTRL 0x10 45 #define DSI_RESET BIT(0) 46 #define DSI_EN BIT(1) 47 #define DPHY_RESET BIT(2) 48 49 #define DSI_MODE_CTRL 0x14 50 #define MODE (3) 51 #define CMD_MODE 0 52 #define SYNC_PULSE_MODE 1 53 #define SYNC_EVENT_MODE 2 54 #define BURST_MODE 3 55 #define FRM_MODE BIT(16) 56 #define MIX_MODE BIT(17) 57 58 #define DSI_TXRX_CTRL 0x18 59 #define VC_NUM BIT(1) 60 #define LANE_NUM (0xf << 2) 61 #define DIS_EOT BIT(6) 62 #define NULL_EN BIT(7) 63 #define TE_FREERUN BIT(8) 64 #define EXT_TE_EN BIT(9) 65 #define EXT_TE_EDGE BIT(10) 66 #define MAX_RTN_SIZE (0xf << 12) 67 #define HSTX_CKLP_EN BIT(16) 68 69 #define DSI_PSCTRL 0x1c 70 #define DSI_PS_WC 0x3fff 71 #define DSI_PS_SEL (3 << 16) 72 #define PACKED_PS_16BIT_RGB565 (0 << 16) 73 #define LOOSELY_PS_18BIT_RGB666 (1 << 16) 74 #define PACKED_PS_18BIT_RGB666 (2 << 16) 75 #define PACKED_PS_24BIT_RGB888 (3 << 16) 76 77 #define DSI_VSA_NL 0x20 78 #define DSI_VBP_NL 0x24 79 #define DSI_VFP_NL 0x28 80 #define DSI_VACT_NL 0x2C 81 #define DSI_SIZE_CON 0x38 82 #define DSI_HSA_WC 0x50 83 #define DSI_HBP_WC 0x54 84 #define DSI_HFP_WC 0x58 85 86 #define DSI_CMDQ_SIZE 0x60 87 #define CMDQ_SIZE 0x3f 88 89 #define DSI_HSTX_CKL_WC 0x64 90 91 #define DSI_RX_DATA0 0x74 92 #define DSI_RX_DATA1 0x78 93 #define DSI_RX_DATA2 0x7c 94 #define DSI_RX_DATA3 0x80 95 96 #define DSI_RACK 0x84 97 #define RACK BIT(0) 98 99 #define DSI_PHY_LCCON 0x104 100 #define LC_HS_TX_EN BIT(0) 101 #define LC_ULPM_EN BIT(1) 102 #define LC_WAKEUP_EN BIT(2) 103 104 #define DSI_PHY_LD0CON 0x108 105 #define LD0_HS_TX_EN BIT(0) 106 #define LD0_ULPM_EN BIT(1) 107 #define LD0_WAKEUP_EN BIT(2) 108 109 #define DSI_PHY_TIMECON0 0x110 110 #define LPX (0xff << 0) 111 #define HS_PREP (0xff << 8) 112 #define HS_ZERO (0xff << 16) 113 #define HS_TRAIL (0xff << 24) 114 115 #define DSI_PHY_TIMECON1 0x114 116 #define TA_GO (0xff << 0) 117 #define TA_SURE (0xff << 8) 118 #define TA_GET (0xff << 16) 119 #define DA_HS_EXIT (0xff << 24) 120 121 #define DSI_PHY_TIMECON2 0x118 122 #define CONT_DET (0xff << 0) 123 #define CLK_ZERO (0xff << 16) 124 #define CLK_TRAIL (0xff << 24) 125 126 #define DSI_PHY_TIMECON3 0x11c 127 #define CLK_HS_PREP (0xff << 0) 128 #define CLK_HS_POST (0xff << 8) 129 #define CLK_HS_EXIT (0xff << 16) 130 131 #define DSI_VM_CMD_CON 0x130 132 #define VM_CMD_EN BIT(0) 133 #define TS_VFP_EN BIT(5) 134 135 #define DSI_SHADOW_DEBUG 0x190U 136 #define FORCE_COMMIT BIT(0) 137 #define BYPASS_SHADOW BIT(1) 138 139 #define CONFIG (0xff << 0) 140 #define SHORT_PACKET 0 141 #define LONG_PACKET 2 142 #define BTA BIT(2) 143 #define DATA_ID (0xff << 8) 144 #define DATA_0 (0xff << 16) 145 #define DATA_1 (0xff << 24) 146 147 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) 148 149 #define MTK_DSI_HOST_IS_READ(type) \ 150 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 151 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 152 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 153 (type == MIPI_DSI_DCS_READ)) 154 155 struct mtk_phy_timing { 156 u32 lpx; 157 u32 da_hs_prepare; 158 u32 da_hs_zero; 159 u32 da_hs_trail; 160 161 u32 ta_go; 162 u32 ta_sure; 163 u32 ta_get; 164 u32 da_hs_exit; 165 166 u32 clk_hs_zero; 167 u32 clk_hs_trail; 168 169 u32 clk_hs_prepare; 170 u32 clk_hs_post; 171 u32 clk_hs_exit; 172 }; 173 174 struct phy; 175 176 struct mtk_dsi_driver_data { 177 const u32 reg_cmdq_off; 178 bool has_shadow_ctl; 179 bool has_size_ctl; 180 }; 181 182 struct mtk_dsi { 183 struct device *dev; 184 struct mipi_dsi_host host; 185 struct drm_encoder encoder; 186 struct drm_bridge bridge; 187 struct drm_bridge *next_bridge; 188 struct drm_connector *connector; 189 struct phy *phy; 190 191 void __iomem *regs; 192 193 struct clk *engine_clk; 194 struct clk *digital_clk; 195 struct clk *hs_clk; 196 197 u32 data_rate; 198 199 unsigned long mode_flags; 200 enum mipi_dsi_pixel_format format; 201 unsigned int lanes; 202 struct videomode vm; 203 struct mtk_phy_timing phy_timing; 204 int refcount; 205 bool enabled; 206 bool lanes_ready; 207 u32 irq_data; 208 wait_queue_head_t irq_wait_queue; 209 const struct mtk_dsi_driver_data *driver_data; 210 }; 211 212 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b) 213 { 214 return container_of(b, struct mtk_dsi, bridge); 215 } 216 217 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h) 218 { 219 return container_of(h, struct mtk_dsi, host); 220 } 221 222 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) 223 { 224 u32 temp = readl(dsi->regs + offset); 225 226 writel((temp & ~mask) | (data & mask), dsi->regs + offset); 227 } 228 229 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) 230 { 231 u32 timcon0, timcon1, timcon2, timcon3; 232 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); 233 struct mtk_phy_timing *timing = &dsi->phy_timing; 234 235 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; 236 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; 237 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - 238 timing->da_hs_prepare; 239 timing->da_hs_trail = timing->da_hs_prepare + 1; 240 241 timing->ta_go = 4 * timing->lpx - 2; 242 timing->ta_sure = timing->lpx + 2; 243 timing->ta_get = 4 * timing->lpx; 244 timing->da_hs_exit = 2 * timing->lpx + 1; 245 246 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); 247 timing->clk_hs_post = timing->clk_hs_prepare + 8; 248 timing->clk_hs_trail = timing->clk_hs_prepare; 249 timing->clk_hs_zero = timing->clk_hs_trail * 4; 250 timing->clk_hs_exit = 2 * timing->clk_hs_trail; 251 252 timcon0 = timing->lpx | timing->da_hs_prepare << 8 | 253 timing->da_hs_zero << 16 | timing->da_hs_trail << 24; 254 timcon1 = timing->ta_go | timing->ta_sure << 8 | 255 timing->ta_get << 16 | timing->da_hs_exit << 24; 256 timcon2 = 1 << 8 | timing->clk_hs_zero << 16 | 257 timing->clk_hs_trail << 24; 258 timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 | 259 timing->clk_hs_exit << 16; 260 261 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); 262 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); 263 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); 264 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); 265 } 266 267 static void mtk_dsi_enable(struct mtk_dsi *dsi) 268 { 269 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN); 270 } 271 272 static void mtk_dsi_disable(struct mtk_dsi *dsi) 273 { 274 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0); 275 } 276 277 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) 278 { 279 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET); 280 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); 281 } 282 283 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi) 284 { 285 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET); 286 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0); 287 } 288 289 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) 290 { 291 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 292 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 293 } 294 295 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) 296 { 297 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 298 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN); 299 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0); 300 } 301 302 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) 303 { 304 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); 305 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 306 } 307 308 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) 309 { 310 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 311 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN); 312 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0); 313 } 314 315 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi) 316 { 317 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN; 318 } 319 320 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter) 321 { 322 if (enter && !mtk_dsi_clk_hs_state(dsi)) 323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN); 324 else if (!enter && mtk_dsi_clk_hs_state(dsi)) 325 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 326 } 327 328 static void mtk_dsi_set_mode(struct mtk_dsi *dsi) 329 { 330 u32 vid_mode = CMD_MODE; 331 332 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 333 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 334 vid_mode = BURST_MODE; 335 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 336 vid_mode = SYNC_PULSE_MODE; 337 else 338 vid_mode = SYNC_EVENT_MODE; 339 } 340 341 writel(vid_mode, dsi->regs + DSI_MODE_CTRL); 342 } 343 344 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) 345 { 346 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); 347 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); 348 } 349 350 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) 351 { 352 struct videomode *vm = &dsi->vm; 353 u32 dsi_buf_bpp, ps_wc; 354 u32 ps_bpp_mode; 355 356 if (dsi->format == MIPI_DSI_FMT_RGB565) 357 dsi_buf_bpp = 2; 358 else 359 dsi_buf_bpp = 3; 360 361 ps_wc = vm->hactive * dsi_buf_bpp; 362 ps_bpp_mode = ps_wc; 363 364 switch (dsi->format) { 365 case MIPI_DSI_FMT_RGB888: 366 ps_bpp_mode |= PACKED_PS_24BIT_RGB888; 367 break; 368 case MIPI_DSI_FMT_RGB666: 369 ps_bpp_mode |= PACKED_PS_18BIT_RGB666; 370 break; 371 case MIPI_DSI_FMT_RGB666_PACKED: 372 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; 373 break; 374 case MIPI_DSI_FMT_RGB565: 375 ps_bpp_mode |= PACKED_PS_16BIT_RGB565; 376 break; 377 } 378 379 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 380 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); 381 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); 382 } 383 384 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) 385 { 386 u32 tmp_reg; 387 388 switch (dsi->lanes) { 389 case 1: 390 tmp_reg = 1 << 2; 391 break; 392 case 2: 393 tmp_reg = 3 << 2; 394 break; 395 case 3: 396 tmp_reg = 7 << 2; 397 break; 398 case 4: 399 tmp_reg = 0xf << 2; 400 break; 401 default: 402 tmp_reg = 0xf << 2; 403 break; 404 } 405 406 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 407 tmp_reg |= HSTX_CKLP_EN; 408 409 if (!(dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 410 tmp_reg |= DIS_EOT; 411 412 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); 413 } 414 415 static void mtk_dsi_ps_control(struct mtk_dsi *dsi) 416 { 417 u32 dsi_tmp_buf_bpp; 418 u32 tmp_reg; 419 420 switch (dsi->format) { 421 case MIPI_DSI_FMT_RGB888: 422 tmp_reg = PACKED_PS_24BIT_RGB888; 423 dsi_tmp_buf_bpp = 3; 424 break; 425 case MIPI_DSI_FMT_RGB666: 426 tmp_reg = LOOSELY_PS_18BIT_RGB666; 427 dsi_tmp_buf_bpp = 3; 428 break; 429 case MIPI_DSI_FMT_RGB666_PACKED: 430 tmp_reg = PACKED_PS_18BIT_RGB666; 431 dsi_tmp_buf_bpp = 3; 432 break; 433 case MIPI_DSI_FMT_RGB565: 434 tmp_reg = PACKED_PS_16BIT_RGB565; 435 dsi_tmp_buf_bpp = 2; 436 break; 437 default: 438 tmp_reg = PACKED_PS_24BIT_RGB888; 439 dsi_tmp_buf_bpp = 3; 440 break; 441 } 442 443 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; 444 writel(tmp_reg, dsi->regs + DSI_PSCTRL); 445 } 446 447 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) 448 { 449 u32 horizontal_sync_active_byte; 450 u32 horizontal_backporch_byte; 451 u32 horizontal_frontporch_byte; 452 u32 horizontal_front_back_byte; 453 u32 data_phy_cycles_byte; 454 u32 dsi_tmp_buf_bpp, data_phy_cycles; 455 u32 delta; 456 struct mtk_phy_timing *timing = &dsi->phy_timing; 457 458 struct videomode *vm = &dsi->vm; 459 460 if (dsi->format == MIPI_DSI_FMT_RGB565) 461 dsi_tmp_buf_bpp = 2; 462 else 463 dsi_tmp_buf_bpp = 3; 464 465 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); 466 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); 467 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); 468 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 469 470 if (dsi->driver_data->has_size_ctl) 471 writel(vm->vactive << 16 | vm->hactive, 472 dsi->regs + DSI_SIZE_CON); 473 474 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); 475 476 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 477 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10; 478 else 479 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) * 480 dsi_tmp_buf_bpp - 10; 481 482 data_phy_cycles = timing->lpx + timing->da_hs_prepare + 483 timing->da_hs_zero + timing->da_hs_exit + 3; 484 485 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; 486 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 2 : 0; 487 488 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp; 489 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte; 490 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta; 491 492 if (horizontal_front_back_byte > data_phy_cycles_byte) { 493 horizontal_frontporch_byte -= data_phy_cycles_byte * 494 horizontal_frontporch_byte / 495 horizontal_front_back_byte; 496 497 horizontal_backporch_byte -= data_phy_cycles_byte * 498 horizontal_backporch_byte / 499 horizontal_front_back_byte; 500 } else { 501 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); 502 } 503 504 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) && 505 (dsi->lanes == 4)) { 506 horizontal_sync_active_byte = 507 roundup(horizontal_sync_active_byte, dsi->lanes) - 2; 508 horizontal_frontporch_byte = 509 roundup(horizontal_frontporch_byte, dsi->lanes) - 2; 510 horizontal_backporch_byte = 511 roundup(horizontal_backporch_byte, dsi->lanes) - 2; 512 horizontal_backporch_byte -= 513 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; 514 } 515 516 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); 517 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 518 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); 519 520 mtk_dsi_ps_control(dsi); 521 } 522 523 static void mtk_dsi_start(struct mtk_dsi *dsi) 524 { 525 writel(0, dsi->regs + DSI_START); 526 writel(1, dsi->regs + DSI_START); 527 } 528 529 static void mtk_dsi_stop(struct mtk_dsi *dsi) 530 { 531 writel(0, dsi->regs + DSI_START); 532 } 533 534 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) 535 { 536 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); 537 } 538 539 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) 540 { 541 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 542 543 writel(inten, dsi->regs + DSI_INTEN); 544 } 545 546 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) 547 { 548 dsi->irq_data |= irq_bit; 549 } 550 551 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit) 552 { 553 dsi->irq_data &= ~irq_bit; 554 } 555 556 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag, 557 unsigned int timeout) 558 { 559 s32 ret = 0; 560 unsigned long jiffies = msecs_to_jiffies(timeout); 561 562 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue, 563 dsi->irq_data & irq_flag, 564 jiffies); 565 if (ret == 0) { 566 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag); 567 568 mtk_dsi_enable(dsi); 569 mtk_dsi_reset_engine(dsi); 570 } 571 572 return ret; 573 } 574 575 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) 576 { 577 struct mtk_dsi *dsi = dev_id; 578 u32 status, tmp; 579 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 580 581 status = readl(dsi->regs + DSI_INTSTA) & flag; 582 583 if (status) { 584 do { 585 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); 586 tmp = readl(dsi->regs + DSI_INTSTA); 587 } while (tmp & DSI_BUSY); 588 589 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); 590 mtk_dsi_irq_data_set(dsi, status); 591 wake_up_interruptible(&dsi->irq_wait_queue); 592 } 593 594 return IRQ_HANDLED; 595 } 596 597 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) 598 { 599 mtk_dsi_irq_data_clear(dsi, irq_flag); 600 mtk_dsi_set_cmd_mode(dsi); 601 602 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { 603 DRM_ERROR("failed to switch cmd mode\n"); 604 return -ETIME; 605 } else { 606 return 0; 607 } 608 } 609 610 static int mtk_dsi_poweron(struct mtk_dsi *dsi) 611 { 612 struct device *dev = dsi->host.dev; 613 int ret; 614 u32 bit_per_pixel; 615 616 if (++dsi->refcount != 1) 617 return 0; 618 619 switch (dsi->format) { 620 case MIPI_DSI_FMT_RGB565: 621 bit_per_pixel = 16; 622 break; 623 case MIPI_DSI_FMT_RGB666_PACKED: 624 bit_per_pixel = 18; 625 break; 626 case MIPI_DSI_FMT_RGB666: 627 case MIPI_DSI_FMT_RGB888: 628 default: 629 bit_per_pixel = 24; 630 break; 631 } 632 633 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel, 634 dsi->lanes); 635 636 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); 637 if (ret < 0) { 638 dev_err(dev, "Failed to set data rate: %d\n", ret); 639 goto err_refcount; 640 } 641 642 phy_power_on(dsi->phy); 643 644 ret = clk_prepare_enable(dsi->engine_clk); 645 if (ret < 0) { 646 dev_err(dev, "Failed to enable engine clock: %d\n", ret); 647 goto err_phy_power_off; 648 } 649 650 ret = clk_prepare_enable(dsi->digital_clk); 651 if (ret < 0) { 652 dev_err(dev, "Failed to enable digital clock: %d\n", ret); 653 goto err_disable_engine_clk; 654 } 655 656 mtk_dsi_enable(dsi); 657 658 if (dsi->driver_data->has_shadow_ctl) 659 writel(FORCE_COMMIT | BYPASS_SHADOW, 660 dsi->regs + DSI_SHADOW_DEBUG); 661 662 mtk_dsi_reset_engine(dsi); 663 mtk_dsi_phy_timconfig(dsi); 664 665 mtk_dsi_ps_control_vact(dsi); 666 mtk_dsi_set_vm_cmd(dsi); 667 mtk_dsi_config_vdo_timing(dsi); 668 mtk_dsi_set_interrupt_enable(dsi); 669 670 return 0; 671 err_disable_engine_clk: 672 clk_disable_unprepare(dsi->engine_clk); 673 err_phy_power_off: 674 phy_power_off(dsi->phy); 675 err_refcount: 676 dsi->refcount--; 677 return ret; 678 } 679 680 static void mtk_dsi_poweroff(struct mtk_dsi *dsi) 681 { 682 if (WARN_ON(dsi->refcount == 0)) 683 return; 684 685 if (--dsi->refcount != 0) 686 return; 687 688 /* 689 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since 690 * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), 691 * which needs irq for vblank, and mtk_dsi_stop() will disable irq. 692 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(), 693 * after dsi is fully set. 694 */ 695 mtk_dsi_stop(dsi); 696 697 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); 698 mtk_dsi_reset_engine(dsi); 699 mtk_dsi_lane0_ulp_mode_enter(dsi); 700 mtk_dsi_clk_ulp_mode_enter(dsi); 701 /* set the lane number as 0 to pull down mipi */ 702 writel(0, dsi->regs + DSI_TXRX_CTRL); 703 704 mtk_dsi_disable(dsi); 705 706 clk_disable_unprepare(dsi->engine_clk); 707 clk_disable_unprepare(dsi->digital_clk); 708 709 phy_power_off(dsi->phy); 710 711 dsi->lanes_ready = false; 712 } 713 714 static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) 715 { 716 if (!dsi->lanes_ready) { 717 dsi->lanes_ready = true; 718 mtk_dsi_rxtx_control(dsi); 719 usleep_range(30, 100); 720 mtk_dsi_reset_dphy(dsi); 721 mtk_dsi_clk_ulp_mode_leave(dsi); 722 mtk_dsi_lane0_ulp_mode_leave(dsi); 723 mtk_dsi_clk_hs_mode(dsi, 0); 724 msleep(20); 725 /* The reaction time after pulling up the mipi signal for dsi_rx */ 726 } 727 } 728 729 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) 730 { 731 if (dsi->enabled) 732 return; 733 734 mtk_dsi_lane_ready(dsi); 735 mtk_dsi_set_mode(dsi); 736 mtk_dsi_clk_hs_mode(dsi, 1); 737 738 mtk_dsi_start(dsi); 739 740 dsi->enabled = true; 741 } 742 743 static void mtk_output_dsi_disable(struct mtk_dsi *dsi) 744 { 745 if (!dsi->enabled) 746 return; 747 748 dsi->enabled = false; 749 } 750 751 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge, 752 enum drm_bridge_attach_flags flags) 753 { 754 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 755 756 /* Attach the panel or bridge to the dsi bridge */ 757 return drm_bridge_attach(bridge->encoder, dsi->next_bridge, 758 &dsi->bridge, flags); 759 } 760 761 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge, 762 const struct drm_display_mode *mode, 763 const struct drm_display_mode *adjusted) 764 { 765 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 766 767 drm_display_mode_to_videomode(adjusted, &dsi->vm); 768 } 769 770 static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge, 771 struct drm_bridge_state *old_bridge_state) 772 { 773 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 774 775 mtk_output_dsi_disable(dsi); 776 } 777 778 static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 779 struct drm_bridge_state *old_bridge_state) 780 { 781 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 782 783 if (dsi->refcount == 0) 784 return; 785 786 mtk_output_dsi_enable(dsi); 787 } 788 789 static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 790 struct drm_bridge_state *old_bridge_state) 791 { 792 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 793 int ret; 794 795 ret = mtk_dsi_poweron(dsi); 796 if (ret < 0) 797 DRM_ERROR("failed to power on dsi\n"); 798 } 799 800 static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge, 801 struct drm_bridge_state *old_bridge_state) 802 { 803 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 804 805 mtk_dsi_poweroff(dsi); 806 } 807 808 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = { 809 .attach = mtk_dsi_bridge_attach, 810 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 811 .atomic_disable = mtk_dsi_bridge_atomic_disable, 812 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 813 .atomic_enable = mtk_dsi_bridge_atomic_enable, 814 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable, 815 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable, 816 .atomic_reset = drm_atomic_helper_bridge_reset, 817 .mode_set = mtk_dsi_bridge_mode_set, 818 }; 819 820 void mtk_dsi_ddp_start(struct device *dev) 821 { 822 struct mtk_dsi *dsi = dev_get_drvdata(dev); 823 824 mtk_dsi_poweron(dsi); 825 } 826 827 void mtk_dsi_ddp_stop(struct device *dev) 828 { 829 struct mtk_dsi *dsi = dev_get_drvdata(dev); 830 831 mtk_dsi_poweroff(dsi); 832 } 833 834 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) 835 { 836 int ret; 837 838 ret = drm_simple_encoder_init(drm, &dsi->encoder, 839 DRM_MODE_ENCODER_DSI); 840 if (ret) { 841 DRM_ERROR("Failed to encoder init to drm\n"); 842 return ret; 843 } 844 845 dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev); 846 847 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 848 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 849 if (ret) 850 goto err_cleanup_encoder; 851 852 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder); 853 if (IS_ERR(dsi->connector)) { 854 DRM_ERROR("Unable to create bridge connector\n"); 855 ret = PTR_ERR(dsi->connector); 856 goto err_cleanup_encoder; 857 } 858 drm_connector_attach_encoder(dsi->connector, &dsi->encoder); 859 860 return 0; 861 862 err_cleanup_encoder: 863 drm_encoder_cleanup(&dsi->encoder); 864 return ret; 865 } 866 867 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) 868 { 869 int ret; 870 struct drm_device *drm = data; 871 struct mtk_dsi *dsi = dev_get_drvdata(dev); 872 873 ret = mtk_dsi_encoder_init(drm, dsi); 874 if (ret) 875 return ret; 876 877 return device_reset_optional(dev); 878 } 879 880 static void mtk_dsi_unbind(struct device *dev, struct device *master, 881 void *data) 882 { 883 struct mtk_dsi *dsi = dev_get_drvdata(dev); 884 885 drm_encoder_cleanup(&dsi->encoder); 886 } 887 888 static const struct component_ops mtk_dsi_component_ops = { 889 .bind = mtk_dsi_bind, 890 .unbind = mtk_dsi_unbind, 891 }; 892 893 static int mtk_dsi_host_attach(struct mipi_dsi_host *host, 894 struct mipi_dsi_device *device) 895 { 896 struct mtk_dsi *dsi = host_to_dsi(host); 897 struct device *dev = host->dev; 898 int ret; 899 900 dsi->lanes = device->lanes; 901 dsi->format = device->format; 902 dsi->mode_flags = device->mode_flags; 903 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0); 904 if (IS_ERR(dsi->next_bridge)) 905 return PTR_ERR(dsi->next_bridge); 906 907 drm_bridge_add(&dsi->bridge); 908 909 ret = component_add(host->dev, &mtk_dsi_component_ops); 910 if (ret) { 911 DRM_ERROR("failed to add dsi_host component: %d\n", ret); 912 drm_bridge_remove(&dsi->bridge); 913 return ret; 914 } 915 916 return 0; 917 } 918 919 static int mtk_dsi_host_detach(struct mipi_dsi_host *host, 920 struct mipi_dsi_device *device) 921 { 922 struct mtk_dsi *dsi = host_to_dsi(host); 923 924 component_del(host->dev, &mtk_dsi_component_ops); 925 drm_bridge_remove(&dsi->bridge); 926 return 0; 927 } 928 929 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi) 930 { 931 int ret; 932 u32 val; 933 934 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY), 935 4, 2000000); 936 if (ret) { 937 DRM_WARN("polling dsi wait not busy timeout!\n"); 938 939 mtk_dsi_enable(dsi); 940 mtk_dsi_reset_engine(dsi); 941 } 942 } 943 944 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data) 945 { 946 switch (type) { 947 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 948 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 949 return 1; 950 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 951 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 952 return 2; 953 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 954 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 955 return read_data[1] + read_data[2] * 16; 956 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 957 DRM_INFO("type is 0x02, try again\n"); 958 break; 959 default: 960 DRM_INFO("type(0x%x) not recognized\n", type); 961 break; 962 } 963 964 return 0; 965 } 966 967 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) 968 { 969 const char *tx_buf = msg->tx_buf; 970 u8 config, cmdq_size, cmdq_off, type = msg->type; 971 u32 reg_val, cmdq_mask, i; 972 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off; 973 974 if (MTK_DSI_HOST_IS_READ(type)) 975 config = BTA; 976 else 977 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; 978 979 if (msg->tx_len > 2) { 980 cmdq_size = 1 + (msg->tx_len + 3) / 4; 981 cmdq_off = 4; 982 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; 983 reg_val = (msg->tx_len << 16) | (type << 8) | config; 984 } else { 985 cmdq_size = 1; 986 cmdq_off = 2; 987 cmdq_mask = CONFIG | DATA_ID; 988 reg_val = (type << 8) | config; 989 } 990 991 for (i = 0; i < msg->tx_len; i++) 992 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U), 993 (0xffUL << (((i + cmdq_off) & 3U) * 8U)), 994 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U)); 995 996 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); 997 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); 998 } 999 1000 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, 1001 const struct mipi_dsi_msg *msg, u8 flag) 1002 { 1003 mtk_dsi_wait_for_idle(dsi); 1004 mtk_dsi_irq_data_clear(dsi, flag); 1005 mtk_dsi_cmdq(dsi, msg); 1006 mtk_dsi_start(dsi); 1007 1008 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000)) 1009 return -ETIME; 1010 else 1011 return 0; 1012 } 1013 1014 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, 1015 const struct mipi_dsi_msg *msg) 1016 { 1017 struct mtk_dsi *dsi = host_to_dsi(host); 1018 u32 recv_cnt, i; 1019 u8 read_data[16]; 1020 void *src_addr; 1021 u8 irq_flag = CMD_DONE_INT_FLAG; 1022 u32 dsi_mode; 1023 int ret; 1024 1025 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL); 1026 if (dsi_mode & MODE) { 1027 mtk_dsi_stop(dsi); 1028 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); 1029 if (ret) 1030 goto restore_dsi_mode; 1031 } 1032 1033 if (MTK_DSI_HOST_IS_READ(msg->type)) 1034 irq_flag |= LPRX_RD_RDY_INT_FLAG; 1035 1036 mtk_dsi_lane_ready(dsi); 1037 1038 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag); 1039 if (ret) 1040 goto restore_dsi_mode; 1041 1042 if (!MTK_DSI_HOST_IS_READ(msg->type)) { 1043 recv_cnt = 0; 1044 goto restore_dsi_mode; 1045 } 1046 1047 if (!msg->rx_buf) { 1048 DRM_ERROR("dsi receive buffer size may be NULL\n"); 1049 ret = -EINVAL; 1050 goto restore_dsi_mode; 1051 } 1052 1053 for (i = 0; i < 16; i++) 1054 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i); 1055 1056 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data); 1057 1058 if (recv_cnt > 2) 1059 src_addr = &read_data[4]; 1060 else 1061 src_addr = &read_data[1]; 1062 1063 if (recv_cnt > 10) 1064 recv_cnt = 10; 1065 1066 if (recv_cnt > msg->rx_len) 1067 recv_cnt = msg->rx_len; 1068 1069 if (recv_cnt) 1070 memcpy(msg->rx_buf, src_addr, recv_cnt); 1071 1072 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", 1073 recv_cnt, *((u8 *)(msg->tx_buf))); 1074 1075 restore_dsi_mode: 1076 if (dsi_mode & MODE) { 1077 mtk_dsi_set_mode(dsi); 1078 mtk_dsi_start(dsi); 1079 } 1080 1081 return ret < 0 ? ret : recv_cnt; 1082 } 1083 1084 static const struct mipi_dsi_host_ops mtk_dsi_ops = { 1085 .attach = mtk_dsi_host_attach, 1086 .detach = mtk_dsi_host_detach, 1087 .transfer = mtk_dsi_host_transfer, 1088 }; 1089 1090 static int mtk_dsi_probe(struct platform_device *pdev) 1091 { 1092 struct mtk_dsi *dsi; 1093 struct device *dev = &pdev->dev; 1094 struct resource *regs; 1095 int irq_num; 1096 int ret; 1097 1098 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1099 if (!dsi) 1100 return -ENOMEM; 1101 1102 dsi->host.ops = &mtk_dsi_ops; 1103 dsi->host.dev = dev; 1104 ret = mipi_dsi_host_register(&dsi->host); 1105 if (ret < 0) { 1106 dev_err(dev, "failed to register DSI host: %d\n", ret); 1107 return ret; 1108 } 1109 1110 dsi->driver_data = of_device_get_match_data(dev); 1111 1112 dsi->engine_clk = devm_clk_get(dev, "engine"); 1113 if (IS_ERR(dsi->engine_clk)) { 1114 ret = PTR_ERR(dsi->engine_clk); 1115 1116 if (ret != -EPROBE_DEFER) 1117 dev_err(dev, "Failed to get engine clock: %d\n", ret); 1118 goto err_unregister_host; 1119 } 1120 1121 dsi->digital_clk = devm_clk_get(dev, "digital"); 1122 if (IS_ERR(dsi->digital_clk)) { 1123 ret = PTR_ERR(dsi->digital_clk); 1124 1125 if (ret != -EPROBE_DEFER) 1126 dev_err(dev, "Failed to get digital clock: %d\n", ret); 1127 goto err_unregister_host; 1128 } 1129 1130 dsi->hs_clk = devm_clk_get(dev, "hs"); 1131 if (IS_ERR(dsi->hs_clk)) { 1132 ret = PTR_ERR(dsi->hs_clk); 1133 dev_err(dev, "Failed to get hs clock: %d\n", ret); 1134 goto err_unregister_host; 1135 } 1136 1137 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1138 dsi->regs = devm_ioremap_resource(dev, regs); 1139 if (IS_ERR(dsi->regs)) { 1140 ret = PTR_ERR(dsi->regs); 1141 dev_err(dev, "Failed to ioremap memory: %d\n", ret); 1142 goto err_unregister_host; 1143 } 1144 1145 dsi->phy = devm_phy_get(dev, "dphy"); 1146 if (IS_ERR(dsi->phy)) { 1147 ret = PTR_ERR(dsi->phy); 1148 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret); 1149 goto err_unregister_host; 1150 } 1151 1152 irq_num = platform_get_irq(pdev, 0); 1153 if (irq_num < 0) { 1154 ret = irq_num; 1155 goto err_unregister_host; 1156 } 1157 1158 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, 1159 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi); 1160 if (ret) { 1161 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); 1162 goto err_unregister_host; 1163 } 1164 1165 init_waitqueue_head(&dsi->irq_wait_queue); 1166 1167 platform_set_drvdata(pdev, dsi); 1168 1169 dsi->bridge.funcs = &mtk_dsi_bridge_funcs; 1170 dsi->bridge.of_node = dev->of_node; 1171 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1172 1173 return 0; 1174 1175 err_unregister_host: 1176 mipi_dsi_host_unregister(&dsi->host); 1177 return ret; 1178 } 1179 1180 static int mtk_dsi_remove(struct platform_device *pdev) 1181 { 1182 struct mtk_dsi *dsi = platform_get_drvdata(pdev); 1183 1184 mtk_output_dsi_disable(dsi); 1185 mipi_dsi_host_unregister(&dsi->host); 1186 1187 return 0; 1188 } 1189 1190 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { 1191 .reg_cmdq_off = 0x200, 1192 }; 1193 1194 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { 1195 .reg_cmdq_off = 0x180, 1196 }; 1197 1198 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { 1199 .reg_cmdq_off = 0x200, 1200 .has_shadow_ctl = true, 1201 .has_size_ctl = true, 1202 }; 1203 1204 static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { 1205 .reg_cmdq_off = 0xd00, 1206 .has_shadow_ctl = true, 1207 .has_size_ctl = true, 1208 }; 1209 1210 static const struct of_device_id mtk_dsi_of_match[] = { 1211 { .compatible = "mediatek,mt2701-dsi", 1212 .data = &mt2701_dsi_driver_data }, 1213 { .compatible = "mediatek,mt8173-dsi", 1214 .data = &mt8173_dsi_driver_data }, 1215 { .compatible = "mediatek,mt8183-dsi", 1216 .data = &mt8183_dsi_driver_data }, 1217 { .compatible = "mediatek,mt8186-dsi", 1218 .data = &mt8186_dsi_driver_data }, 1219 { }, 1220 }; 1221 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match); 1222 1223 struct platform_driver mtk_dsi_driver = { 1224 .probe = mtk_dsi_probe, 1225 .remove = mtk_dsi_remove, 1226 .driver = { 1227 .name = "mtk-dsi", 1228 .of_match_table = mtk_dsi_of_match, 1229 }, 1230 }; 1231