1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/debugfs.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/device.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/spi/spi.h> 18 #include <linux/err.h> 19 #include <linux/delay.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/of.h> 22 23 24 #include <linux/iio/backend.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 28 #include <linux/clk.h> 29 30 /* 31 * ADI High-Speed ADC common spi interface registers 32 * See Application-Note AN-877: 33 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 34 */ 35 36 #define AN877_ADC_REG_CHIP_PORT_CONF 0x00 37 #define AN877_ADC_REG_CHIP_ID 0x01 38 #define AN877_ADC_REG_CHIP_GRADE 0x02 39 #define AN877_ADC_REG_CHAN_INDEX 0x05 40 #define AN877_ADC_REG_TRANSFER 0xFF 41 #define AN877_ADC_REG_MODES 0x08 42 #define AN877_ADC_REG_TEST_IO 0x0D 43 #define AN877_ADC_REG_ADC_INPUT 0x0F 44 #define AN877_ADC_REG_OFFSET 0x10 45 #define AN877_ADC_REG_OUTPUT_MODE 0x14 46 #define AN877_ADC_REG_OUTPUT_ADJUST 0x15 47 #define AN877_ADC_REG_OUTPUT_PHASE 0x16 48 #define AN877_ADC_REG_OUTPUT_DELAY 0x17 49 #define AN877_ADC_REG_VREF 0x18 50 #define AN877_ADC_REG_ANALOG_INPUT 0x2C 51 52 /* AN877_ADC_REG_TEST_IO */ 53 #define AN877_ADC_TESTMODE_OFF 0x0 54 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 55 #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 56 #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 57 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 58 #define AN877_ADC_TESTMODE_PN23_SEQ 0x5 59 #define AN877_ADC_TESTMODE_PN9_SEQ 0x6 60 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 61 #define AN877_ADC_TESTMODE_USER 0x8 62 #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 63 #define AN877_ADC_TESTMODE_SYNC 0xA 64 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 65 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 66 #define AN877_ADC_TESTMODE_RAMP 0xF 67 68 /* AN877_ADC_REG_TRANSFER */ 69 #define AN877_ADC_TRANSFER_SYNC 0x1 70 71 /* AN877_ADC_REG_OUTPUT_MODE */ 72 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 73 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 74 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 75 76 /* AN877_ADC_REG_OUTPUT_PHASE */ 77 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 78 #define AN877_ADC_INVERT_DCO_CLK 0x80 79 80 /* AN877_ADC_REG_OUTPUT_DELAY */ 81 #define AN877_ADC_DCO_DELAY_ENABLE 0x80 82 83 /* 84 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 85 */ 86 87 #define CHIPID_AD9265 0x64 88 #define AD9265_DEF_OUTPUT_MODE 0x40 89 #define AD9265_REG_VREF_MASK 0xC0 90 91 /* 92 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 93 */ 94 95 #define CHIPID_AD9434 0x6A 96 #define AD9434_DEF_OUTPUT_MODE 0x00 97 #define AD9434_REG_VREF_MASK 0xC0 98 99 /* 100 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 101 */ 102 103 #define CHIPID_AD9467 0x50 104 #define AD9467_DEF_OUTPUT_MODE 0x08 105 #define AD9467_REG_VREF_MASK 0x0F 106 107 #define AD9647_MAX_TEST_POINTS 32 108 109 struct ad9467_chip_info { 110 const char *name; 111 unsigned int id; 112 const struct iio_chan_spec *channels; 113 unsigned int num_channels; 114 const unsigned int (*scale_table)[2]; 115 int num_scales; 116 unsigned long max_rate; 117 unsigned int default_output_mode; 118 unsigned int vref_mask; 119 unsigned int num_lanes; 120 /* data clock output */ 121 bool has_dco; 122 }; 123 124 struct ad9467_state { 125 const struct ad9467_chip_info *info; 126 struct iio_backend *back; 127 struct spi_device *spi; 128 struct clk *clk; 129 unsigned int output_mode; 130 unsigned int (*scales)[2]; 131 /* 132 * Times 2 because we may also invert the signal polarity and run the 133 * calibration again. For some reference on the test points (ad9265) see: 134 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad9265.pdf 135 * at page 38 for the dco output delay. On devices as ad9467, the 136 * calibration is done at the backend level. For the ADI axi-adc: 137 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 138 * at the io delay control section. 139 */ 140 DECLARE_BITMAP(calib_map, AD9647_MAX_TEST_POINTS * 2); 141 struct gpio_desc *pwrdown_gpio; 142 /* ensure consistent state obtained on multiple related accesses */ 143 struct mutex lock; 144 }; 145 146 static int ad9467_spi_read(struct spi_device *spi, unsigned int reg) 147 { 148 unsigned char tbuf[2], rbuf[1]; 149 int ret; 150 151 tbuf[0] = 0x80 | (reg >> 8); 152 tbuf[1] = reg & 0xFF; 153 154 ret = spi_write_then_read(spi, 155 tbuf, ARRAY_SIZE(tbuf), 156 rbuf, ARRAY_SIZE(rbuf)); 157 158 if (ret < 0) 159 return ret; 160 161 return rbuf[0]; 162 } 163 164 static int ad9467_spi_write(struct spi_device *spi, unsigned int reg, 165 unsigned int val) 166 { 167 unsigned char buf[3]; 168 169 buf[0] = reg >> 8; 170 buf[1] = reg & 0xFF; 171 buf[2] = val; 172 173 return spi_write(spi, buf, ARRAY_SIZE(buf)); 174 } 175 176 static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg, 177 unsigned int writeval, unsigned int *readval) 178 { 179 struct ad9467_state *st = iio_priv(indio_dev); 180 struct spi_device *spi = st->spi; 181 int ret; 182 183 if (!readval) { 184 guard(mutex)(&st->lock); 185 ret = ad9467_spi_write(spi, reg, writeval); 186 if (ret) 187 return ret; 188 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 189 AN877_ADC_TRANSFER_SYNC); 190 } 191 192 ret = ad9467_spi_read(spi, reg); 193 if (ret < 0) 194 return ret; 195 *readval = ret; 196 197 return 0; 198 } 199 200 static const unsigned int ad9265_scale_table[][2] = { 201 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 202 }; 203 204 static const unsigned int ad9434_scale_table[][2] = { 205 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 206 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 207 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 208 {1200, 0x0B}, {1180, 0x0C}, 209 }; 210 211 static const unsigned int ad9467_scale_table[][2] = { 212 {2000, 0}, {2100, 6}, {2200, 7}, 213 {2300, 8}, {2400, 9}, {2500, 10}, 214 }; 215 216 static void __ad9467_get_scale(struct ad9467_state *st, int index, 217 unsigned int *val, unsigned int *val2) 218 { 219 const struct ad9467_chip_info *info = st->info; 220 const struct iio_chan_spec *chan = &info->channels[0]; 221 unsigned int tmp; 222 223 tmp = (info->scale_table[index][0] * 1000000ULL) >> 224 chan->scan_type.realbits; 225 *val = tmp / 1000000; 226 *val2 = tmp % 1000000; 227 } 228 229 #define AD9467_CHAN(_chan, _si, _bits, _sign) \ 230 { \ 231 .type = IIO_VOLTAGE, \ 232 .indexed = 1, \ 233 .channel = _chan, \ 234 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 235 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 236 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 237 .scan_index = _si, \ 238 .scan_type = { \ 239 .sign = _sign, \ 240 .realbits = _bits, \ 241 .storagebits = 16, \ 242 }, \ 243 } 244 245 static const struct iio_chan_spec ad9434_channels[] = { 246 AD9467_CHAN(0, 0, 12, 'S'), 247 }; 248 249 static const struct iio_chan_spec ad9467_channels[] = { 250 AD9467_CHAN(0, 0, 16, 'S'), 251 }; 252 253 static const struct ad9467_chip_info ad9467_chip_tbl = { 254 .name = "ad9467", 255 .id = CHIPID_AD9467, 256 .max_rate = 250000000UL, 257 .scale_table = ad9467_scale_table, 258 .num_scales = ARRAY_SIZE(ad9467_scale_table), 259 .channels = ad9467_channels, 260 .num_channels = ARRAY_SIZE(ad9467_channels), 261 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 262 .vref_mask = AD9467_REG_VREF_MASK, 263 .num_lanes = 8, 264 }; 265 266 static const struct ad9467_chip_info ad9434_chip_tbl = { 267 .name = "ad9434", 268 .id = CHIPID_AD9434, 269 .max_rate = 500000000UL, 270 .scale_table = ad9434_scale_table, 271 .num_scales = ARRAY_SIZE(ad9434_scale_table), 272 .channels = ad9434_channels, 273 .num_channels = ARRAY_SIZE(ad9434_channels), 274 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 275 .vref_mask = AD9434_REG_VREF_MASK, 276 .num_lanes = 6, 277 }; 278 279 static const struct ad9467_chip_info ad9265_chip_tbl = { 280 .name = "ad9265", 281 .id = CHIPID_AD9265, 282 .max_rate = 125000000UL, 283 .scale_table = ad9265_scale_table, 284 .num_scales = ARRAY_SIZE(ad9265_scale_table), 285 .channels = ad9467_channels, 286 .num_channels = ARRAY_SIZE(ad9467_channels), 287 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 288 .vref_mask = AD9265_REG_VREF_MASK, 289 .has_dco = true, 290 }; 291 292 static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2) 293 { 294 const struct ad9467_chip_info *info = st->info; 295 unsigned int i, vref_val; 296 int ret; 297 298 ret = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF); 299 if (ret < 0) 300 return ret; 301 302 vref_val = ret & info->vref_mask; 303 304 for (i = 0; i < info->num_scales; i++) { 305 if (vref_val == info->scale_table[i][1]) 306 break; 307 } 308 309 if (i == info->num_scales) 310 return -ERANGE; 311 312 __ad9467_get_scale(st, i, val, val2); 313 314 return IIO_VAL_INT_PLUS_MICRO; 315 } 316 317 static int ad9467_set_scale(struct ad9467_state *st, int val, int val2) 318 { 319 const struct ad9467_chip_info *info = st->info; 320 unsigned int scale_val[2]; 321 unsigned int i; 322 int ret; 323 324 if (val != 0) 325 return -EINVAL; 326 327 for (i = 0; i < info->num_scales; i++) { 328 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]); 329 if (scale_val[0] != val || scale_val[1] != val2) 330 continue; 331 332 guard(mutex)(&st->lock); 333 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_VREF, 334 info->scale_table[i][1]); 335 if (ret < 0) 336 return ret; 337 338 return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 339 AN877_ADC_TRANSFER_SYNC); 340 } 341 342 return -EINVAL; 343 } 344 345 static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode) 346 { 347 int ret; 348 349 ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode); 350 if (ret < 0) 351 return ret; 352 353 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 354 AN877_ADC_TRANSFER_SYNC); 355 } 356 357 static int ad9647_calibrate_prepare(const struct ad9467_state *st) 358 { 359 struct iio_backend_data_fmt data = { 360 .enable = false, 361 }; 362 unsigned int c; 363 int ret; 364 365 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_TEST_IO, 366 AN877_ADC_TESTMODE_PN9_SEQ); 367 if (ret) 368 return ret; 369 370 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 371 AN877_ADC_TRANSFER_SYNC); 372 if (ret) 373 return ret; 374 375 ret = ad9467_outputmode_set(st->spi, st->info->default_output_mode); 376 if (ret) 377 return ret; 378 379 for (c = 0; c < st->info->num_channels; c++) { 380 ret = iio_backend_data_format_set(st->back, c, &data); 381 if (ret) 382 return ret; 383 } 384 385 ret = iio_backend_test_pattern_set(st->back, 0, 386 IIO_BACKEND_ADI_PRBS_9A); 387 if (ret) 388 return ret; 389 390 return iio_backend_chan_enable(st->back, 0); 391 } 392 393 static int ad9647_calibrate_polarity_set(const struct ad9467_state *st, 394 bool invert) 395 { 396 enum iio_backend_sample_trigger trigger; 397 398 if (st->info->has_dco) { 399 unsigned int phase = AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN; 400 401 if (invert) 402 phase |= AN877_ADC_INVERT_DCO_CLK; 403 404 return ad9467_spi_write(st->spi, AN877_ADC_REG_OUTPUT_PHASE, 405 phase); 406 } 407 408 if (invert) 409 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING; 410 else 411 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING; 412 413 return iio_backend_data_sample_trigger(st->back, trigger); 414 } 415 416 /* 417 * The idea is pretty simple. Find the max number of successful points in a row 418 * and get the one in the middle. 419 */ 420 static unsigned int ad9467_find_optimal_point(const unsigned long *calib_map, 421 unsigned int start, 422 unsigned int nbits, 423 unsigned int *val) 424 { 425 unsigned int bit = start, end, start_cnt, cnt = 0; 426 427 for_each_clear_bitrange_from(bit, end, calib_map, nbits + start) { 428 if (end - bit > cnt) { 429 cnt = end - bit; 430 start_cnt = bit; 431 } 432 } 433 434 if (cnt) 435 *val = start_cnt + cnt / 2; 436 437 return cnt; 438 } 439 440 static int ad9467_calibrate_apply(const struct ad9467_state *st, 441 unsigned int val) 442 { 443 unsigned int lane; 444 int ret; 445 446 if (st->info->has_dco) { 447 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_OUTPUT_DELAY, 448 val); 449 if (ret) 450 return ret; 451 452 return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 453 AN877_ADC_TRANSFER_SYNC); 454 } 455 456 for (lane = 0; lane < st->info->num_lanes; lane++) { 457 ret = iio_backend_iodelay_set(st->back, lane, val); 458 if (ret) 459 return ret; 460 } 461 462 return 0; 463 } 464 465 static int ad9647_calibrate_stop(const struct ad9467_state *st) 466 { 467 struct iio_backend_data_fmt data = { 468 .sign_extend = true, 469 .enable = true, 470 }; 471 unsigned int c, mode; 472 int ret; 473 474 ret = iio_backend_chan_disable(st->back, 0); 475 if (ret) 476 return ret; 477 478 ret = iio_backend_test_pattern_set(st->back, 0, 479 IIO_BACKEND_NO_TEST_PATTERN); 480 if (ret) 481 return ret; 482 483 for (c = 0; c < st->info->num_channels; c++) { 484 ret = iio_backend_data_format_set(st->back, c, &data); 485 if (ret) 486 return ret; 487 } 488 489 mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 490 ret = ad9467_outputmode_set(st->spi, mode); 491 if (ret) 492 return ret; 493 494 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_TEST_IO, 495 AN877_ADC_TESTMODE_OFF); 496 if (ret) 497 return ret; 498 499 return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 500 AN877_ADC_TRANSFER_SYNC); 501 } 502 503 static int ad9467_calibrate(struct ad9467_state *st) 504 { 505 unsigned int point, val, inv_val, cnt, inv_cnt = 0; 506 /* 507 * Half of the bitmap is for the inverted signal. The number of test 508 * points is the same though... 509 */ 510 unsigned int test_points = AD9647_MAX_TEST_POINTS; 511 unsigned long sample_rate = clk_get_rate(st->clk); 512 struct device *dev = &st->spi->dev; 513 bool invert = false, stat; 514 int ret; 515 516 /* all points invalid */ 517 bitmap_fill(st->calib_map, BITS_PER_TYPE(st->calib_map)); 518 519 ret = ad9647_calibrate_prepare(st); 520 if (ret) 521 return ret; 522 retune: 523 ret = ad9647_calibrate_polarity_set(st, invert); 524 if (ret) 525 return ret; 526 527 for (point = 0; point < test_points; point++) { 528 ret = ad9467_calibrate_apply(st, point); 529 if (ret) 530 return ret; 531 532 ret = iio_backend_chan_status(st->back, 0, &stat); 533 if (ret) 534 return ret; 535 536 __assign_bit(point + invert * test_points, st->calib_map, stat); 537 } 538 539 if (!invert) { 540 cnt = ad9467_find_optimal_point(st->calib_map, 0, test_points, 541 &val); 542 /* 543 * We're happy if we find, at least, three good test points in 544 * a row. 545 */ 546 if (cnt < 3) { 547 invert = true; 548 goto retune; 549 } 550 } else { 551 inv_cnt = ad9467_find_optimal_point(st->calib_map, test_points, 552 test_points, &inv_val); 553 if (!inv_cnt && !cnt) 554 return -EIO; 555 } 556 557 if (inv_cnt < cnt) { 558 ret = ad9647_calibrate_polarity_set(st, false); 559 if (ret) 560 return ret; 561 } else { 562 /* 563 * polarity inverted is the last test to run. Hence, there's no 564 * need to re-do any configuration. We just need to "normalize" 565 * the selected value. 566 */ 567 val = inv_val - test_points; 568 } 569 570 if (st->info->has_dco) 571 dev_dbg(dev, "%sDCO 0x%X CLK %lu Hz\n", inv_cnt >= cnt ? "INVERT " : "", 572 val, sample_rate); 573 else 574 dev_dbg(dev, "%sIDELAY 0x%x\n", inv_cnt >= cnt ? "INVERT " : "", 575 val); 576 577 ret = ad9467_calibrate_apply(st, val); 578 if (ret) 579 return ret; 580 581 /* finally apply the optimal value */ 582 return ad9647_calibrate_stop(st); 583 } 584 585 static int ad9467_read_raw(struct iio_dev *indio_dev, 586 struct iio_chan_spec const *chan, 587 int *val, int *val2, long m) 588 { 589 struct ad9467_state *st = iio_priv(indio_dev); 590 591 switch (m) { 592 case IIO_CHAN_INFO_SCALE: 593 return ad9467_get_scale(st, val, val2); 594 case IIO_CHAN_INFO_SAMP_FREQ: 595 *val = clk_get_rate(st->clk); 596 597 return IIO_VAL_INT; 598 default: 599 return -EINVAL; 600 } 601 } 602 603 static int ad9467_write_raw(struct iio_dev *indio_dev, 604 struct iio_chan_spec const *chan, 605 int val, int val2, long mask) 606 { 607 struct ad9467_state *st = iio_priv(indio_dev); 608 const struct ad9467_chip_info *info = st->info; 609 unsigned long sample_rate; 610 long r_clk; 611 int ret; 612 613 switch (mask) { 614 case IIO_CHAN_INFO_SCALE: 615 return ad9467_set_scale(st, val, val2); 616 case IIO_CHAN_INFO_SAMP_FREQ: 617 r_clk = clk_round_rate(st->clk, val); 618 if (r_clk < 0 || r_clk > info->max_rate) { 619 dev_warn(&st->spi->dev, 620 "Error setting ADC sample rate %ld", r_clk); 621 return -EINVAL; 622 } 623 624 sample_rate = clk_get_rate(st->clk); 625 /* 626 * clk_set_rate() would also do this but since we would still 627 * need it for avoiding an unnecessary calibration, do it now. 628 */ 629 if (sample_rate == r_clk) 630 return 0; 631 632 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 633 ret = clk_set_rate(st->clk, r_clk); 634 if (ret) 635 return ret; 636 637 guard(mutex)(&st->lock); 638 ret = ad9467_calibrate(st); 639 } 640 return ret; 641 default: 642 return -EINVAL; 643 } 644 } 645 646 static int ad9467_read_avail(struct iio_dev *indio_dev, 647 struct iio_chan_spec const *chan, 648 const int **vals, int *type, int *length, 649 long mask) 650 { 651 struct ad9467_state *st = iio_priv(indio_dev); 652 const struct ad9467_chip_info *info = st->info; 653 654 switch (mask) { 655 case IIO_CHAN_INFO_SCALE: 656 *vals = (const int *)st->scales; 657 *type = IIO_VAL_INT_PLUS_MICRO; 658 /* Values are stored in a 2D matrix */ 659 *length = info->num_scales * 2; 660 return IIO_AVAIL_LIST; 661 default: 662 return -EINVAL; 663 } 664 } 665 666 static int ad9467_update_scan_mode(struct iio_dev *indio_dev, 667 const unsigned long *scan_mask) 668 { 669 struct ad9467_state *st = iio_priv(indio_dev); 670 unsigned int c; 671 int ret; 672 673 for (c = 0; c < st->info->num_channels; c++) { 674 if (test_bit(c, scan_mask)) 675 ret = iio_backend_chan_enable(st->back, c); 676 else 677 ret = iio_backend_chan_disable(st->back, c); 678 if (ret) 679 return ret; 680 } 681 682 return 0; 683 } 684 685 static const struct iio_info ad9467_info = { 686 .read_raw = ad9467_read_raw, 687 .write_raw = ad9467_write_raw, 688 .update_scan_mode = ad9467_update_scan_mode, 689 .debugfs_reg_access = ad9467_reg_access, 690 .read_avail = ad9467_read_avail, 691 }; 692 693 static int ad9467_scale_fill(struct ad9467_state *st) 694 { 695 const struct ad9467_chip_info *info = st->info; 696 unsigned int i, val1, val2; 697 698 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 699 sizeof(*st->scales), GFP_KERNEL); 700 if (!st->scales) 701 return -ENOMEM; 702 703 for (i = 0; i < info->num_scales; i++) { 704 __ad9467_get_scale(st, i, &val1, &val2); 705 st->scales[i][0] = val1; 706 st->scales[i][1] = val2; 707 } 708 709 return 0; 710 } 711 712 static int ad9467_reset(struct device *dev) 713 { 714 struct gpio_desc *gpio; 715 716 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 717 if (IS_ERR_OR_NULL(gpio)) 718 return PTR_ERR_OR_ZERO(gpio); 719 720 fsleep(1); 721 gpiod_set_value_cansleep(gpio, 0); 722 fsleep(10 * USEC_PER_MSEC); 723 724 return 0; 725 } 726 727 static int ad9467_iio_backend_get(struct ad9467_state *st) 728 { 729 struct device *dev = &st->spi->dev; 730 struct device_node *__back; 731 732 st->back = devm_iio_backend_get(dev, NULL); 733 if (!IS_ERR(st->back)) 734 return 0; 735 /* If not found, don't error out as we might have legacy DT property */ 736 if (PTR_ERR(st->back) != -ENOENT) 737 return PTR_ERR(st->back); 738 739 /* 740 * if we don't get the backend using the normal API's, use the legacy 741 * 'adi,adc-dev' property. So we get all nodes with that property, and 742 * look for the one pointing at us. Then we directly lookup that fwnode 743 * on the backend list of registered devices. This is done so we don't 744 * make io-backends mandatory which would break DT ABI. 745 */ 746 for_each_node_with_property(__back, "adi,adc-dev") { 747 struct device_node *__me; 748 749 __me = of_parse_phandle(__back, "adi,adc-dev", 0); 750 if (!__me) 751 continue; 752 753 if (!device_match_of_node(dev, __me)) { 754 of_node_put(__me); 755 continue; 756 } 757 758 of_node_put(__me); 759 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev, 760 of_fwnode_handle(__back)); 761 of_node_put(__back); 762 return PTR_ERR_OR_ZERO(st->back); 763 } 764 765 return -ENODEV; 766 } 767 768 static ssize_t ad9467_dump_calib_table(struct file *file, 769 char __user *userbuf, 770 size_t count, loff_t *ppos) 771 { 772 struct ad9467_state *st = file->private_data; 773 unsigned int bit, size = BITS_PER_TYPE(st->calib_map); 774 /* +2 for the newline and +1 for the string termination */ 775 unsigned char map[AD9647_MAX_TEST_POINTS * 2 + 3]; 776 ssize_t len = 0; 777 778 guard(mutex)(&st->lock); 779 if (*ppos) 780 goto out_read; 781 782 for (bit = 0; bit < size; bit++) { 783 if (bit == size / 2) 784 len += scnprintf(map + len, sizeof(map) - len, "\n"); 785 786 len += scnprintf(map + len, sizeof(map) - len, "%c", 787 test_bit(bit, st->calib_map) ? 'x' : 'o'); 788 } 789 790 len += scnprintf(map + len, sizeof(map) - len, "\n"); 791 out_read: 792 return simple_read_from_buffer(userbuf, count, ppos, map, len); 793 } 794 795 static const struct file_operations ad9467_calib_table_fops = { 796 .open = simple_open, 797 .read = ad9467_dump_calib_table, 798 .llseek = default_llseek, 799 .owner = THIS_MODULE, 800 }; 801 802 static void ad9467_debugfs_init(struct iio_dev *indio_dev) 803 { 804 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 805 struct ad9467_state *st = iio_priv(indio_dev); 806 807 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 808 return; 809 810 debugfs_create_file("calibration_table_dump", 0400, d, st, 811 &ad9467_calib_table_fops); 812 } 813 814 static int ad9467_probe(struct spi_device *spi) 815 { 816 struct iio_dev *indio_dev; 817 struct ad9467_state *st; 818 unsigned int id; 819 int ret; 820 821 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 822 if (!indio_dev) 823 return -ENOMEM; 824 825 st = iio_priv(indio_dev); 826 st->spi = spi; 827 828 st->info = spi_get_device_match_data(spi); 829 if (!st->info) 830 return -ENODEV; 831 832 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 833 if (IS_ERR(st->clk)) 834 return PTR_ERR(st->clk); 835 836 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 837 GPIOD_OUT_LOW); 838 if (IS_ERR(st->pwrdown_gpio)) 839 return PTR_ERR(st->pwrdown_gpio); 840 841 ret = ad9467_reset(&spi->dev); 842 if (ret) 843 return ret; 844 845 ret = ad9467_scale_fill(st); 846 if (ret) 847 return ret; 848 849 id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID); 850 if (id != st->info->id) { 851 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 852 id, st->info->id); 853 return -ENODEV; 854 } 855 856 indio_dev->name = st->info->name; 857 indio_dev->channels = st->info->channels; 858 indio_dev->num_channels = st->info->num_channels; 859 indio_dev->info = &ad9467_info; 860 861 ret = ad9467_iio_backend_get(st); 862 if (ret) 863 return ret; 864 865 ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev); 866 if (ret) 867 return ret; 868 869 ret = devm_iio_backend_enable(&spi->dev, st->back); 870 if (ret) 871 return ret; 872 873 ret = ad9467_calibrate(st); 874 if (ret) 875 return ret; 876 877 ret = devm_iio_device_register(&spi->dev, indio_dev); 878 if (ret) 879 return ret; 880 881 ad9467_debugfs_init(indio_dev); 882 883 return 0; 884 } 885 886 static const struct of_device_id ad9467_of_match[] = { 887 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, }, 888 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, }, 889 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, }, 890 {} 891 }; 892 MODULE_DEVICE_TABLE(of, ad9467_of_match); 893 894 static const struct spi_device_id ad9467_ids[] = { 895 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl }, 896 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl }, 897 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl }, 898 {} 899 }; 900 MODULE_DEVICE_TABLE(spi, ad9467_ids); 901 902 static struct spi_driver ad9467_driver = { 903 .driver = { 904 .name = "ad9467", 905 .of_match_table = ad9467_of_match, 906 }, 907 .probe = ad9467_probe, 908 .id_table = ad9467_ids, 909 }; 910 module_spi_driver(ad9467_driver); 911 912 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 913 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 914 MODULE_LICENSE("GPL v2"); 915 MODULE_IMPORT_NS(IIO_BACKEND); 916