1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 #include <linux/debugfs.h> 12 #include <linux/kthread.h> 13 #include <linux/seq_file.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_file.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_framebuffer.h> 20 21 #include "msm_drv.h" 22 #include "dpu_kms.h" 23 #include "dpu_hwio.h" 24 #include "dpu_hw_catalog.h" 25 #include "dpu_hw_intf.h" 26 #include "dpu_hw_ctl.h" 27 #include "dpu_hw_dspp.h" 28 #include "dpu_hw_dsc.h" 29 #include "dpu_hw_merge3d.h" 30 #include "dpu_hw_cdm.h" 31 #include "dpu_formats.h" 32 #include "dpu_encoder_phys.h" 33 #include "dpu_crtc.h" 34 #include "dpu_trace.h" 35 #include "dpu_core_irq.h" 36 #include "disp/msm_disp_snapshot.h" 37 38 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ 39 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 40 41 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 42 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 43 44 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\ 45 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 46 47 /* 48 * Two to anticipate panels that can do cmd/vid dynamic switching 49 * plan is to create all possible physical encoder types, and switch between 50 * them at runtime 51 */ 52 #define NUM_PHYS_ENCODER_TYPES 2 53 54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 56 57 #define MAX_CHANNELS_PER_ENC 2 58 59 #define IDLE_SHORT_TIMEOUT 1 60 61 #define MAX_HDISPLAY_SPLIT 1080 62 63 /* timeout in frames waiting for frame done */ 64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 65 66 /** 67 * enum dpu_enc_rc_events - events for resource control state machine 68 * @DPU_ENC_RC_EVENT_KICKOFF: 69 * This event happens at NORMAL priority. 70 * Event that signals the start of the transfer. When this event is 71 * received, enable MDP/DSI core clocks. Regardless of the previous 72 * state, the resource should be in ON state at the end of this event. 73 * @DPU_ENC_RC_EVENT_FRAME_DONE: 74 * This event happens at INTERRUPT level. 75 * Event signals the end of the data transfer after the PP FRAME_DONE 76 * event. At the end of this event, a delayed work is scheduled to go to 77 * IDLE_PC state after IDLE_TIMEOUT time. 78 * @DPU_ENC_RC_EVENT_PRE_STOP: 79 * This event happens at NORMAL priority. 80 * This event, when received during the ON state, leave the RC STATE 81 * in the PRE_OFF state. It should be followed by the STOP event as 82 * part of encoder disable. 83 * If received during IDLE or OFF states, it will do nothing. 84 * @DPU_ENC_RC_EVENT_STOP: 85 * This event happens at NORMAL priority. 86 * When this event is received, disable all the MDP/DSI core clocks, and 87 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 89 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 90 * Resource state should be in OFF at the end of the event. 91 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 92 * This event happens at NORMAL priority from a work item. 93 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 94 * This would disable MDP/DSI core clocks and change the resource state 95 * to IDLE. 96 */ 97 enum dpu_enc_rc_events { 98 DPU_ENC_RC_EVENT_KICKOFF = 1, 99 DPU_ENC_RC_EVENT_FRAME_DONE, 100 DPU_ENC_RC_EVENT_PRE_STOP, 101 DPU_ENC_RC_EVENT_STOP, 102 DPU_ENC_RC_EVENT_ENTER_IDLE 103 }; 104 105 /* 106 * enum dpu_enc_rc_states - states that the resource control maintains 107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 112 */ 113 enum dpu_enc_rc_states { 114 DPU_ENC_RC_STATE_OFF, 115 DPU_ENC_RC_STATE_PRE_OFF, 116 DPU_ENC_RC_STATE_ON, 117 DPU_ENC_RC_STATE_IDLE 118 }; 119 120 /** 121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 122 * encoders. Virtual encoder manages one "logical" display. Physical 123 * encoders manage one intf block, tied to a specific panel/sub-panel. 124 * Virtual encoder defers as much as possible to the physical encoders. 125 * Virtual encoder registers itself with the DRM Framework as the encoder. 126 * @base: drm_encoder base class for registration with DRM 127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 128 * @enabled: True if the encoder is active, protected by enc_lock 129 * @num_phys_encs: Actual number of physical encoders contained. 130 * @phys_encs: Container of physical encoders managed. 131 * @cur_master: Pointer to the current master in this mode. Optimization 132 * Only valid after enable. Cleared as disable. 133 * @cur_slave: As above but for the slave encoder. 134 * @hw_pp: Handle to the pingpong blocks used for the display. No. 135 * pingpong blocks can be different than num_phys_encs. 136 * @hw_dsc: Handle to the DSC blocks used for the display. 137 * @dsc_mask: Bitmask of used DSC blocks. 138 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 139 * for partial update right-only cases, such as pingpong 140 * split where virtual pingpong does not generate IRQs 141 * @crtc: Pointer to the currently assigned crtc. Normally you 142 * would use crtc->state->encoder_mask to determine the 143 * link between encoder/crtc. However in this case we need 144 * to track crtc in the disable() hook which is called 145 * _after_ encoder_mask is cleared. 146 * @connector: If a mode is set, cached pointer to the active connector 147 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 148 * all CTL paths 149 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 150 * @debugfs_root: Debug file system root file node 151 * @enc_lock: Lock around physical encoder 152 * create/destroy/enable/disable 153 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 154 * busy processing current command. 155 * Bit0 = phys_encs[0] etc. 156 * @crtc_frame_event_cb: callback handler for frame event 157 * @crtc_frame_event_cb_data: callback handler private data 158 * @frame_done_timeout_ms: frame done timeout in ms 159 * @frame_done_timeout_cnt: atomic counter tracking the number of frame 160 * done timeouts 161 * @frame_done_timer: watchdog timer for frame done event 162 * @disp_info: local copy of msm_display_info struct 163 * @idle_pc_supported: indicate if idle power collaps is supported 164 * @rc_lock: resource control mutex lock to protect 165 * virt encoder over various state changes 166 * @rc_state: resource controller state 167 * @delayed_off_work: delayed worker to schedule disabling of 168 * clks and resources after IDLE_TIMEOUT time. 169 * @topology: topology of the display 170 * @idle_timeout: idle timeout duration in milliseconds 171 * @wide_bus_en: wide bus is enabled on this interface 172 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders 173 */ 174 struct dpu_encoder_virt { 175 struct drm_encoder base; 176 spinlock_t enc_spinlock; 177 178 bool enabled; 179 180 unsigned int num_phys_encs; 181 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 182 struct dpu_encoder_phys *cur_master; 183 struct dpu_encoder_phys *cur_slave; 184 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 185 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 186 187 unsigned int dsc_mask; 188 189 bool intfs_swapped; 190 191 struct drm_crtc *crtc; 192 struct drm_connector *connector; 193 194 struct mutex enc_lock; 195 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 196 void (*crtc_frame_event_cb)(void *, u32 event); 197 void *crtc_frame_event_cb_data; 198 199 atomic_t frame_done_timeout_ms; 200 atomic_t frame_done_timeout_cnt; 201 struct timer_list frame_done_timer; 202 203 struct msm_display_info disp_info; 204 205 bool idle_pc_supported; 206 struct mutex rc_lock; 207 enum dpu_enc_rc_states rc_state; 208 struct delayed_work delayed_off_work; 209 struct msm_display_topology topology; 210 211 u32 idle_timeout; 212 213 bool wide_bus_en; 214 215 /* DSC configuration */ 216 struct drm_dsc_config *dsc; 217 }; 218 219 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 220 221 static u32 dither_matrix[DITHER_MATRIX_SZ] = { 222 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 223 }; 224 225 226 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 227 { 228 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 229 230 return dpu_enc->wide_bus_en; 231 } 232 233 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 234 { 235 struct dpu_encoder_virt *dpu_enc; 236 int i, num_intf = 0; 237 238 dpu_enc = to_dpu_encoder_virt(drm_enc); 239 240 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 241 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 242 243 if (phys->hw_intf && phys->hw_intf->ops.setup_misr 244 && phys->hw_intf->ops.collect_misr) 245 num_intf++; 246 } 247 248 return num_intf; 249 } 250 251 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 252 { 253 struct dpu_encoder_virt *dpu_enc; 254 255 int i; 256 257 dpu_enc = to_dpu_encoder_virt(drm_enc); 258 259 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 260 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 261 262 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) 263 continue; 264 265 phys->hw_intf->ops.setup_misr(phys->hw_intf); 266 } 267 } 268 269 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 270 { 271 struct dpu_encoder_virt *dpu_enc; 272 273 int i, rc = 0, entries_added = 0; 274 275 if (!drm_enc->crtc) { 276 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); 277 return -EINVAL; 278 } 279 280 dpu_enc = to_dpu_encoder_virt(drm_enc); 281 282 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 283 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 284 285 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) 286 continue; 287 288 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); 289 if (rc) 290 return rc; 291 entries_added++; 292 } 293 294 return entries_added; 295 } 296 297 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) 298 { 299 struct dpu_hw_dither_cfg dither_cfg = { 0 }; 300 301 if (!hw_pp->ops.setup_dither) 302 return; 303 304 switch (bpc) { 305 case 6: 306 dither_cfg.c0_bitdepth = 6; 307 dither_cfg.c1_bitdepth = 6; 308 dither_cfg.c2_bitdepth = 6; 309 dither_cfg.c3_bitdepth = 6; 310 dither_cfg.temporal_en = 0; 311 break; 312 default: 313 hw_pp->ops.setup_dither(hw_pp, NULL); 314 return; 315 } 316 317 memcpy(&dither_cfg.matrix, dither_matrix, 318 sizeof(u32) * DITHER_MATRIX_SZ); 319 320 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); 321 } 322 323 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode) 324 { 325 switch (intf_mode) { 326 case INTF_MODE_VIDEO: 327 return "INTF_MODE_VIDEO"; 328 case INTF_MODE_CMD: 329 return "INTF_MODE_CMD"; 330 case INTF_MODE_WB_BLOCK: 331 return "INTF_MODE_WB_BLOCK"; 332 case INTF_MODE_WB_LINE: 333 return "INTF_MODE_WB_LINE"; 334 default: 335 return "INTF_MODE_UNKNOWN"; 336 } 337 } 338 339 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 340 enum dpu_intr_idx intr_idx) 341 { 342 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n", 343 DRMID(phys_enc->parent), 344 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), 345 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, 346 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, 347 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 348 349 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, 350 DPU_ENCODER_FRAME_EVENT_ERROR); 351 } 352 353 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 354 u32 irq_idx, struct dpu_encoder_wait_info *info); 355 356 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 357 unsigned int irq_idx, 358 void (*func)(void *arg), 359 struct dpu_encoder_wait_info *wait_info) 360 { 361 u32 irq_status; 362 int ret; 363 364 if (!wait_info) { 365 DPU_ERROR("invalid params\n"); 366 return -EINVAL; 367 } 368 /* note: do master / slave checking outside */ 369 370 /* return EWOULDBLOCK since we know the wait isn't necessary */ 371 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 372 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n", 373 DRMID(phys_enc->parent), func, 374 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); 375 return -EWOULDBLOCK; 376 } 377 378 if (irq_idx < 0) { 379 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n", 380 DRMID(phys_enc->parent), func); 381 return 0; 382 } 383 384 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n", 385 DRMID(phys_enc->parent), func, 386 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, 387 atomic_read(wait_info->atomic_cnt)); 388 389 ret = dpu_encoder_helper_wait_event_timeout( 390 DRMID(phys_enc->parent), 391 irq_idx, 392 wait_info); 393 394 if (ret <= 0) { 395 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); 396 if (irq_status) { 397 unsigned long flags; 398 399 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 400 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 401 DRMID(phys_enc->parent), func, 402 phys_enc->hw_pp->idx - PINGPONG_0, 403 atomic_read(wait_info->atomic_cnt)); 404 local_irq_save(flags); 405 func(phys_enc); 406 local_irq_restore(flags); 407 ret = 0; 408 } else { 409 ret = -ETIMEDOUT; 410 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 411 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 412 DRMID(phys_enc->parent), func, 413 phys_enc->hw_pp->idx - PINGPONG_0, 414 atomic_read(wait_info->atomic_cnt)); 415 } 416 } else { 417 ret = 0; 418 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 419 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 420 phys_enc->hw_pp->idx - PINGPONG_0, 421 atomic_read(wait_info->atomic_cnt)); 422 } 423 424 return ret; 425 } 426 427 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 428 { 429 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 430 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL; 431 return phys ? atomic_read(&phys->vsync_cnt) : 0; 432 } 433 434 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 435 { 436 struct dpu_encoder_virt *dpu_enc; 437 struct dpu_encoder_phys *phys; 438 int linecount = 0; 439 440 dpu_enc = to_dpu_encoder_virt(drm_enc); 441 phys = dpu_enc ? dpu_enc->cur_master : NULL; 442 443 if (phys && phys->ops.get_line_count) 444 linecount = phys->ops.get_line_count(phys); 445 446 return linecount; 447 } 448 449 void dpu_encoder_helper_split_config( 450 struct dpu_encoder_phys *phys_enc, 451 enum dpu_intf interface) 452 { 453 struct dpu_encoder_virt *dpu_enc; 454 struct split_pipe_cfg cfg = { 0 }; 455 struct dpu_hw_mdp *hw_mdptop; 456 struct msm_display_info *disp_info; 457 458 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 459 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 460 return; 461 } 462 463 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 464 hw_mdptop = phys_enc->hw_mdptop; 465 disp_info = &dpu_enc->disp_info; 466 467 if (disp_info->intf_type != INTF_DSI) 468 return; 469 470 /** 471 * disable split modes since encoder will be operating in as the only 472 * encoder, either for the entire use case in the case of, for example, 473 * single DSI, or for this frame in the case of left/right only partial 474 * update. 475 */ 476 if (phys_enc->split_role == ENC_ROLE_SOLO) { 477 if (hw_mdptop->ops.setup_split_pipe) 478 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 479 return; 480 } 481 482 cfg.en = true; 483 cfg.mode = phys_enc->intf_mode; 484 cfg.intf = interface; 485 486 if (cfg.en && phys_enc->ops.needs_single_flush && 487 phys_enc->ops.needs_single_flush(phys_enc)) 488 cfg.split_flush_en = true; 489 490 if (phys_enc->split_role == ENC_ROLE_MASTER) { 491 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 492 493 if (hw_mdptop->ops.setup_split_pipe) 494 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 495 } 496 } 497 498 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 499 { 500 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 501 int i, intf_count = 0, num_dsc = 0; 502 503 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 504 if (dpu_enc->phys_encs[i]) 505 intf_count++; 506 507 /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ 508 if (dpu_enc->dsc) 509 num_dsc = 2; 510 511 return (num_dsc > 0) && (num_dsc > intf_count); 512 } 513 514 static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 515 { 516 struct msm_drm_private *priv = drm_enc->dev->dev_private; 517 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 518 int index = dpu_enc->disp_info.h_tile_instance[0]; 519 520 if (dpu_enc->disp_info.intf_type == INTF_DSI) 521 return msm_dsi_get_dsc_config(priv->dsi[index]); 522 523 return NULL; 524 } 525 526 static struct msm_display_topology dpu_encoder_get_topology( 527 struct dpu_encoder_virt *dpu_enc, 528 struct dpu_kms *dpu_kms, 529 struct drm_display_mode *mode, 530 struct drm_crtc_state *crtc_state, 531 struct drm_dsc_config *dsc) 532 { 533 struct msm_display_topology topology = {0}; 534 int i, intf_count = 0; 535 536 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 537 if (dpu_enc->phys_encs[i]) 538 intf_count++; 539 540 /* Datapath topology selection 541 * 542 * Dual display 543 * 2 LM, 2 INTF ( Split display using 2 interfaces) 544 * 545 * Single display 546 * 1 LM, 1 INTF 547 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 548 * 549 * Add dspps to the reservation requirements if ctm is requested 550 */ 551 if (intf_count == 2) 552 topology.num_lm = 2; 553 else if (!dpu_kms->catalog->caps->has_3d_merge) 554 topology.num_lm = 1; 555 else 556 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 557 558 if (crtc_state->ctm) 559 topology.num_dspp = topology.num_lm; 560 561 topology.num_intf = intf_count; 562 563 if (dsc) { 564 /* 565 * In case of Display Stream Compression (DSC), we would use 566 * 2 DSC encoders, 2 layer mixers and 1 interface 567 * this is power optimal and can drive up to (including) 4k 568 * screens 569 */ 570 topology.num_dsc = 2; 571 topology.num_lm = 2; 572 topology.num_intf = 1; 573 } 574 575 return topology; 576 } 577 578 static int dpu_encoder_virt_atomic_check( 579 struct drm_encoder *drm_enc, 580 struct drm_crtc_state *crtc_state, 581 struct drm_connector_state *conn_state) 582 { 583 struct dpu_encoder_virt *dpu_enc; 584 struct msm_drm_private *priv; 585 struct dpu_kms *dpu_kms; 586 struct drm_display_mode *adj_mode; 587 struct msm_display_topology topology; 588 struct dpu_global_state *global_state; 589 struct drm_framebuffer *fb; 590 struct drm_dsc_config *dsc; 591 int i = 0; 592 int ret = 0; 593 594 if (!drm_enc || !crtc_state || !conn_state) { 595 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 596 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 597 return -EINVAL; 598 } 599 600 dpu_enc = to_dpu_encoder_virt(drm_enc); 601 DPU_DEBUG_ENC(dpu_enc, "\n"); 602 603 priv = drm_enc->dev->dev_private; 604 dpu_kms = to_dpu_kms(priv->kms); 605 adj_mode = &crtc_state->adjusted_mode; 606 global_state = dpu_kms_get_global_state(crtc_state->state); 607 if (IS_ERR(global_state)) 608 return PTR_ERR(global_state); 609 610 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 611 612 /* perform atomic check on the first physical encoder (master) */ 613 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 614 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 615 616 if (phys->ops.atomic_check) 617 ret = phys->ops.atomic_check(phys, crtc_state, 618 conn_state); 619 if (ret) { 620 DPU_ERROR_ENC(dpu_enc, 621 "mode unsupported, phys idx %d\n", i); 622 return ret; 623 } 624 } 625 626 dsc = dpu_encoder_get_dsc_config(drm_enc); 627 628 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); 629 630 /* 631 * Use CDM only for writeback at the moment as other interfaces cannot handle it. 632 * if writeback itself cannot handle cdm for some reason it will fail in its atomic_check() 633 * earlier. 634 */ 635 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { 636 fb = conn_state->writeback_job->fb; 637 638 if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb)))) 639 topology.needs_cdm = true; 640 if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) 641 crtc_state->mode_changed = true; 642 else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) 643 crtc_state->mode_changed = true; 644 } 645 646 /* 647 * Release and Allocate resources on every modeset 648 * Dont allocate when active is false. 649 */ 650 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 651 dpu_rm_release(global_state, drm_enc); 652 653 if (!crtc_state->active_changed || crtc_state->enable) 654 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 655 drm_enc, crtc_state, topology); 656 } 657 658 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); 659 660 return ret; 661 } 662 663 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 664 struct msm_display_info *disp_info) 665 { 666 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 667 struct msm_drm_private *priv; 668 struct dpu_kms *dpu_kms; 669 struct dpu_hw_mdp *hw_mdptop; 670 struct drm_encoder *drm_enc; 671 struct dpu_encoder_phys *phys_enc; 672 int i; 673 674 if (!dpu_enc || !disp_info) { 675 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 676 dpu_enc != NULL, disp_info != NULL); 677 return; 678 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 679 DPU_ERROR("invalid num phys enc %d/%d\n", 680 dpu_enc->num_phys_encs, 681 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 682 return; 683 } 684 685 drm_enc = &dpu_enc->base; 686 /* this pointers are checked in virt_enable_helper */ 687 priv = drm_enc->dev->dev_private; 688 689 dpu_kms = to_dpu_kms(priv->kms); 690 hw_mdptop = dpu_kms->hw_mdp; 691 if (!hw_mdptop) { 692 DPU_ERROR("invalid mdptop\n"); 693 return; 694 } 695 696 if (hw_mdptop->ops.setup_vsync_source && 697 disp_info->is_cmd_mode) { 698 for (i = 0; i < dpu_enc->num_phys_encs; i++) 699 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 700 701 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 702 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); 703 704 if (disp_info->is_te_using_watchdog_timer) 705 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 706 else 707 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 708 709 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 710 711 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 712 phys_enc = dpu_enc->phys_encs[i]; 713 714 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 715 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 716 vsync_cfg.vsync_source); 717 } 718 } 719 } 720 721 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 722 { 723 struct dpu_encoder_virt *dpu_enc; 724 int i; 725 726 if (!drm_enc) { 727 DPU_ERROR("invalid encoder\n"); 728 return; 729 } 730 731 dpu_enc = to_dpu_encoder_virt(drm_enc); 732 733 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 734 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 735 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 736 737 if (phys->ops.irq_control) 738 phys->ops.irq_control(phys, enable); 739 } 740 741 } 742 743 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 744 bool enable) 745 { 746 struct msm_drm_private *priv; 747 struct dpu_kms *dpu_kms; 748 struct dpu_encoder_virt *dpu_enc; 749 750 dpu_enc = to_dpu_encoder_virt(drm_enc); 751 priv = drm_enc->dev->dev_private; 752 dpu_kms = to_dpu_kms(priv->kms); 753 754 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 755 756 if (!dpu_enc->cur_master) { 757 DPU_ERROR("encoder master not set\n"); 758 return; 759 } 760 761 if (enable) { 762 /* enable DPU core clks */ 763 pm_runtime_get_sync(&dpu_kms->pdev->dev); 764 765 /* enable all the irq */ 766 _dpu_encoder_irq_control(drm_enc, true); 767 768 } else { 769 /* disable all the irq */ 770 _dpu_encoder_irq_control(drm_enc, false); 771 772 /* disable DPU core clks */ 773 pm_runtime_put_sync(&dpu_kms->pdev->dev); 774 } 775 776 } 777 778 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 779 u32 sw_event) 780 { 781 struct dpu_encoder_virt *dpu_enc; 782 struct msm_drm_private *priv; 783 bool is_vid_mode = false; 784 785 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 786 DPU_ERROR("invalid parameters\n"); 787 return -EINVAL; 788 } 789 dpu_enc = to_dpu_encoder_virt(drm_enc); 790 priv = drm_enc->dev->dev_private; 791 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode; 792 793 /* 794 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 795 * events and return early for other events (ie wb display). 796 */ 797 if (!dpu_enc->idle_pc_supported && 798 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 799 sw_event != DPU_ENC_RC_EVENT_STOP && 800 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 801 return 0; 802 803 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 804 dpu_enc->rc_state, "begin"); 805 806 switch (sw_event) { 807 case DPU_ENC_RC_EVENT_KICKOFF: 808 /* cancel delayed off work, if any */ 809 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 810 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 811 sw_event); 812 813 mutex_lock(&dpu_enc->rc_lock); 814 815 /* return if the resource control is already in ON state */ 816 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 817 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", 818 DRMID(drm_enc), sw_event); 819 mutex_unlock(&dpu_enc->rc_lock); 820 return 0; 821 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 822 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 823 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", 824 DRMID(drm_enc), sw_event, 825 dpu_enc->rc_state); 826 mutex_unlock(&dpu_enc->rc_lock); 827 return -EINVAL; 828 } 829 830 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 831 _dpu_encoder_irq_control(drm_enc, true); 832 else 833 _dpu_encoder_resource_control_helper(drm_enc, true); 834 835 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 836 837 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 838 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 839 "kickoff"); 840 841 mutex_unlock(&dpu_enc->rc_lock); 842 break; 843 844 case DPU_ENC_RC_EVENT_FRAME_DONE: 845 /* 846 * mutex lock is not used as this event happens at interrupt 847 * context. And locking is not required as, the other events 848 * like KICKOFF and STOP does a wait-for-idle before executing 849 * the resource_control 850 */ 851 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 852 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 853 DRMID(drm_enc), sw_event, 854 dpu_enc->rc_state); 855 return -EINVAL; 856 } 857 858 /* 859 * schedule off work item only when there are no 860 * frames pending 861 */ 862 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 863 DRM_DEBUG_KMS("id:%d skip schedule work\n", 864 DRMID(drm_enc)); 865 return 0; 866 } 867 868 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 869 msecs_to_jiffies(dpu_enc->idle_timeout)); 870 871 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 872 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 873 "frame done"); 874 break; 875 876 case DPU_ENC_RC_EVENT_PRE_STOP: 877 /* cancel delayed off work, if any */ 878 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 879 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 880 sw_event); 881 882 mutex_lock(&dpu_enc->rc_lock); 883 884 if (is_vid_mode && 885 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 886 _dpu_encoder_irq_control(drm_enc, true); 887 } 888 /* skip if is already OFF or IDLE, resources are off already */ 889 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 890 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 891 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 892 DRMID(drm_enc), sw_event, 893 dpu_enc->rc_state); 894 mutex_unlock(&dpu_enc->rc_lock); 895 return 0; 896 } 897 898 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 899 900 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 901 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 902 "pre stop"); 903 904 mutex_unlock(&dpu_enc->rc_lock); 905 break; 906 907 case DPU_ENC_RC_EVENT_STOP: 908 mutex_lock(&dpu_enc->rc_lock); 909 910 /* return if the resource control is already in OFF state */ 911 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 912 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 913 DRMID(drm_enc), sw_event); 914 mutex_unlock(&dpu_enc->rc_lock); 915 return 0; 916 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 917 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 918 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 919 mutex_unlock(&dpu_enc->rc_lock); 920 return -EINVAL; 921 } 922 923 /** 924 * expect to arrive here only if in either idle state or pre-off 925 * and in IDLE state the resources are already disabled 926 */ 927 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 928 _dpu_encoder_resource_control_helper(drm_enc, false); 929 930 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 931 932 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 933 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 934 "stop"); 935 936 mutex_unlock(&dpu_enc->rc_lock); 937 break; 938 939 case DPU_ENC_RC_EVENT_ENTER_IDLE: 940 mutex_lock(&dpu_enc->rc_lock); 941 942 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 943 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 944 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 945 mutex_unlock(&dpu_enc->rc_lock); 946 return 0; 947 } 948 949 /* 950 * if we are in ON but a frame was just kicked off, 951 * ignore the IDLE event, it's probably a stale timer event 952 */ 953 if (dpu_enc->frame_busy_mask[0]) { 954 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 955 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 956 mutex_unlock(&dpu_enc->rc_lock); 957 return 0; 958 } 959 960 if (is_vid_mode) 961 _dpu_encoder_irq_control(drm_enc, false); 962 else 963 _dpu_encoder_resource_control_helper(drm_enc, false); 964 965 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 966 967 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 968 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 969 "idle"); 970 971 mutex_unlock(&dpu_enc->rc_lock); 972 break; 973 974 default: 975 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 976 sw_event); 977 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 978 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 979 "error"); 980 break; 981 } 982 983 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 984 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 985 "end"); 986 return 0; 987 } 988 989 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 990 struct drm_writeback_job *job) 991 { 992 struct dpu_encoder_virt *dpu_enc; 993 int i; 994 995 dpu_enc = to_dpu_encoder_virt(drm_enc); 996 997 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 998 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 999 1000 if (phys->ops.prepare_wb_job) 1001 phys->ops.prepare_wb_job(phys, job); 1002 1003 } 1004 } 1005 1006 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1007 struct drm_writeback_job *job) 1008 { 1009 struct dpu_encoder_virt *dpu_enc; 1010 int i; 1011 1012 dpu_enc = to_dpu_encoder_virt(drm_enc); 1013 1014 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1015 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1016 1017 if (phys->ops.cleanup_wb_job) 1018 phys->ops.cleanup_wb_job(phys, job); 1019 1020 } 1021 } 1022 1023 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, 1024 struct drm_crtc_state *crtc_state, 1025 struct drm_connector_state *conn_state) 1026 { 1027 struct dpu_encoder_virt *dpu_enc; 1028 struct msm_drm_private *priv; 1029 struct dpu_kms *dpu_kms; 1030 struct dpu_crtc_state *cstate; 1031 struct dpu_global_state *global_state; 1032 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 1033 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 1034 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 1035 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; 1036 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; 1037 int num_lm, num_ctl, num_pp, num_dsc; 1038 unsigned int dsc_mask = 0; 1039 int i; 1040 1041 if (!drm_enc) { 1042 DPU_ERROR("invalid encoder\n"); 1043 return; 1044 } 1045 1046 dpu_enc = to_dpu_encoder_virt(drm_enc); 1047 DPU_DEBUG_ENC(dpu_enc, "\n"); 1048 1049 priv = drm_enc->dev->dev_private; 1050 dpu_kms = to_dpu_kms(priv->kms); 1051 1052 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1053 if (IS_ERR_OR_NULL(global_state)) { 1054 DPU_ERROR("Failed to get global state"); 1055 return; 1056 } 1057 1058 trace_dpu_enc_mode_set(DRMID(drm_enc)); 1059 1060 /* Query resource that have been reserved in atomic check step. */ 1061 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1062 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1063 ARRAY_SIZE(hw_pp)); 1064 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1065 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1066 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1067 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1068 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1069 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, 1070 ARRAY_SIZE(hw_dspp)); 1071 1072 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1073 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1074 : NULL; 1075 1076 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1077 drm_enc->base.id, DPU_HW_BLK_DSC, 1078 hw_dsc, ARRAY_SIZE(hw_dsc)); 1079 for (i = 0; i < num_dsc; i++) { 1080 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); 1081 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); 1082 } 1083 1084 dpu_enc->dsc_mask = dsc_mask; 1085 1086 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { 1087 struct dpu_hw_blk *hw_cdm = NULL; 1088 1089 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1090 drm_enc->base.id, DPU_HW_BLK_CDM, 1091 &hw_cdm, 1); 1092 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; 1093 } 1094 1095 cstate = to_dpu_crtc_state(crtc_state); 1096 1097 for (i = 0; i < num_lm; i++) { 1098 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 1099 1100 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 1101 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 1102 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); 1103 } 1104 1105 cstate->num_mixers = num_lm; 1106 1107 dpu_enc->connector = conn_state->connector; 1108 1109 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1110 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1111 1112 if (!dpu_enc->hw_pp[i]) { 1113 DPU_ERROR_ENC(dpu_enc, 1114 "no pp block assigned at idx: %d\n", i); 1115 return; 1116 } 1117 1118 if (!hw_ctl[i]) { 1119 DPU_ERROR_ENC(dpu_enc, 1120 "no ctl block assigned at idx: %d\n", i); 1121 return; 1122 } 1123 1124 phys->hw_pp = dpu_enc->hw_pp[i]; 1125 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1126 1127 phys->cached_mode = crtc_state->adjusted_mode; 1128 if (phys->ops.atomic_mode_set) 1129 phys->ops.atomic_mode_set(phys, crtc_state, conn_state); 1130 } 1131 } 1132 1133 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1134 { 1135 struct dpu_encoder_virt *dpu_enc = NULL; 1136 int i; 1137 1138 if (!drm_enc || !drm_enc->dev) { 1139 DPU_ERROR("invalid parameters\n"); 1140 return; 1141 } 1142 1143 dpu_enc = to_dpu_encoder_virt(drm_enc); 1144 if (!dpu_enc || !dpu_enc->cur_master) { 1145 DPU_ERROR("invalid dpu encoder/master\n"); 1146 return; 1147 } 1148 1149 1150 if (dpu_enc->disp_info.intf_type == INTF_DP && 1151 dpu_enc->cur_master->hw_mdptop && 1152 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) 1153 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( 1154 dpu_enc->cur_master->hw_mdptop); 1155 1156 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1157 1158 if (dpu_enc->disp_info.intf_type == INTF_DSI && 1159 !WARN_ON(dpu_enc->num_phys_encs == 0)) { 1160 unsigned bpc = dpu_enc->connector->display_info.bpc; 1161 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1162 if (!dpu_enc->hw_pp[i]) 1163 continue; 1164 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc); 1165 } 1166 } 1167 } 1168 1169 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1170 { 1171 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1172 1173 mutex_lock(&dpu_enc->enc_lock); 1174 1175 if (!dpu_enc->enabled) 1176 goto out; 1177 1178 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1179 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1180 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1181 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1182 1183 _dpu_encoder_virt_enable_helper(drm_enc); 1184 1185 out: 1186 mutex_unlock(&dpu_enc->enc_lock); 1187 } 1188 1189 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, 1190 struct drm_atomic_state *state) 1191 { 1192 struct dpu_encoder_virt *dpu_enc = NULL; 1193 int ret = 0; 1194 struct drm_display_mode *cur_mode = NULL; 1195 struct msm_drm_private *priv = drm_enc->dev->dev_private; 1196 struct msm_display_info *disp_info; 1197 int index; 1198 1199 dpu_enc = to_dpu_encoder_virt(drm_enc); 1200 disp_info = &dpu_enc->disp_info; 1201 index = disp_info->h_tile_instance[0]; 1202 1203 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); 1204 1205 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 1206 1207 if (disp_info->intf_type == INTF_DP) 1208 dpu_enc->wide_bus_en = msm_dp_wide_bus_available(priv->dp[index]); 1209 else if (disp_info->intf_type == INTF_DSI) 1210 dpu_enc->wide_bus_en = msm_dsi_wide_bus_enabled(priv->dsi[index]); 1211 1212 mutex_lock(&dpu_enc->enc_lock); 1213 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1214 1215 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1216 cur_mode->vdisplay); 1217 1218 /* always enable slave encoder before master */ 1219 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1220 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1221 1222 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1223 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1224 1225 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1226 if (ret) { 1227 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1228 ret); 1229 goto out; 1230 } 1231 1232 _dpu_encoder_virt_enable_helper(drm_enc); 1233 1234 dpu_enc->enabled = true; 1235 1236 out: 1237 mutex_unlock(&dpu_enc->enc_lock); 1238 } 1239 1240 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, 1241 struct drm_atomic_state *state) 1242 { 1243 struct dpu_encoder_virt *dpu_enc = NULL; 1244 struct drm_crtc *crtc; 1245 struct drm_crtc_state *old_state = NULL; 1246 int i = 0; 1247 1248 dpu_enc = to_dpu_encoder_virt(drm_enc); 1249 DPU_DEBUG_ENC(dpu_enc, "\n"); 1250 1251 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc); 1252 if (crtc) 1253 old_state = drm_atomic_get_old_crtc_state(state, crtc); 1254 1255 /* 1256 * The encoder is already disabled if self refresh mode was set earlier, 1257 * in the old_state for the corresponding crtc. 1258 */ 1259 if (old_state && old_state->self_refresh_active) 1260 return; 1261 1262 mutex_lock(&dpu_enc->enc_lock); 1263 dpu_enc->enabled = false; 1264 1265 trace_dpu_enc_disable(DRMID(drm_enc)); 1266 1267 /* wait for idle */ 1268 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1269 1270 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1271 1272 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1273 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1274 1275 if (phys->ops.disable) 1276 phys->ops.disable(phys); 1277 } 1278 1279 1280 /* after phys waits for frame-done, should be no more frames pending */ 1281 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1282 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1283 del_timer_sync(&dpu_enc->frame_done_timer); 1284 } 1285 1286 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1287 1288 dpu_enc->connector = NULL; 1289 1290 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1291 1292 mutex_unlock(&dpu_enc->enc_lock); 1293 } 1294 1295 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, 1296 struct dpu_rm *dpu_rm, 1297 enum dpu_intf_type type, u32 controller_id) 1298 { 1299 int i = 0; 1300 1301 if (type == INTF_WB) 1302 return NULL; 1303 1304 for (i = 0; i < catalog->intf_count; i++) { 1305 if (catalog->intf[i].type == type 1306 && catalog->intf[i].controller_id == controller_id) { 1307 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); 1308 } 1309 } 1310 1311 return NULL; 1312 } 1313 1314 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1315 struct dpu_encoder_phys *phy_enc) 1316 { 1317 struct dpu_encoder_virt *dpu_enc = NULL; 1318 unsigned long lock_flags; 1319 1320 if (!drm_enc || !phy_enc) 1321 return; 1322 1323 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1324 dpu_enc = to_dpu_encoder_virt(drm_enc); 1325 1326 atomic_inc(&phy_enc->vsync_cnt); 1327 1328 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1329 if (dpu_enc->crtc) 1330 dpu_crtc_vblank_callback(dpu_enc->crtc); 1331 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1332 1333 DPU_ATRACE_END("encoder_vblank_callback"); 1334 } 1335 1336 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1337 struct dpu_encoder_phys *phy_enc) 1338 { 1339 if (!phy_enc) 1340 return; 1341 1342 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1343 atomic_inc(&phy_enc->underrun_cnt); 1344 1345 /* trigger dump only on the first underrun */ 1346 if (atomic_read(&phy_enc->underrun_cnt) == 1) 1347 msm_disp_snapshot_state(drm_enc->dev); 1348 1349 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1350 atomic_read(&phy_enc->underrun_cnt)); 1351 DPU_ATRACE_END("encoder_underrun_callback"); 1352 } 1353 1354 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1355 { 1356 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1357 unsigned long lock_flags; 1358 1359 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1360 /* crtc should always be cleared before re-assigning */ 1361 WARN_ON(crtc && dpu_enc->crtc); 1362 dpu_enc->crtc = crtc; 1363 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1364 } 1365 1366 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1367 struct drm_crtc *crtc, bool enable) 1368 { 1369 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1370 unsigned long lock_flags; 1371 int i; 1372 1373 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1374 1375 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1376 if (dpu_enc->crtc != crtc) { 1377 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1378 return; 1379 } 1380 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1381 1382 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1383 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1384 1385 if (phys->ops.control_vblank_irq) 1386 phys->ops.control_vblank_irq(phys, enable); 1387 } 1388 } 1389 1390 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1391 void (*frame_event_cb)(void *, u32 event), 1392 void *frame_event_cb_data) 1393 { 1394 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1395 unsigned long lock_flags; 1396 bool enable; 1397 1398 enable = frame_event_cb ? true : false; 1399 1400 if (!drm_enc) { 1401 DPU_ERROR("invalid encoder\n"); 1402 return; 1403 } 1404 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1405 1406 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1407 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1408 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1409 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1410 } 1411 1412 void dpu_encoder_frame_done_callback( 1413 struct drm_encoder *drm_enc, 1414 struct dpu_encoder_phys *ready_phys, u32 event) 1415 { 1416 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1417 unsigned int i; 1418 1419 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1420 | DPU_ENCODER_FRAME_EVENT_ERROR 1421 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1422 1423 if (!dpu_enc->frame_busy_mask[0]) { 1424 /** 1425 * suppress frame_done without waiter, 1426 * likely autorefresh 1427 */ 1428 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event, 1429 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode), 1430 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1, 1431 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1); 1432 return; 1433 } 1434 1435 /* One of the physical encoders has become idle */ 1436 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1437 if (dpu_enc->phys_encs[i] == ready_phys) { 1438 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1439 dpu_enc->frame_busy_mask[0]); 1440 clear_bit(i, dpu_enc->frame_busy_mask); 1441 } 1442 } 1443 1444 if (!dpu_enc->frame_busy_mask[0]) { 1445 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1446 del_timer(&dpu_enc->frame_done_timer); 1447 1448 dpu_encoder_resource_control(drm_enc, 1449 DPU_ENC_RC_EVENT_FRAME_DONE); 1450 1451 if (dpu_enc->crtc_frame_event_cb) 1452 dpu_enc->crtc_frame_event_cb( 1453 dpu_enc->crtc_frame_event_cb_data, 1454 event); 1455 } 1456 } else { 1457 if (dpu_enc->crtc_frame_event_cb) 1458 dpu_enc->crtc_frame_event_cb( 1459 dpu_enc->crtc_frame_event_cb_data, event); 1460 } 1461 } 1462 1463 static void dpu_encoder_off_work(struct work_struct *work) 1464 { 1465 struct dpu_encoder_virt *dpu_enc = container_of(work, 1466 struct dpu_encoder_virt, delayed_off_work.work); 1467 1468 dpu_encoder_resource_control(&dpu_enc->base, 1469 DPU_ENC_RC_EVENT_ENTER_IDLE); 1470 1471 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1472 DPU_ENCODER_FRAME_EVENT_IDLE); 1473 } 1474 1475 /** 1476 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1477 * @drm_enc: Pointer to drm encoder structure 1478 * @phys: Pointer to physical encoder structure 1479 * @extra_flush_bits: Additional bit mask to include in flush trigger 1480 */ 1481 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1482 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1483 { 1484 struct dpu_hw_ctl *ctl; 1485 int pending_kickoff_cnt; 1486 u32 ret = UINT_MAX; 1487 1488 if (!phys->hw_pp) { 1489 DPU_ERROR("invalid pingpong hw\n"); 1490 return; 1491 } 1492 1493 ctl = phys->hw_ctl; 1494 if (!ctl->ops.trigger_flush) { 1495 DPU_ERROR("missing trigger cb\n"); 1496 return; 1497 } 1498 1499 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1500 1501 if (extra_flush_bits && ctl->ops.update_pending_flush) 1502 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1503 1504 ctl->ops.trigger_flush(ctl); 1505 1506 if (ctl->ops.get_pending_flush) 1507 ret = ctl->ops.get_pending_flush(ctl); 1508 1509 trace_dpu_enc_trigger_flush(DRMID(drm_enc), 1510 dpu_encoder_helper_get_intf_type(phys->intf_mode), 1511 phys->hw_intf ? phys->hw_intf->idx : -1, 1512 phys->hw_wb ? phys->hw_wb->idx : -1, 1513 pending_kickoff_cnt, ctl->idx, 1514 extra_flush_bits, ret); 1515 } 1516 1517 /** 1518 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1519 * @phys: Pointer to physical encoder structure 1520 */ 1521 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1522 { 1523 if (!phys) { 1524 DPU_ERROR("invalid argument(s)\n"); 1525 return; 1526 } 1527 1528 if (!phys->hw_pp) { 1529 DPU_ERROR("invalid pingpong hw\n"); 1530 return; 1531 } 1532 1533 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1534 phys->ops.trigger_start(phys); 1535 } 1536 1537 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1538 { 1539 struct dpu_hw_ctl *ctl; 1540 1541 ctl = phys_enc->hw_ctl; 1542 if (ctl->ops.trigger_start) { 1543 ctl->ops.trigger_start(ctl); 1544 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1545 } 1546 } 1547 1548 static int dpu_encoder_helper_wait_event_timeout( 1549 int32_t drm_id, 1550 unsigned int irq_idx, 1551 struct dpu_encoder_wait_info *info) 1552 { 1553 int rc = 0; 1554 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1555 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1556 s64 time; 1557 1558 do { 1559 rc = wait_event_timeout(*(info->wq), 1560 atomic_read(info->atomic_cnt) == 0, jiffies); 1561 time = ktime_to_ms(ktime_get()); 1562 1563 trace_dpu_enc_wait_event_timeout(drm_id, 1564 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 1565 rc, time, 1566 expected_time, 1567 atomic_read(info->atomic_cnt)); 1568 /* If we timed out, counter is valid and time is less, wait again */ 1569 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1570 (time < expected_time)); 1571 1572 return rc; 1573 } 1574 1575 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1576 { 1577 struct dpu_encoder_virt *dpu_enc; 1578 struct dpu_hw_ctl *ctl; 1579 int rc; 1580 struct drm_encoder *drm_enc; 1581 1582 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1583 ctl = phys_enc->hw_ctl; 1584 drm_enc = phys_enc->parent; 1585 1586 if (!ctl->ops.reset) 1587 return; 1588 1589 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), 1590 ctl->idx); 1591 1592 rc = ctl->ops.reset(ctl); 1593 if (rc) { 1594 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1595 msm_disp_snapshot_state(drm_enc->dev); 1596 } 1597 1598 phys_enc->enable_state = DPU_ENC_ENABLED; 1599 } 1600 1601 /** 1602 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1603 * Iterate through the physical encoders and perform consolidated flush 1604 * and/or control start triggering as needed. This is done in the virtual 1605 * encoder rather than the individual physical ones in order to handle 1606 * use cases that require visibility into multiple physical encoders at 1607 * a time. 1608 * @dpu_enc: Pointer to virtual encoder structure 1609 */ 1610 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1611 { 1612 struct dpu_hw_ctl *ctl; 1613 uint32_t i, pending_flush; 1614 unsigned long lock_flags; 1615 1616 pending_flush = 0x0; 1617 1618 /* update pending counts and trigger kickoff ctl flush atomically */ 1619 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1620 1621 /* don't perform flush/start operations for slave encoders */ 1622 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1623 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1624 1625 if (phys->enable_state == DPU_ENC_DISABLED) 1626 continue; 1627 1628 ctl = phys->hw_ctl; 1629 1630 /* 1631 * This is cleared in frame_done worker, which isn't invoked 1632 * for async commits. So don't set this for async, since it'll 1633 * roll over to the next commit. 1634 */ 1635 if (phys->split_role != ENC_ROLE_SLAVE) 1636 set_bit(i, dpu_enc->frame_busy_mask); 1637 1638 if (!phys->ops.needs_single_flush || 1639 !phys->ops.needs_single_flush(phys)) 1640 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1641 else if (ctl->ops.get_pending_flush) 1642 pending_flush |= ctl->ops.get_pending_flush(ctl); 1643 } 1644 1645 /* for split flush, combine pending flush masks and send to master */ 1646 if (pending_flush && dpu_enc->cur_master) { 1647 _dpu_encoder_trigger_flush( 1648 &dpu_enc->base, 1649 dpu_enc->cur_master, 1650 pending_flush); 1651 } 1652 1653 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1654 1655 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1656 } 1657 1658 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1659 { 1660 struct dpu_encoder_virt *dpu_enc; 1661 struct dpu_encoder_phys *phys; 1662 unsigned int i; 1663 struct dpu_hw_ctl *ctl; 1664 struct msm_display_info *disp_info; 1665 1666 if (!drm_enc) { 1667 DPU_ERROR("invalid encoder\n"); 1668 return; 1669 } 1670 dpu_enc = to_dpu_encoder_virt(drm_enc); 1671 disp_info = &dpu_enc->disp_info; 1672 1673 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1674 phys = dpu_enc->phys_encs[i]; 1675 1676 ctl = phys->hw_ctl; 1677 if (ctl->ops.clear_pending_flush) 1678 ctl->ops.clear_pending_flush(ctl); 1679 1680 /* update only for command mode primary ctl */ 1681 if ((phys == dpu_enc->cur_master) && 1682 disp_info->is_cmd_mode 1683 && ctl->ops.trigger_pending) 1684 ctl->ops.trigger_pending(ctl); 1685 } 1686 } 1687 1688 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1689 struct drm_display_mode *mode) 1690 { 1691 u64 pclk_rate; 1692 u32 pclk_period; 1693 u32 line_time; 1694 1695 /* 1696 * For linetime calculation, only operate on master encoder. 1697 */ 1698 if (!dpu_enc->cur_master) 1699 return 0; 1700 1701 if (!dpu_enc->cur_master->ops.get_line_count) { 1702 DPU_ERROR("get_line_count function not defined\n"); 1703 return 0; 1704 } 1705 1706 pclk_rate = mode->clock; /* pixel clock in kHz */ 1707 if (pclk_rate == 0) { 1708 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1709 return 0; 1710 } 1711 1712 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1713 if (pclk_period == 0) { 1714 DPU_ERROR("pclk period is 0\n"); 1715 return 0; 1716 } 1717 1718 /* 1719 * Line time calculation based on Pixel clock and HTOTAL. 1720 * Final unit is in ns. 1721 */ 1722 line_time = (pclk_period * mode->htotal) / 1000; 1723 if (line_time == 0) { 1724 DPU_ERROR("line time calculation is 0\n"); 1725 return 0; 1726 } 1727 1728 DPU_DEBUG_ENC(dpu_enc, 1729 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1730 pclk_rate, pclk_period, line_time); 1731 1732 return line_time; 1733 } 1734 1735 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1736 { 1737 struct drm_display_mode *mode; 1738 struct dpu_encoder_virt *dpu_enc; 1739 u32 cur_line; 1740 u32 line_time; 1741 u32 vtotal, time_to_vsync; 1742 ktime_t cur_time; 1743 1744 dpu_enc = to_dpu_encoder_virt(drm_enc); 1745 1746 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1747 DPU_ERROR("crtc/crtc state object is NULL\n"); 1748 return -EINVAL; 1749 } 1750 mode = &drm_enc->crtc->state->adjusted_mode; 1751 1752 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1753 if (!line_time) 1754 return -EINVAL; 1755 1756 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1757 1758 vtotal = mode->vtotal; 1759 if (cur_line >= vtotal) 1760 time_to_vsync = line_time * vtotal; 1761 else 1762 time_to_vsync = line_time * (vtotal - cur_line); 1763 1764 if (time_to_vsync == 0) { 1765 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1766 vtotal); 1767 return -EINVAL; 1768 } 1769 1770 cur_time = ktime_get(); 1771 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1772 1773 DPU_DEBUG_ENC(dpu_enc, 1774 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1775 cur_line, vtotal, time_to_vsync, 1776 ktime_to_ms(cur_time), 1777 ktime_to_ms(*wakeup_time)); 1778 return 0; 1779 } 1780 1781 static u32 1782 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, 1783 u32 enc_ip_width) 1784 { 1785 int ssm_delay, total_pixels, soft_slice_per_enc; 1786 1787 soft_slice_per_enc = enc_ip_width / dsc->slice_width; 1788 1789 /* 1790 * minimum number of initial line pixels is a sum of: 1791 * 1. sub-stream multiplexer delay (83 groups for 8bpc, 1792 * 91 for 10 bpc) * 3 1793 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 1794 * 3. the initial xmit delay 1795 * 4. total pipeline delay through the "lock step" of encoder (47) 1796 * 5. 6 additional pixels as the output of the rate buffer is 1797 * 48 bits wide 1798 */ 1799 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); 1800 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; 1801 if (soft_slice_per_enc > 1) 1802 total_pixels += (ssm_delay * 3); 1803 return DIV_ROUND_UP(total_pixels, dsc->slice_width); 1804 } 1805 1806 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl, 1807 struct dpu_hw_dsc *hw_dsc, 1808 struct dpu_hw_pingpong *hw_pp, 1809 struct drm_dsc_config *dsc, 1810 u32 common_mode, 1811 u32 initial_lines) 1812 { 1813 if (hw_dsc->ops.dsc_config) 1814 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines); 1815 1816 if (hw_dsc->ops.dsc_config_thresh) 1817 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); 1818 1819 if (hw_pp->ops.setup_dsc) 1820 hw_pp->ops.setup_dsc(hw_pp); 1821 1822 if (hw_dsc->ops.dsc_bind_pingpong_blk) 1823 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx); 1824 1825 if (hw_pp->ops.enable_dsc) 1826 hw_pp->ops.enable_dsc(hw_pp); 1827 1828 if (ctl->ops.update_pending_flush_dsc) 1829 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 1830 } 1831 1832 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 1833 struct drm_dsc_config *dsc) 1834 { 1835 /* coding only for 2LM, 2enc, 1 dsc config */ 1836 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 1837 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 1838 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 1839 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 1840 int this_frame_slices; 1841 int intf_ip_w, enc_ip_w; 1842 int dsc_common_mode; 1843 int pic_width; 1844 u32 initial_lines; 1845 int i; 1846 1847 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1848 hw_pp[i] = dpu_enc->hw_pp[i]; 1849 hw_dsc[i] = dpu_enc->hw_dsc[i]; 1850 1851 if (!hw_pp[i] || !hw_dsc[i]) { 1852 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); 1853 return; 1854 } 1855 } 1856 1857 dsc_common_mode = 0; 1858 pic_width = dsc->pic_width; 1859 1860 dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL; 1861 if (enc_master->intf_mode == INTF_MODE_VIDEO) 1862 dsc_common_mode |= DSC_MODE_VIDEO; 1863 1864 this_frame_slices = pic_width / dsc->slice_width; 1865 intf_ip_w = this_frame_slices * dsc->slice_width; 1866 1867 /* 1868 * dsc merge case: when using 2 encoders for the same stream, 1869 * no. of slices need to be same on both the encoders. 1870 */ 1871 enc_ip_w = intf_ip_w / 2; 1872 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); 1873 1874 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1875 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], 1876 dsc, dsc_common_mode, initial_lines); 1877 } 1878 1879 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1880 { 1881 struct dpu_encoder_virt *dpu_enc; 1882 struct dpu_encoder_phys *phys; 1883 bool needs_hw_reset = false; 1884 unsigned int i; 1885 1886 dpu_enc = to_dpu_encoder_virt(drm_enc); 1887 1888 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1889 1890 /* prepare for next kickoff, may include waiting on previous kickoff */ 1891 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1892 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1893 phys = dpu_enc->phys_encs[i]; 1894 if (phys->ops.prepare_for_kickoff) 1895 phys->ops.prepare_for_kickoff(phys); 1896 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1897 needs_hw_reset = true; 1898 } 1899 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1900 1901 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1902 1903 /* if any phys needs reset, reset all phys, in-order */ 1904 if (needs_hw_reset) { 1905 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1906 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1907 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1908 } 1909 } 1910 1911 if (dpu_enc->dsc) 1912 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 1913 } 1914 1915 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 1916 { 1917 struct dpu_encoder_virt *dpu_enc; 1918 unsigned int i; 1919 struct dpu_encoder_phys *phys; 1920 1921 dpu_enc = to_dpu_encoder_virt(drm_enc); 1922 1923 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { 1924 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1925 phys = dpu_enc->phys_encs[i]; 1926 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) { 1927 DPU_DEBUG("invalid FB not kicking off\n"); 1928 return false; 1929 } 1930 } 1931 } 1932 1933 return true; 1934 } 1935 1936 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1937 { 1938 struct dpu_encoder_virt *dpu_enc; 1939 struct dpu_encoder_phys *phys; 1940 unsigned long timeout_ms; 1941 unsigned int i; 1942 1943 DPU_ATRACE_BEGIN("encoder_kickoff"); 1944 dpu_enc = to_dpu_encoder_virt(drm_enc); 1945 1946 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1947 1948 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1949 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1950 1951 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1952 mod_timer(&dpu_enc->frame_done_timer, 1953 jiffies + msecs_to_jiffies(timeout_ms)); 1954 1955 /* All phys encs are ready to go, trigger the kickoff */ 1956 _dpu_encoder_kickoff_phys(dpu_enc); 1957 1958 /* allow phys encs to handle any post-kickoff business */ 1959 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1960 phys = dpu_enc->phys_encs[i]; 1961 if (phys->ops.handle_post_kickoff) 1962 phys->ops.handle_post_kickoff(phys); 1963 } 1964 1965 DPU_ATRACE_END("encoder_kickoff"); 1966 } 1967 1968 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) 1969 { 1970 struct dpu_hw_mixer_cfg mixer; 1971 int i, num_lm; 1972 struct dpu_global_state *global_state; 1973 struct dpu_hw_blk *hw_lm[2]; 1974 struct dpu_hw_mixer *hw_mixer[2]; 1975 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 1976 1977 memset(&mixer, 0, sizeof(mixer)); 1978 1979 /* reset all mixers for this encoder */ 1980 if (phys_enc->hw_ctl->ops.clear_all_blendstages) 1981 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl); 1982 1983 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); 1984 1985 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, 1986 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1987 1988 for (i = 0; i < num_lm; i++) { 1989 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); 1990 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer) 1991 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx); 1992 1993 /* clear all blendstages */ 1994 if (phys_enc->hw_ctl->ops.setup_blendstage) 1995 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); 1996 } 1997 } 1998 1999 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl, 2000 struct dpu_hw_dsc *hw_dsc, 2001 struct dpu_hw_pingpong *hw_pp) 2002 { 2003 if (hw_dsc->ops.dsc_disable) 2004 hw_dsc->ops.dsc_disable(hw_dsc); 2005 2006 if (hw_pp->ops.disable_dsc) 2007 hw_pp->ops.disable_dsc(hw_pp); 2008 2009 if (hw_dsc->ops.dsc_bind_pingpong_blk) 2010 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE); 2011 2012 if (ctl->ops.update_pending_flush_dsc) 2013 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2014 } 2015 2016 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) 2017 { 2018 /* coding only for 2LM, 2enc, 1 dsc config */ 2019 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2020 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2021 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2022 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2023 int i; 2024 2025 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2026 hw_pp[i] = dpu_enc->hw_pp[i]; 2027 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2028 2029 if (hw_pp[i] && hw_dsc[i]) 2030 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]); 2031 } 2032 } 2033 2034 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2035 { 2036 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2037 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 2038 int i; 2039 struct dpu_encoder_virt *dpu_enc; 2040 2041 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2042 2043 phys_enc->hw_ctl->ops.reset(ctl); 2044 2045 dpu_encoder_helper_reset_mixers(phys_enc); 2046 2047 /* 2048 * TODO: move the once-only operation like CTL flush/trigger 2049 * into dpu_encoder_virt_disable() and all operations which need 2050 * to be done per phys encoder into the phys_disable() op. 2051 */ 2052 if (phys_enc->hw_wb) { 2053 /* disable the PP block */ 2054 if (phys_enc->hw_wb->ops.bind_pingpong_blk) 2055 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); 2056 2057 /* mark WB flush as pending */ 2058 if (phys_enc->hw_ctl->ops.update_pending_flush_wb) 2059 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); 2060 } else { 2061 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2062 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) 2063 phys_enc->hw_intf->ops.bind_pingpong_blk( 2064 dpu_enc->phys_encs[i]->hw_intf, 2065 PINGPONG_NONE); 2066 2067 /* mark INTF flush as pending */ 2068 if (phys_enc->hw_ctl->ops.update_pending_flush_intf) 2069 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl, 2070 dpu_enc->phys_encs[i]->hw_intf->idx); 2071 } 2072 } 2073 2074 /* reset the merge 3D HW block */ 2075 if (phys_enc->hw_pp->merge_3d) { 2076 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, 2077 BLEND_3D_NONE); 2078 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d) 2079 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl, 2080 phys_enc->hw_pp->merge_3d->idx); 2081 } 2082 2083 if (phys_enc->hw_cdm) { 2084 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) 2085 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, 2086 PINGPONG_NONE); 2087 if (phys_enc->hw_ctl->ops.update_pending_flush_cdm) 2088 phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl, 2089 phys_enc->hw_cdm->idx); 2090 } 2091 2092 if (dpu_enc->dsc) { 2093 dpu_encoder_unprep_dsc(dpu_enc); 2094 dpu_enc->dsc = NULL; 2095 } 2096 2097 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 2098 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2099 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 2100 2101 if (phys_enc->hw_intf) 2102 intf_cfg.intf = phys_enc->hw_intf->idx; 2103 if (phys_enc->hw_wb) 2104 intf_cfg.wb = phys_enc->hw_wb->idx; 2105 2106 if (phys_enc->hw_pp->merge_3d) 2107 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 2108 2109 if (ctl->ops.reset_intf_cfg) 2110 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); 2111 2112 ctl->ops.trigger_flush(ctl); 2113 ctl->ops.trigger_start(ctl); 2114 ctl->ops.clear_pending_flush(ctl); 2115 } 2116 2117 #ifdef CONFIG_DEBUG_FS 2118 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 2119 { 2120 struct drm_encoder *drm_enc = s->private; 2121 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 2122 int i; 2123 2124 mutex_lock(&dpu_enc->enc_lock); 2125 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2126 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2127 2128 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d", 2129 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1, 2130 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1, 2131 atomic_read(&phys->vsync_cnt), 2132 atomic_read(&phys->underrun_cnt), 2133 atomic_read(&dpu_enc->frame_done_timeout_cnt)); 2134 2135 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode)); 2136 } 2137 mutex_unlock(&dpu_enc->enc_lock); 2138 2139 return 0; 2140 } 2141 2142 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status); 2143 2144 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root) 2145 { 2146 /* don't error check these */ 2147 debugfs_create_file("status", 0600, 2148 root, drm_enc, &_dpu_encoder_status_fops); 2149 } 2150 #else 2151 #define dpu_encoder_debugfs_init NULL 2152 #endif 2153 2154 static int dpu_encoder_virt_add_phys_encs( 2155 struct drm_device *dev, 2156 struct msm_display_info *disp_info, 2157 struct dpu_encoder_virt *dpu_enc, 2158 struct dpu_enc_phys_init_params *params) 2159 { 2160 struct dpu_encoder_phys *enc = NULL; 2161 2162 DPU_DEBUG_ENC(dpu_enc, "\n"); 2163 2164 /* 2165 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 2166 * in this function, check up-front. 2167 */ 2168 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 2169 ARRAY_SIZE(dpu_enc->phys_encs)) { 2170 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 2171 dpu_enc->num_phys_encs); 2172 return -EINVAL; 2173 } 2174 2175 2176 if (disp_info->intf_type == INTF_WB) { 2177 enc = dpu_encoder_phys_wb_init(dev, params); 2178 2179 if (IS_ERR(enc)) { 2180 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", 2181 PTR_ERR(enc)); 2182 return PTR_ERR(enc); 2183 } 2184 2185 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2186 ++dpu_enc->num_phys_encs; 2187 } else if (disp_info->is_cmd_mode) { 2188 enc = dpu_encoder_phys_cmd_init(dev, params); 2189 2190 if (IS_ERR(enc)) { 2191 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 2192 PTR_ERR(enc)); 2193 return PTR_ERR(enc); 2194 } 2195 2196 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2197 ++dpu_enc->num_phys_encs; 2198 } else { 2199 enc = dpu_encoder_phys_vid_init(dev, params); 2200 2201 if (IS_ERR(enc)) { 2202 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 2203 PTR_ERR(enc)); 2204 return PTR_ERR(enc); 2205 } 2206 2207 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2208 ++dpu_enc->num_phys_encs; 2209 } 2210 2211 if (params->split_role == ENC_ROLE_SLAVE) 2212 dpu_enc->cur_slave = enc; 2213 else 2214 dpu_enc->cur_master = enc; 2215 2216 return 0; 2217 } 2218 2219 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 2220 struct dpu_kms *dpu_kms, 2221 struct msm_display_info *disp_info) 2222 { 2223 int ret = 0; 2224 int i = 0; 2225 struct dpu_enc_phys_init_params phys_params; 2226 2227 if (!dpu_enc) { 2228 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2229 return -EINVAL; 2230 } 2231 2232 dpu_enc->cur_master = NULL; 2233 2234 memset(&phys_params, 0, sizeof(phys_params)); 2235 phys_params.dpu_kms = dpu_kms; 2236 phys_params.parent = &dpu_enc->base; 2237 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2238 2239 WARN_ON(disp_info->num_of_h_tiles < 1); 2240 2241 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2242 2243 if (disp_info->intf_type != INTF_WB) 2244 dpu_enc->idle_pc_supported = 2245 dpu_kms->catalog->caps->has_idle_pc; 2246 2247 mutex_lock(&dpu_enc->enc_lock); 2248 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2249 /* 2250 * Left-most tile is at index 0, content is controller id 2251 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2252 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2253 */ 2254 u32 controller_id = disp_info->h_tile_instance[i]; 2255 2256 if (disp_info->num_of_h_tiles > 1) { 2257 if (i == 0) 2258 phys_params.split_role = ENC_ROLE_MASTER; 2259 else 2260 phys_params.split_role = ENC_ROLE_SLAVE; 2261 } else { 2262 phys_params.split_role = ENC_ROLE_SOLO; 2263 } 2264 2265 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2266 i, controller_id, phys_params.split_role); 2267 2268 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, 2269 disp_info->intf_type, 2270 controller_id); 2271 2272 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) 2273 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); 2274 2275 if (!phys_params.hw_intf && !phys_params.hw_wb) { 2276 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i); 2277 ret = -EINVAL; 2278 break; 2279 } 2280 2281 if (phys_params.hw_intf && phys_params.hw_wb) { 2282 DPU_ERROR_ENC(dpu_enc, 2283 "invalid phys both intf and wb block at idx: %d\n", i); 2284 ret = -EINVAL; 2285 break; 2286 } 2287 2288 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info, 2289 dpu_enc, &phys_params); 2290 if (ret) { 2291 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2292 break; 2293 } 2294 } 2295 2296 mutex_unlock(&dpu_enc->enc_lock); 2297 2298 return ret; 2299 } 2300 2301 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2302 { 2303 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2304 frame_done_timer); 2305 struct drm_encoder *drm_enc = &dpu_enc->base; 2306 u32 event; 2307 2308 if (!drm_enc->dev) { 2309 DPU_ERROR("invalid parameters\n"); 2310 return; 2311 } 2312 2313 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2314 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2315 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2316 return; 2317 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2318 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2319 return; 2320 } 2321 2322 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n"); 2323 2324 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1) 2325 msm_disp_snapshot_state(drm_enc->dev); 2326 2327 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2328 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2329 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2330 } 2331 2332 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2333 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, 2334 .atomic_disable = dpu_encoder_virt_atomic_disable, 2335 .atomic_enable = dpu_encoder_virt_atomic_enable, 2336 .atomic_check = dpu_encoder_virt_atomic_check, 2337 }; 2338 2339 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2340 .debugfs_init = dpu_encoder_debugfs_init, 2341 }; 2342 2343 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2344 int drm_enc_mode, 2345 struct msm_display_info *disp_info) 2346 { 2347 struct msm_drm_private *priv = dev->dev_private; 2348 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2349 struct dpu_encoder_virt *dpu_enc; 2350 int ret; 2351 2352 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base, 2353 &dpu_encoder_funcs, drm_enc_mode, NULL); 2354 if (IS_ERR(dpu_enc)) 2355 return ERR_CAST(dpu_enc); 2356 2357 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2358 2359 spin_lock_init(&dpu_enc->enc_spinlock); 2360 dpu_enc->enabled = false; 2361 mutex_init(&dpu_enc->enc_lock); 2362 mutex_init(&dpu_enc->rc_lock); 2363 2364 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2365 if (ret) { 2366 DPU_ERROR("failed to setup encoder\n"); 2367 return ERR_PTR(-ENOMEM); 2368 } 2369 2370 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2371 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 2372 timer_setup(&dpu_enc->frame_done_timer, 2373 dpu_encoder_frame_done_timeout, 0); 2374 2375 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2376 dpu_encoder_off_work); 2377 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2378 2379 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2380 2381 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2382 2383 return &dpu_enc->base; 2384 } 2385 2386 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2387 enum msm_event_wait event) 2388 { 2389 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2390 struct dpu_encoder_virt *dpu_enc = NULL; 2391 int i, ret = 0; 2392 2393 if (!drm_enc) { 2394 DPU_ERROR("invalid encoder\n"); 2395 return -EINVAL; 2396 } 2397 dpu_enc = to_dpu_encoder_virt(drm_enc); 2398 DPU_DEBUG_ENC(dpu_enc, "\n"); 2399 2400 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2401 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2402 2403 switch (event) { 2404 case MSM_ENC_COMMIT_DONE: 2405 fn_wait = phys->ops.wait_for_commit_done; 2406 break; 2407 case MSM_ENC_TX_COMPLETE: 2408 fn_wait = phys->ops.wait_for_tx_complete; 2409 break; 2410 default: 2411 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2412 event); 2413 return -EINVAL; 2414 } 2415 2416 if (fn_wait) { 2417 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2418 ret = fn_wait(phys); 2419 DPU_ATRACE_END("wait_for_completion_event"); 2420 if (ret) 2421 return ret; 2422 } 2423 } 2424 2425 return ret; 2426 } 2427 2428 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2429 { 2430 struct dpu_encoder_virt *dpu_enc = NULL; 2431 2432 if (!encoder) { 2433 DPU_ERROR("invalid encoder\n"); 2434 return INTF_MODE_NONE; 2435 } 2436 dpu_enc = to_dpu_encoder_virt(encoder); 2437 2438 if (dpu_enc->cur_master) 2439 return dpu_enc->cur_master->intf_mode; 2440 2441 if (dpu_enc->num_phys_encs) 2442 return dpu_enc->phys_encs[0]->intf_mode; 2443 2444 return INTF_MODE_NONE; 2445 } 2446 2447 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2448 { 2449 struct drm_encoder *encoder = phys_enc->parent; 2450 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2451 2452 return dpu_enc->dsc_mask; 2453 } 2454 2455 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, 2456 struct dpu_enc_phys_init_params *p) 2457 { 2458 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 2459 phys_enc->hw_intf = p->hw_intf; 2460 phys_enc->hw_wb = p->hw_wb; 2461 phys_enc->parent = p->parent; 2462 phys_enc->dpu_kms = p->dpu_kms; 2463 phys_enc->split_role = p->split_role; 2464 phys_enc->enc_spinlock = p->enc_spinlock; 2465 phys_enc->enable_state = DPU_ENC_DISABLED; 2466 2467 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 2468 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); 2469 2470 atomic_set(&phys_enc->vsync_cnt, 0); 2471 atomic_set(&phys_enc->underrun_cnt, 0); 2472 2473 init_waitqueue_head(&phys_enc->pending_kickoff_wq); 2474 } 2475