1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef UFS_QCOM_H_ 6 #define UFS_QCOM_H_ 7 8 #include <linux/reset-controller.h> 9 #include <linux/reset.h> 10 #include <ufs/ufshcd.h> 11 12 #define MAX_UFS_QCOM_HOSTS 1 13 #define MAX_U32 (~(u32)0) 14 #define MPHY_TX_FSM_STATE 0x41 15 #define TX_FSM_HIBERN8 0x1 16 #define HBRN8_POLL_TOUT_MS 100 17 #define DEFAULT_CLK_RATE_HZ 1000000 18 #define BUS_VECTOR_NAME_LEN 32 19 #define MAX_SUPP_MAC 64 20 21 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) 22 #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) 23 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0) 24 25 /* vendor specific pre-defined parameters */ 26 #define SLOW 1 27 #define FAST 2 28 29 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B 30 31 /* QCOM UFS host controller vendor specific registers */ 32 enum { 33 REG_UFS_SYS1CLK_1US = 0xC0, 34 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, 35 REG_UFS_LOCAL_PORT_ID_REG = 0xC8, 36 REG_UFS_PA_ERR_CODE = 0xCC, 37 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ 38 REG_UFS_PARAM0 = 0xD0, 39 /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ 40 REG_UFS_CFG0 = 0xD8, 41 REG_UFS_CFG1 = 0xDC, 42 REG_UFS_CFG2 = 0xE0, 43 REG_UFS_HW_VERSION = 0xE4, 44 45 UFS_TEST_BUS = 0xE8, 46 UFS_TEST_BUS_CTRL_0 = 0xEC, 47 UFS_TEST_BUS_CTRL_1 = 0xF0, 48 UFS_TEST_BUS_CTRL_2 = 0xF4, 49 UFS_UNIPRO_CFG = 0xF8, 50 51 /* 52 * QCOM UFS host controller vendor specific registers 53 * added in HW Version 3.0.0 54 */ 55 UFS_AH8_CFG = 0xFC, 56 57 REG_UFS_CFG3 = 0x271C, 58 }; 59 60 /* QCOM UFS host controller vendor specific debug registers */ 61 enum { 62 UFS_DBG_RD_REG_UAWM = 0x100, 63 UFS_DBG_RD_REG_UARM = 0x200, 64 UFS_DBG_RD_REG_TXUC = 0x300, 65 UFS_DBG_RD_REG_RXUC = 0x400, 66 UFS_DBG_RD_REG_DFC = 0x500, 67 UFS_DBG_RD_REG_TRLUT = 0x600, 68 UFS_DBG_RD_REG_TMRLUT = 0x700, 69 UFS_UFS_DBG_RD_REG_OCSC = 0x800, 70 71 UFS_UFS_DBG_RD_DESC_RAM = 0x1500, 72 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700, 73 UFS_UFS_DBG_RD_RESP_RAM = 0x1800, 74 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900, 75 }; 76 77 enum { 78 UFS_MEM_CQIS_VS = 0x8, 79 }; 80 81 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) 82 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) 83 84 /* bit definitions for REG_UFS_CFG0 register */ 85 #define QUNIPRO_G4_SEL BIT(5) 86 87 /* bit definitions for REG_UFS_CFG1 register */ 88 #define QUNIPRO_SEL BIT(0) 89 #define UFS_PHY_SOFT_RESET BIT(1) 90 #define UTP_DBG_RAMS_EN BIT(17) 91 #define TEST_BUS_EN BIT(18) 92 #define TEST_BUS_SEL GENMASK(22, 19) 93 #define UFS_REG_TEST_BUS_EN BIT(30) 94 95 #define UFS_PHY_RESET_ENABLE 1 96 #define UFS_PHY_RESET_DISABLE 0 97 98 /* bit definitions for REG_UFS_CFG2 register */ 99 #define UAWM_HW_CGC_EN BIT(0) 100 #define UARM_HW_CGC_EN BIT(1) 101 #define TXUC_HW_CGC_EN BIT(2) 102 #define RXUC_HW_CGC_EN BIT(3) 103 #define DFC_HW_CGC_EN BIT(4) 104 #define TRLUT_HW_CGC_EN BIT(5) 105 #define TMRLUT_HW_CGC_EN BIT(6) 106 #define OCSC_HW_CGC_EN BIT(7) 107 108 /* bit definitions for REG_UFS_PARAM0 */ 109 #define MAX_HS_GEAR_MASK GENMASK(6, 4) 110 #define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) 111 112 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ 113 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ 114 115 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ 116 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ 117 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ 118 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) 119 120 /* bit offset */ 121 #define OFFSET_CLK_NS_REG 0xa 122 123 /* bit masks */ 124 #define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) 125 #define MASK_CLK_NS_REG GENMASK(23, 10) 126 127 /* QUniPro Vendor specific attributes */ 128 #define PA_VS_CONFIG_REG1 0x9000 129 #define DME_VS_CORE_CLK_CTRL 0xD002 130 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ 131 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) 132 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF 133 134 static inline void 135 ufs_qcom_get_controller_revision(struct ufs_hba *hba, 136 u8 *major, u16 *minor, u16 *step) 137 { 138 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); 139 140 *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); 141 *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); 142 *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); 143 }; 144 145 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) 146 { 147 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE), 148 REG_UFS_CFG1); 149 150 /* 151 * Make sure assertion of ufs phy reset is written to 152 * register before returning 153 */ 154 mb(); 155 } 156 157 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) 158 { 159 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE), 160 REG_UFS_CFG1); 161 162 /* 163 * Make sure de-assertion of ufs phy reset is written to 164 * register before returning 165 */ 166 mb(); 167 } 168 169 /* Host controller hardware version: major.minor.step */ 170 struct ufs_hw_version { 171 u16 step; 172 u16 minor; 173 u8 major; 174 }; 175 176 struct ufs_qcom_testbus { 177 u8 select_major; 178 u8 select_minor; 179 }; 180 181 struct gpio_desc; 182 183 struct ufs_qcom_host { 184 /* 185 * Set this capability if host controller supports the QUniPro mode 186 * and if driver wants the Host controller to operate in QUniPro mode. 187 * Note: By default this capability will be kept enabled if host 188 * controller supports the QUniPro mode. 189 */ 190 #define UFS_QCOM_CAP_QUNIPRO 0x1 191 192 /* 193 * Set this capability if host controller can retain the secure 194 * configuration even after UFS controller core power collapse. 195 */ 196 #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE 0x2 197 u32 caps; 198 199 struct phy *generic_phy; 200 struct ufs_hba *hba; 201 struct ufs_pa_layer_attr dev_req_params; 202 struct clk *rx_l0_sync_clk; 203 struct clk *tx_l0_sync_clk; 204 struct clk *rx_l1_sync_clk; 205 struct clk *tx_l1_sync_clk; 206 bool is_lane_clks_enabled; 207 208 void __iomem *dev_ref_clk_ctrl_mmio; 209 bool is_dev_ref_clk_enabled; 210 struct ufs_hw_version hw_ver; 211 #ifdef CONFIG_SCSI_UFS_CRYPTO 212 void __iomem *ice_mmio; 213 #endif 214 215 u32 dev_ref_clk_en_mask; 216 217 struct ufs_qcom_testbus testbus; 218 219 /* Reset control of HCI */ 220 struct reset_control *core_reset; 221 struct reset_controller_dev rcdev; 222 223 struct gpio_desc *device_reset; 224 225 u32 hs_gear; 226 227 int esi_base; 228 bool esi_enabled; 229 }; 230 231 static inline u32 232 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) 233 { 234 if (host->hw_ver.major <= 0x02) 235 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); 236 237 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); 238 }; 239 240 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba) 241 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba) 242 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba) 243 244 int ufs_qcom_testbus_config(struct ufs_qcom_host *host); 245 246 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host) 247 { 248 return host->caps & UFS_QCOM_CAP_QUNIPRO; 249 } 250 251 /* ufs-qcom-ice.c */ 252 253 #ifdef CONFIG_SCSI_UFS_CRYPTO 254 int ufs_qcom_ice_init(struct ufs_qcom_host *host); 255 int ufs_qcom_ice_enable(struct ufs_qcom_host *host); 256 int ufs_qcom_ice_resume(struct ufs_qcom_host *host); 257 int ufs_qcom_ice_program_key(struct ufs_hba *hba, 258 const union ufs_crypto_cfg_entry *cfg, int slot); 259 #else 260 static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host) 261 { 262 return 0; 263 } 264 static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host) 265 { 266 return 0; 267 } 268 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 269 { 270 return 0; 271 } 272 #define ufs_qcom_ice_program_key NULL 273 #endif /* !CONFIG_SCSI_UFS_CRYPTO */ 274 275 #endif /* UFS_QCOM_H_ */ 276