1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_NUM_PHYS 5 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 ID_MT7988 = 3, 22 }; 23 24 #define NUM_TRGMII_CTRL 5 25 26 #define TRGMII_BASE(x) (0x10000 + (x)) 27 28 /* Registers to ethsys access */ 29 #define ETHSYS_CLKCFG0 0x2c 30 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 31 32 #define SYSC_REG_RSTCTRL 0x34 33 #define RESET_MCM BIT(2) 34 35 /* Registers to mac forward control for unknown frames */ 36 #define MT7530_MFC 0x10 37 #define BC_FFP(x) (((x) & 0xff) << 24) 38 #define BC_FFP_MASK BC_FFP(~0) 39 #define UNM_FFP(x) (((x) & 0xff) << 16) 40 #define UNM_FFP_MASK UNM_FFP(~0) 41 #define UNU_FFP(x) (((x) & 0xff) << 8) 42 #define UNU_FFP_MASK UNU_FFP(~0) 43 #define CPU_EN BIT(7) 44 #define CPU_PORT_MASK GENMASK(6, 4) 45 #define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) 46 #define MIRROR_EN BIT(3) 47 #define MIRROR_PORT(x) ((x) & 0x7) 48 #define MIRROR_MASK 0x7 49 50 /* Registers for CPU forward control */ 51 #define MT7531_CFC 0x4 52 #define MT7531_MIRROR_EN BIT(19) 53 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16) 54 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) 55 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) 56 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 57 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) 58 59 #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 60 MT7531_CFC : MT7530_MFC) 61 #define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 62 MT7531_MIRROR_EN : MIRROR_EN) 63 #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 64 MT7531_MIRROR_MASK : MIRROR_MASK) 65 66 /* Registers for BPDU and PAE frame control*/ 67 #define MT753X_BPC 0x24 68 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) 69 #define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) 70 #define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x) 71 72 /* Register for :03 and :0E MAC DA frame control */ 73 #define MT753X_RGAC2 0x2c 74 #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) 75 #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) 76 77 enum mt753x_bpdu_port_fw { 78 MT753X_BPDU_FOLLOW_MFC, 79 MT753X_BPDU_CPU_EXCLUDE = 4, 80 MT753X_BPDU_CPU_INCLUDE = 5, 81 MT753X_BPDU_CPU_ONLY = 6, 82 MT753X_BPDU_DROP = 7, 83 }; 84 85 /* Registers for address table access */ 86 #define MT7530_ATA1 0x74 87 #define STATIC_EMP 0 88 #define STATIC_ENT 3 89 #define MT7530_ATA2 0x78 90 #define ATA2_IVL BIT(15) 91 #define ATA2_FID(x) (((x) & 0x7) << 12) 92 93 /* Register for address table write data */ 94 #define MT7530_ATWD 0x7c 95 96 /* Register for address table control */ 97 #define MT7530_ATC 0x80 98 #define ATC_HASH (((x) & 0xfff) << 16) 99 #define ATC_BUSY BIT(15) 100 #define ATC_SRCH_END BIT(14) 101 #define ATC_SRCH_HIT BIT(13) 102 #define ATC_INVALID BIT(12) 103 #define ATC_MAT(x) (((x) & 0xf) << 8) 104 #define ATC_MAT_MACTAB ATC_MAT(0) 105 106 enum mt7530_fdb_cmd { 107 MT7530_FDB_READ = 0, 108 MT7530_FDB_WRITE = 1, 109 MT7530_FDB_FLUSH = 2, 110 MT7530_FDB_START = 4, 111 MT7530_FDB_NEXT = 5, 112 }; 113 114 /* Registers for table search read address */ 115 #define MT7530_TSRA1 0x84 116 #define MAC_BYTE_0 24 117 #define MAC_BYTE_1 16 118 #define MAC_BYTE_2 8 119 #define MAC_BYTE_3 0 120 #define MAC_BYTE_MASK 0xff 121 122 #define MT7530_TSRA2 0x88 123 #define MAC_BYTE_4 24 124 #define MAC_BYTE_5 16 125 #define CVID 0 126 #define CVID_MASK 0xfff 127 128 #define MT7530_ATRD 0x8C 129 #define AGE_TIMER 24 130 #define AGE_TIMER_MASK 0xff 131 #define PORT_MAP 4 132 #define PORT_MAP_MASK 0xff 133 #define ENT_STATUS 2 134 #define ENT_STATUS_MASK 0x3 135 136 /* Register for vlan table control */ 137 #define MT7530_VTCR 0x90 138 #define VTCR_BUSY BIT(31) 139 #define VTCR_INVALID BIT(16) 140 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 141 #define VTCR_VID ((x) & 0xfff) 142 143 enum mt7530_vlan_cmd { 144 /* Read/Write the specified VID entry from VAWD register based 145 * on VID. 146 */ 147 MT7530_VTCR_RD_VID = 0, 148 MT7530_VTCR_WR_VID = 1, 149 }; 150 151 /* Register for setup vlan and acl write data */ 152 #define MT7530_VAWD1 0x94 153 #define PORT_STAG BIT(31) 154 /* Independent VLAN Learning */ 155 #define IVL_MAC BIT(30) 156 /* Egress Tag Consistent */ 157 #define EG_CON BIT(29) 158 /* Per VLAN Egress Tag Control */ 159 #define VTAG_EN BIT(28) 160 /* VLAN Member Control */ 161 #define PORT_MEM(x) (((x) & 0xff) << 16) 162 /* Filter ID */ 163 #define FID(x) (((x) & 0x7) << 1) 164 /* VLAN Entry Valid */ 165 #define VLAN_VALID BIT(0) 166 #define PORT_MEM_SHFT 16 167 #define PORT_MEM_MASK 0xff 168 169 enum mt7530_fid { 170 FID_STANDALONE = 0, 171 FID_BRIDGED = 1, 172 }; 173 174 #define MT7530_VAWD2 0x98 175 /* Egress Tag Control */ 176 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 177 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 178 179 enum mt7530_vlan_egress_attr { 180 MT7530_VLAN_EGRESS_UNTAG = 0, 181 MT7530_VLAN_EGRESS_TAG = 2, 182 MT7530_VLAN_EGRESS_STACK = 3, 183 }; 184 185 /* Register for address age control */ 186 #define MT7530_AAC 0xa0 187 /* Disable ageing */ 188 #define AGE_DIS BIT(20) 189 /* Age count */ 190 #define AGE_CNT_MASK GENMASK(19, 12) 191 #define AGE_CNT_MAX 0xff 192 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 193 /* Age unit */ 194 #define AGE_UNIT_MASK GENMASK(11, 0) 195 #define AGE_UNIT_MAX 0xfff 196 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 197 198 /* Register for port STP state control */ 199 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 200 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 201 #define FID_PST_MASK(fid) FID_PST(fid, 0x3) 202 203 enum mt7530_stp_state { 204 MT7530_STP_DISABLED = 0, 205 MT7530_STP_BLOCKING = 1, 206 MT7530_STP_LISTENING = 1, 207 MT7530_STP_LEARNING = 2, 208 MT7530_STP_FORWARDING = 3 209 }; 210 211 /* Register for port control */ 212 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 213 #define PORT_TX_MIR BIT(9) 214 #define PORT_RX_MIR BIT(8) 215 #define PORT_VLAN(x) ((x) & 0x3) 216 217 enum mt7530_port_mode { 218 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 219 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 220 221 /* Fallback Mode: Forward received frames with ingress ports that do 222 * not belong to the VLAN member. Frames whose VID is not listed on 223 * the VLAN table are forwarded by the PCR_MATRIX members. 224 */ 225 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 226 227 /* Security Mode: Discard any frame due to ingress membership 228 * violation or VID missed on the VLAN table. 229 */ 230 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 231 }; 232 233 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 234 #define PORT_PRI(x) (((x) & 0x7) << 24) 235 #define EG_TAG(x) (((x) & 0x3) << 28) 236 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 237 #define PCR_MATRIX_CLR PCR_MATRIX(0) 238 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 239 240 /* Register for port security control */ 241 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 242 #define SA_DIS BIT(4) 243 244 /* Register for port vlan control */ 245 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 246 #define PORT_SPEC_TAG BIT(5) 247 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 248 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 249 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 250 #define VLAN_ATTR_MASK VLAN_ATTR(3) 251 #define ACC_FRM_MASK GENMASK(1, 0) 252 253 enum mt7530_vlan_port_eg_tag { 254 MT7530_VLAN_EG_DISABLED = 0, 255 MT7530_VLAN_EG_CONSISTENT = 1, 256 }; 257 258 enum mt7530_vlan_port_attr { 259 MT7530_VLAN_USER = 0, 260 MT7530_VLAN_TRANSPARENT = 3, 261 }; 262 263 enum mt7530_vlan_port_acc_frm { 264 MT7530_VLAN_ACC_ALL = 0, 265 MT7530_VLAN_ACC_TAGGED = 1, 266 MT7530_VLAN_ACC_UNTAGGED = 2, 267 }; 268 269 #define STAG_VPID (((x) & 0xffff) << 16) 270 271 /* Register for port port-and-protocol based vlan 1 control */ 272 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 273 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 274 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 275 #define G0_PORT_VID_DEF G0_PORT_VID(0) 276 277 /* Register for port MAC control register */ 278 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 279 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 280 #define PMCR_EXT_PHY BIT(17) 281 #define PMCR_MAC_MODE BIT(16) 282 #define PMCR_FORCE_MODE BIT(15) 283 #define PMCR_TX_EN BIT(14) 284 #define PMCR_RX_EN BIT(13) 285 #define PMCR_BACKOFF_EN BIT(9) 286 #define PMCR_BACKPR_EN BIT(8) 287 #define PMCR_FORCE_EEE1G BIT(7) 288 #define PMCR_FORCE_EEE100 BIT(6) 289 #define PMCR_TX_FC_EN BIT(5) 290 #define PMCR_RX_FC_EN BIT(4) 291 #define PMCR_FORCE_SPEED_1000 BIT(3) 292 #define PMCR_FORCE_SPEED_100 BIT(2) 293 #define PMCR_FORCE_FDX BIT(1) 294 #define PMCR_FORCE_LNK BIT(0) 295 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 296 PMCR_FORCE_SPEED_1000) 297 #define MT7531_FORCE_LNK BIT(31) 298 #define MT7531_FORCE_SPD BIT(30) 299 #define MT7531_FORCE_DPX BIT(29) 300 #define MT7531_FORCE_RX_FC BIT(28) 301 #define MT7531_FORCE_TX_FC BIT(27) 302 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ 303 MT7531_FORCE_SPD | \ 304 MT7531_FORCE_DPX | \ 305 MT7531_FORCE_RX_FC | \ 306 MT7531_FORCE_TX_FC) 307 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 308 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 309 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 310 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ 311 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) 312 313 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) 314 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) 315 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) 316 #define LPI_THRESH_MASK GENMASK(15, 4) 317 #define LPI_THRESH_SHT 4 318 #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) 319 #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) 320 #define LPI_MODE_EN BIT(0) 321 322 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 323 #define PMSR_EEE1G BIT(7) 324 #define PMSR_EEE100M BIT(6) 325 #define PMSR_RX_FC BIT(5) 326 #define PMSR_TX_FC BIT(4) 327 #define PMSR_SPEED_1000 BIT(3) 328 #define PMSR_SPEED_100 BIT(2) 329 #define PMSR_SPEED_10 0x00 330 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 331 #define PMSR_DPX BIT(1) 332 #define PMSR_LINK BIT(0) 333 334 /* Register for port debug count */ 335 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 336 #define MT7531_DIS_CLR BIT(31) 337 338 #define MT7530_GMACCR 0x30e0 339 #define MAX_RX_JUMBO(x) ((x) << 2) 340 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 341 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 342 #define MAX_RX_PKT_LEN_1522 0x0 343 #define MAX_RX_PKT_LEN_1536 0x1 344 #define MAX_RX_PKT_LEN_1552 0x2 345 #define MAX_RX_PKT_LEN_JUMBO 0x3 346 347 /* Register for MIB */ 348 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 349 #define MT7530_MIB_CCR 0x4fe0 350 #define CCR_MIB_ENABLE BIT(31) 351 #define CCR_RX_OCT_CNT_GOOD BIT(7) 352 #define CCR_RX_OCT_CNT_BAD BIT(6) 353 #define CCR_TX_OCT_CNT_GOOD BIT(5) 354 #define CCR_TX_OCT_CNT_BAD BIT(4) 355 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 356 CCR_RX_OCT_CNT_BAD | \ 357 CCR_TX_OCT_CNT_GOOD | \ 358 CCR_TX_OCT_CNT_BAD) 359 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 360 CCR_RX_OCT_CNT_GOOD | \ 361 CCR_RX_OCT_CNT_BAD | \ 362 CCR_TX_OCT_CNT_GOOD | \ 363 CCR_TX_OCT_CNT_BAD) 364 365 /* MT7531 SGMII register group */ 366 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000) 367 #define MT7531_PHYA_CTRL_SIGNAL3 0x128 368 369 /* Register for system reset */ 370 #define MT7530_SYS_CTRL 0x7000 371 #define SYS_CTRL_PHY_RST BIT(2) 372 #define SYS_CTRL_SW_RST BIT(1) 373 #define SYS_CTRL_REG_RST BIT(0) 374 375 /* Register for system interrupt */ 376 #define MT7530_SYS_INT_EN 0x7008 377 378 /* Register for system interrupt status */ 379 #define MT7530_SYS_INT_STS 0x700c 380 381 /* Register for PHY Indirect Access Control */ 382 #define MT7531_PHY_IAC 0x701C 383 #define MT7531_PHY_ACS_ST BIT(31) 384 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 385 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 386 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 387 #define MT7531_MDIO_ST_MASK (0x3 << 16) 388 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 389 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 390 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 391 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 392 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 393 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 394 395 enum mt7531_phy_iac_cmd { 396 MT7531_MDIO_ADDR = 0, 397 MT7531_MDIO_WRITE = 1, 398 MT7531_MDIO_READ = 2, 399 MT7531_MDIO_READ_CL45 = 3, 400 }; 401 402 /* MDIO_ST: MDIO start field */ 403 enum mt7531_mdio_st { 404 MT7531_MDIO_ST_CL45 = 0, 405 MT7531_MDIO_ST_CL22 = 1, 406 }; 407 408 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 409 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 410 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 411 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 412 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 413 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 414 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 415 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 416 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 417 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 418 419 /* Register for RGMII clock phase */ 420 #define MT7531_CLKGEN_CTRL 0x7500 421 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 422 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 423 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 424 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 425 #define RXCLK_NO_DELAY BIT(5) 426 #define TXCLK_NO_REVERSE BIT(4) 427 #define GP_MODE(x) (((x) & 0x3) << 1) 428 #define GP_MODE_MASK GENMASK(2, 1) 429 #define GP_CLK_EN BIT(0) 430 431 enum mt7531_gp_mode { 432 MT7531_GP_MODE_RGMII = 0, 433 MT7531_GP_MODE_MII = 1, 434 MT7531_GP_MODE_REV_MII = 2 435 }; 436 437 enum mt7531_clk_skew { 438 MT7531_CLK_SKEW_NO_CHG = 0, 439 MT7531_CLK_SKEW_DLY_100PPS = 1, 440 MT7531_CLK_SKEW_DLY_200PPS = 2, 441 MT7531_CLK_SKEW_REVERSE = 3, 442 }; 443 444 /* Register for hw trap status */ 445 #define MT7530_HWTRAP 0x7800 446 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 447 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 448 #define HWTRAP_XTAL_40MHZ (BIT(10)) 449 #define HWTRAP_XTAL_20MHZ (BIT(9)) 450 451 #define MT7531_HWTRAP 0x7800 452 #define HWTRAP_XTAL_FSEL_MASK BIT(7) 453 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7) 454 #define HWTRAP_XTAL_FSEL_40MHZ 0 455 /* Unique fields of (M)HWSTRAP for MT7531 */ 456 #define XTAL_FSEL_S 7 457 #define XTAL_FSEL_M BIT(7) 458 #define PHY_EN BIT(6) 459 #define CHG_STRAP BIT(8) 460 461 /* Register for hw trap modification */ 462 #define MT7530_MHWTRAP 0x7804 463 #define MHWTRAP_PHY0_SEL BIT(20) 464 #define MHWTRAP_MANUAL BIT(16) 465 #define MHWTRAP_P5_MAC_SEL BIT(13) 466 #define MHWTRAP_P6_DIS BIT(8) 467 #define MHWTRAP_P5_RGMII_MODE BIT(7) 468 #define MHWTRAP_P5_DIS BIT(6) 469 #define MHWTRAP_PHY_ACCESS BIT(5) 470 471 /* Register for TOP signal control */ 472 #define MT7530_TOP_SIG_CTRL 0x7808 473 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 474 475 #define MT7531_TOP_SIG_SR 0x780c 476 #define PAD_DUAL_SGMII_EN BIT(1) 477 #define PAD_MCM_SMI_EN BIT(0) 478 479 #define MT7530_IO_DRV_CR 0x7810 480 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 481 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 482 483 #define MT7531_CHIP_REV 0x781C 484 485 #define MT7531_PLLGP_EN 0x7820 486 #define EN_COREPLL BIT(2) 487 #define SW_CLKSW BIT(1) 488 #define SW_PLLGP BIT(0) 489 490 #define MT7530_P6ECR 0x7830 491 #define P6_INTF_MODE_MASK 0x3 492 #define P6_INTF_MODE(x) ((x) & 0x3) 493 494 #define MT7531_PLLGP_CR0 0x78a8 495 #define RG_COREPLL_EN BIT(22) 496 #define RG_COREPLL_POSDIV_S 23 497 #define RG_COREPLL_POSDIV_M 0x3800000 498 #define RG_COREPLL_SDM_PCW_S 1 499 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 500 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 501 502 /* Registers for RGMII and SGMII PLL clock */ 503 #define MT7531_ANA_PLLGP_CR2 0x78b0 504 #define MT7531_ANA_PLLGP_CR5 0x78bc 505 506 /* Registers for TRGMII on the both side */ 507 #define MT7530_TRGMII_RCK_CTRL 0x7a00 508 #define RX_RST BIT(31) 509 #define RXC_DQSISEL BIT(30) 510 #define DQSI1_TAP_MASK (0x7f << 8) 511 #define DQSI0_TAP_MASK 0x7f 512 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 513 #define DQSI0_TAP(x) ((x) & 0x7f) 514 515 #define MT7530_TRGMII_RCK_RTT 0x7a04 516 #define DQS1_GATE BIT(31) 517 #define DQS0_GATE BIT(30) 518 519 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 520 #define BSLIP_EN BIT(31) 521 #define EDGE_CHK BIT(30) 522 #define RD_TAP_MASK 0x7f 523 #define RD_TAP(x) ((x) & 0x7f) 524 525 #define MT7530_TRGMII_TXCTRL 0x7a40 526 #define TRAIN_TXEN BIT(31) 527 #define TXC_INV BIT(30) 528 #define TX_RST BIT(28) 529 530 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 531 #define TD_DM_DRVP(x) ((x) & 0xf) 532 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 533 534 #define MT7530_TRGMII_TCK_CTRL 0x7a78 535 #define TCK_TAP(x) (((x) & 0xf) << 8) 536 537 #define MT7530_P5RGMIIRXCR 0x7b00 538 #define CSR_RGMII_EDGE_ALIGN BIT(8) 539 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 540 541 #define MT7530_P5RGMIITXCR 0x7b04 542 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 543 544 /* Registers for GPIO mode */ 545 #define MT7531_GPIO_MODE0 0x7c0c 546 #define MT7531_GPIO0_MASK GENMASK(3, 0) 547 #define MT7531_GPIO0_INTERRUPT 1 548 549 #define MT7531_GPIO_MODE1 0x7c10 550 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 551 #define MT7531_EXT_P_MDC_11 (2 << 12) 552 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 553 #define MT7531_EXT_P_MDIO_12 (2 << 16) 554 555 /* Registers for LED GPIO control (MT7530 only) 556 * All registers follow this pattern: 557 * [ 2: 0] port 0 558 * [ 6: 4] port 1 559 * [10: 8] port 2 560 * [14:12] port 3 561 * [18:16] port 4 562 */ 563 564 /* LED enable, 0: Disable, 1: Enable (Default) */ 565 #define MT7530_LED_EN 0x7d00 566 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 567 #define MT7530_LED_IO_MODE 0x7d04 568 /* GPIO direction, 0: Input, 1: Output */ 569 #define MT7530_LED_GPIO_DIR 0x7d10 570 /* GPIO output enable, 0: Disable, 1: Enable */ 571 #define MT7530_LED_GPIO_OE 0x7d14 572 /* GPIO value, 0: Low, 1: High */ 573 #define MT7530_LED_GPIO_DATA 0x7d18 574 575 #define MT7530_CREV 0x7ffc 576 #define CHIP_NAME_SHIFT 16 577 #define MT7530_ID 0x7530 578 579 #define MT7531_CREV 0x781C 580 #define CHIP_REV_M 0x0f 581 #define MT7531_ID 0x7531 582 583 /* Registers for core PLL access through mmd indirect */ 584 #define CORE_PLL_GROUP2 0x401 585 #define RG_SYSPLL_EN_NORMAL BIT(15) 586 #define RG_SYSPLL_VODEN BIT(14) 587 #define RG_SYSPLL_LF BIT(13) 588 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 589 #define RG_SYSPLL_LVROD_EN BIT(10) 590 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 591 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 592 #define RG_SYSPLL_FBKSEL BIT(4) 593 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 594 595 #define CORE_PLL_GROUP4 0x403 596 #define RG_SYSPLL_DDSFBK_EN BIT(12) 597 #define RG_SYSPLL_BIAS_EN BIT(11) 598 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 599 #define MT7531_PHY_PLL_OFF BIT(5) 600 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 601 602 #define MT753X_CTRL_PHY_ADDR 0 603 604 #define CORE_PLL_GROUP5 0x404 605 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 606 607 #define CORE_PLL_GROUP6 0x405 608 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 609 610 #define CORE_PLL_GROUP7 0x406 611 #define RG_LCDDS_PWDB BIT(15) 612 #define RG_LCDDS_ISO_EN BIT(13) 613 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 614 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 615 616 #define CORE_PLL_GROUP10 0x409 617 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 618 619 #define CORE_PLL_GROUP11 0x40a 620 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 621 622 #define CORE_GSWPLL_GRP1 0x40d 623 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 624 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 625 #define RG_GSWPLL_EN_PRE BIT(11) 626 #define RG_GSWPLL_FBKSEL BIT(10) 627 #define RG_GSWPLL_BP BIT(9) 628 #define RG_GSWPLL_BR BIT(8) 629 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 630 631 #define CORE_GSWPLL_GRP2 0x40e 632 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 633 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 634 635 #define CORE_TRGMII_GSW_CLK_CG 0x410 636 #define REG_GSWCK_EN BIT(0) 637 #define REG_TRGMIICK_EN BIT(1) 638 639 #define MIB_DESC(_s, _o, _n) \ 640 { \ 641 .size = (_s), \ 642 .offset = (_o), \ 643 .name = (_n), \ 644 } 645 646 struct mt7530_mib_desc { 647 unsigned int size; 648 unsigned int offset; 649 const char *name; 650 }; 651 652 struct mt7530_fdb { 653 u16 vid; 654 u8 port_mask; 655 u8 aging; 656 u8 mac[6]; 657 bool noarp; 658 }; 659 660 /* struct mt7530_port - This is the main data structure for holding the state 661 * of the port. 662 * @enable: The status used for show port is enabled or not. 663 * @pm: The matrix used to show all connections with the port. 664 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 665 * untagged frames will be assigned to the related VLAN. 666 * @sgmii_pcs: Pointer to PCS instance for SerDes ports 667 */ 668 struct mt7530_port { 669 bool enable; 670 u32 pm; 671 u16 pvid; 672 struct phylink_pcs *sgmii_pcs; 673 }; 674 675 /* Port 5 interface select definitions */ 676 enum p5_interface_select { 677 P5_DISABLED, 678 P5_INTF_SEL_PHY_P0, 679 P5_INTF_SEL_PHY_P4, 680 P5_INTF_SEL_GMAC5, 681 }; 682 683 struct mt7530_priv; 684 685 struct mt753x_pcs { 686 struct phylink_pcs pcs; 687 struct mt7530_priv *priv; 688 int port; 689 }; 690 691 /* struct mt753x_info - This is the main data structure for holding the specific 692 * part for each supported device 693 * @sw_setup: Holding the handler to a device initialization 694 * @phy_read_c22: Holding the way reading PHY port using C22 695 * @phy_write_c22: Holding the way writing PHY port using C22 696 * @phy_read_c45: Holding the way reading PHY port using C45 697 * @phy_write_c45: Holding the way writing PHY port using C45 698 * @phy_mode_supported: Check if the PHY type is being supported on a certain 699 * port 700 * @mac_port_validate: Holding the way to set addition validate type for a 701 * certan MAC port 702 * @mac_port_config: Holding the way setting up the PHY attribute to a 703 * certain MAC port 704 */ 705 struct mt753x_info { 706 enum mt753x_id id; 707 708 const struct phylink_pcs_ops *pcs_ops; 709 710 int (*sw_setup)(struct dsa_switch *ds); 711 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 712 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 713 u16 val); 714 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 715 int regnum); 716 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 717 int regnum, u16 val); 718 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 719 struct phylink_config *config); 720 void (*mac_port_validate)(struct dsa_switch *ds, int port, 721 phy_interface_t interface, 722 unsigned long *supported); 723 void (*mac_port_config)(struct dsa_switch *ds, int port, 724 unsigned int mode, 725 phy_interface_t interface); 726 }; 727 728 /* struct mt7530_priv - This is the main data structure for holding the state 729 * of the driver 730 * @dev: The device pointer 731 * @ds: The pointer to the dsa core structure 732 * @bus: The bus used for the device and built-in PHY 733 * @regmap: The regmap instance representing all switch registers 734 * @rstc: The pointer to reset control used by MCM 735 * @core_pwr: The power supplied into the core 736 * @io_pwr: The power supplied into the I/O 737 * @reset: The descriptor for GPIO line tied to its reset pin 738 * @mcm: Flag for distinguishing if standalone IC or module 739 * coupling 740 * @ports: Holding the state among ports 741 * @reg_mutex: The lock for protecting among process accessing 742 * registers 743 * @p5_intf_sel: Holding the current port 5 interface select 744 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch 745 * has got SGMII 746 * @irq: IRQ number of the switch 747 * @irq_domain: IRQ domain of the switch irq_chip 748 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN 749 * @create_sgmii: Pointer to function creating SGMII PCS instance(s) 750 * @active_cpu_ports: Holding the active CPU ports 751 */ 752 struct mt7530_priv { 753 struct device *dev; 754 struct dsa_switch *ds; 755 struct mii_bus *bus; 756 struct regmap *regmap; 757 struct reset_control *rstc; 758 struct regulator *core_pwr; 759 struct regulator *io_pwr; 760 struct gpio_desc *reset; 761 const struct mt753x_info *info; 762 unsigned int id; 763 bool mcm; 764 enum p5_interface_select p5_intf_sel; 765 bool p5_sgmii; 766 u8 mirror_rx; 767 u8 mirror_tx; 768 struct mt7530_port ports[MT7530_NUM_PORTS]; 769 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 770 /* protect among processes for registers access*/ 771 struct mutex reg_mutex; 772 int irq; 773 struct irq_domain *irq_domain; 774 u32 irq_enable; 775 int (*create_sgmii)(struct mt7530_priv *priv); 776 u8 active_cpu_ports; 777 }; 778 779 struct mt7530_hw_vlan_entry { 780 int port; 781 u8 old_members; 782 bool untagged; 783 }; 784 785 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 786 int port, bool untagged) 787 { 788 e->port = port; 789 e->untagged = untagged; 790 } 791 792 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 793 struct mt7530_hw_vlan_entry *); 794 795 struct mt7530_hw_stats { 796 const char *string; 797 u16 reg; 798 u8 sizeof_stat; 799 }; 800 801 struct mt7530_dummy_poll { 802 struct mt7530_priv *priv; 803 u32 reg; 804 }; 805 806 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 807 struct mt7530_priv *priv, u32 reg) 808 { 809 p->priv = priv; 810 p->reg = reg; 811 } 812 813 int mt7530_probe_common(struct mt7530_priv *priv); 814 void mt7530_remove_common(struct mt7530_priv *priv); 815 816 extern const struct dsa_switch_ops mt7530_switch_ops; 817 extern const struct mt753x_info mt753x_table[]; 818 819 #endif /* __MT7530_H */ 820