1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 9 select ARCH_HAS_CURRENT_STACK_POINTER 10 select ARCH_HAS_DEBUG_VIRTUAL if MMU 11 select ARCH_HAS_DMA_ALLOC if MMU 12 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 13 select ARCH_HAS_ELF_RANDOMIZE 14 select ARCH_HAS_FORTIFY_SOURCE 15 select ARCH_HAS_KEEPINITRD 16 select ARCH_HAS_KCOV 17 select ARCH_HAS_MEMBARRIER_SYNC_CORE 18 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 19 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 20 select ARCH_HAS_SETUP_DMA_OPS 21 select ARCH_HAS_SET_MEMORY 22 select ARCH_STACKWALK 23 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 24 select ARCH_HAS_STRICT_MODULE_RWX if MMU 25 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 26 select ARCH_HAS_SYNC_DMA_FOR_CPU 27 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 29 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_KEEP_MEMBLOCK 32 select ARCH_HAS_UBSAN_SANITIZE_ALL 33 select ARCH_MIGHT_HAVE_PC_PARPORT 34 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 35 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 36 select ARCH_SUPPORTS_ATOMIC_RMW 37 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 38 select ARCH_USE_BUILTIN_BSWAP 39 select ARCH_USE_CMPXCHG_LOCKREF 40 select ARCH_USE_MEMTEST 41 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 42 select ARCH_WANT_GENERAL_HUGETLB 43 select ARCH_WANT_IPC_PARSE_VERSION 44 select ARCH_WANT_LD_ORPHAN_WARN 45 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 46 select BUILDTIME_TABLE_SORT if MMU 47 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 48 select CLONE_BACKWARDS 49 select CPU_PM if SUSPEND || CPU_IDLE 50 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 51 select DMA_DECLARE_COHERENT 52 select DMA_GLOBAL_POOL if !MMU 53 select DMA_OPS 54 select DMA_NONCOHERENT_MMAP if MMU 55 select EDAC_SUPPORT 56 select EDAC_ATOMIC_SCRUB 57 select GENERIC_ALLOCATOR 58 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 59 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 60 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 61 select GENERIC_IRQ_IPI if SMP 62 select GENERIC_CPU_AUTOPROBE 63 select GENERIC_EARLY_IOREMAP 64 select GENERIC_IDLE_POLL_SETUP 65 select GENERIC_IRQ_MULTI_HANDLER 66 select GENERIC_IRQ_PROBE 67 select GENERIC_IRQ_SHOW 68 select GENERIC_IRQ_SHOW_LEVEL 69 select GENERIC_LIB_DEVMEM_IS_ALLOWED 70 select GENERIC_PCI_IOMAP 71 select GENERIC_SCHED_CLOCK 72 select GENERIC_SMP_IDLE_THREAD 73 select HARDIRQS_SW_RESEND 74 select HAS_IOPORT 75 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 76 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 77 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 78 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 79 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 80 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 81 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 82 select HAVE_ARCH_MMAP_RND_BITS if MMU 83 select HAVE_ARCH_PFN_VALID 84 select HAVE_ARCH_SECCOMP 85 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 86 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 87 select HAVE_ARCH_TRACEHOOK 88 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 89 select HAVE_ARM_SMCCC if CPU_V7 90 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 91 select HAVE_CONTEXT_TRACKING_USER 92 select HAVE_C_RECORDMCOUNT 93 select HAVE_BUILDTIME_MCOUNT_SORT 94 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 95 select HAVE_DMA_CONTIGUOUS if MMU 96 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 97 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 98 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 99 select HAVE_EXIT_THREAD 100 select HAVE_FAST_GUP if ARM_LPAE 101 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 102 select HAVE_FUNCTION_ERROR_INJECTION 103 select HAVE_FUNCTION_GRAPH_TRACER 104 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 105 select HAVE_GCC_PLUGINS 106 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 107 select HAVE_IRQ_TIME_ACCOUNTING 108 select HAVE_KERNEL_GZIP 109 select HAVE_KERNEL_LZ4 110 select HAVE_KERNEL_LZMA 111 select HAVE_KERNEL_LZO 112 select HAVE_KERNEL_XZ 113 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 114 select HAVE_KRETPROBES if HAVE_KPROBES 115 select HAVE_MOD_ARCH_SPECIFIC 116 select HAVE_NMI 117 select HAVE_OPTPROBES if !THUMB2_KERNEL 118 select HAVE_PCI if MMU 119 select HAVE_PERF_EVENTS 120 select HAVE_PERF_REGS 121 select HAVE_PERF_USER_STACK_DUMP 122 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 123 select HAVE_REGS_AND_STACK_ACCESS_API 124 select HAVE_RSEQ 125 select HAVE_STACKPROTECTOR 126 select HAVE_SYSCALL_TRACEPOINTS 127 select HAVE_UID16 128 select HAVE_VIRT_CPU_ACCOUNTING_GEN 129 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 130 select IRQ_FORCED_THREADING 131 select LOCK_MM_AND_FIND_VMA 132 select MODULES_USE_ELF_REL 133 select NEED_DMA_MAP_STATE 134 select OF_EARLY_FLATTREE if OF 135 select OLD_SIGACTION 136 select OLD_SIGSUSPEND3 137 select PCI_DOMAINS_GENERIC if PCI 138 select PCI_SYSCALL if PCI 139 select PERF_USE_VMALLOC 140 select RTC_LIB 141 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 142 select SYS_SUPPORTS_APM_EMULATION 143 select THREAD_INFO_IN_TASK 144 select TIMER_OF if OF 145 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 146 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 147 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 148 # Above selects are sorted alphabetically; please add new ones 149 # according to that. Thanks. 150 help 151 The ARM series is a line of low-power-consumption RISC chip designs 152 licensed by ARM Ltd and targeted at embedded applications and 153 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 154 manufactured, but legacy ARM-based PC hardware remains popular in 155 Europe. There is an ARM Linux project with a web page at 156 <http://www.arm.linux.org.uk/>. 157 158config ARM_HAS_GROUP_RELOCS 159 def_bool y 160 depends on !LD_IS_LLD || LLD_VERSION >= 140000 161 depends on !COMPILE_TEST 162 help 163 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 164 relocations, which have been around for a long time, but were not 165 supported in LLD until version 14. The combined range is -/+ 256 MiB, 166 which is usually sufficient, but not for allyesconfig, so we disable 167 this feature when doing compile testing. 168 169config ARM_DMA_USE_IOMMU 170 bool 171 select NEED_SG_DMA_LENGTH 172 173if ARM_DMA_USE_IOMMU 174 175config ARM_DMA_IOMMU_ALIGNMENT 176 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 177 range 4 9 178 default 8 179 help 180 DMA mapping framework by default aligns all buffers to the smallest 181 PAGE_SIZE order which is greater than or equal to the requested buffer 182 size. This works well for buffers up to a few hundreds kilobytes, but 183 for larger buffers it just a waste of address space. Drivers which has 184 relatively small addressing window (like 64Mib) might run out of 185 virtual space with just a few allocations. 186 187 With this parameter you can specify the maximum PAGE_SIZE order for 188 DMA IOMMU buffers. Larger buffers will be aligned only to this 189 specified order. The order is expressed as a power of two multiplied 190 by the PAGE_SIZE. 191 192endif 193 194config SYS_SUPPORTS_APM_EMULATION 195 bool 196 197config HAVE_TCM 198 bool 199 select GENERIC_ALLOCATOR 200 201config HAVE_PROC_CPU 202 bool 203 204config NO_IOPORT_MAP 205 bool 206 207config SBUS 208 bool 209 210config STACKTRACE_SUPPORT 211 bool 212 default y 213 214config LOCKDEP_SUPPORT 215 bool 216 default y 217 218config ARCH_HAS_ILOG2_U32 219 bool 220 221config ARCH_HAS_ILOG2_U64 222 bool 223 224config ARCH_HAS_BANDGAP 225 bool 226 227config FIX_EARLYCON_MEM 228 def_bool y if MMU 229 230config GENERIC_HWEIGHT 231 bool 232 default y 233 234config GENERIC_CALIBRATE_DELAY 235 bool 236 default y 237 238config ARCH_MAY_HAVE_PC_FDC 239 bool 240 241config ARCH_SUPPORTS_UPROBES 242 def_bool y 243 244config GENERIC_ISA_DMA 245 bool 246 247config FIQ 248 bool 249 250config ARCH_MTD_XIP 251 bool 252 253config ARM_PATCH_PHYS_VIRT 254 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 255 default y 256 depends on MMU 257 help 258 Patch phys-to-virt and virt-to-phys translation functions at 259 boot and module load time according to the position of the 260 kernel in system memory. 261 262 This can only be used with non-XIP MMU kernels where the base 263 of physical memory is at a 2 MiB boundary. 264 265 Only disable this option if you know that you do not require 266 this feature (eg, building a kernel for a single machine) and 267 you need to shrink the kernel to the minimal size. 268 269config NEED_MACH_IO_H 270 bool 271 help 272 Select this when mach/io.h is required to provide special 273 definitions for this platform. The need for mach/io.h should 274 be avoided when possible. 275 276config NEED_MACH_MEMORY_H 277 bool 278 help 279 Select this when mach/memory.h is required to provide special 280 definitions for this platform. The need for mach/memory.h should 281 be avoided when possible. 282 283config PHYS_OFFSET 284 hex "Physical address of main memory" if MMU 285 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 286 default DRAM_BASE if !MMU 287 default 0x00000000 if ARCH_FOOTBRIDGE 288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 289 default 0xa0000000 if ARCH_PXA 290 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 291 default 0 292 help 293 Please provide the physical address corresponding to the 294 location of main memory in your system. 295 296config GENERIC_BUG 297 def_bool y 298 depends on BUG 299 300config PGTABLE_LEVELS 301 int 302 default 3 if ARM_LPAE 303 default 2 304 305menu "System Type" 306 307config MMU 308 bool "MMU-based Paged Memory Management Support" 309 default y 310 help 311 Select if you want MMU-based virtualised addressing space 312 support by paged memory management. If unsure, say 'Y'. 313 314config ARM_SINGLE_ARMV7M 315 def_bool !MMU 316 select ARM_NVIC 317 select CPU_V7M 318 select NO_IOPORT_MAP 319 320config ARCH_MMAP_RND_BITS_MIN 321 default 8 322 323config ARCH_MMAP_RND_BITS_MAX 324 default 14 if PAGE_OFFSET=0x40000000 325 default 15 if PAGE_OFFSET=0x80000000 326 default 16 327 328config ARCH_MULTIPLATFORM 329 bool "Require kernel to be portable to multiple machines" if EXPERT 330 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 331 default y 332 help 333 In general, all Arm machines can be supported in a single 334 kernel image, covering either Armv4/v5 or Armv6/v7. 335 336 However, some configuration options require hardcoding machine 337 specific physical addresses or enable errata workarounds that may 338 break other machines. 339 340 Selecting N here allows using those options, including 341 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 342 343menu "Platform selection" 344 depends on MMU 345 346comment "CPU Core family selection" 347 348config ARCH_MULTI_V4 349 bool "ARMv4 based platforms (FA526, StrongARM)" 350 depends on !ARCH_MULTI_V6_V7 351 # https://github.com/llvm/llvm-project/issues/50764 352 depends on !LD_IS_LLD || LLD_VERSION >= 160000 353 select ARCH_MULTI_V4_V5 354 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 355 356config ARCH_MULTI_V4T 357 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 358 depends on !ARCH_MULTI_V6_V7 359 # https://github.com/llvm/llvm-project/issues/50764 360 depends on !LD_IS_LLD || LLD_VERSION >= 160000 361 select ARCH_MULTI_V4_V5 362 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 363 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 364 CPU_ARM925T || CPU_ARM940T) 365 366config ARCH_MULTI_V5 367 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 368 depends on !ARCH_MULTI_V6_V7 369 select ARCH_MULTI_V4_V5 370 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 371 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 372 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 373 374config ARCH_MULTI_V4_V5 375 bool 376 377config ARCH_MULTI_V6 378 bool "ARMv6 based platforms (ARM11)" 379 select ARCH_MULTI_V6_V7 380 select CPU_V6K 381 382config ARCH_MULTI_V7 383 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 384 default y 385 select ARCH_MULTI_V6_V7 386 select CPU_V7 387 select HAVE_SMP 388 389config ARCH_MULTI_V6_V7 390 bool 391 select MIGHT_HAVE_CACHE_L2X0 392 393config ARCH_MULTI_CPU_AUTO 394 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 395 select ARCH_MULTI_V5 396 397endmenu 398 399config ARCH_VIRT 400 bool "Dummy Virtual Machine" 401 depends on ARCH_MULTI_V7 402 select ARM_AMBA 403 select ARM_GIC 404 select ARM_GIC_V2M if PCI 405 select ARM_GIC_V3 406 select ARM_GIC_V3_ITS if PCI 407 select ARM_PSCI 408 select HAVE_ARM_ARCH_TIMER 409 410config ARCH_AIROHA 411 bool "Airoha SoC Support" 412 depends on ARCH_MULTI_V7 413 select ARM_AMBA 414 select ARM_GIC 415 select ARM_GIC_V3 416 select ARM_PSCI 417 select HAVE_ARM_ARCH_TIMER 418 help 419 Support for Airoha EN7523 SoCs 420 421# 422# This is sorted alphabetically by mach-* pathname. However, plat-* 423# Kconfigs may be included either alphabetically (according to the 424# plat- suffix) or along side the corresponding mach-* source. 425# 426source "arch/arm/mach-actions/Kconfig" 427 428source "arch/arm/mach-alpine/Kconfig" 429 430source "arch/arm/mach-artpec/Kconfig" 431 432source "arch/arm/mach-asm9260/Kconfig" 433 434source "arch/arm/mach-aspeed/Kconfig" 435 436source "arch/arm/mach-at91/Kconfig" 437 438source "arch/arm/mach-axxia/Kconfig" 439 440source "arch/arm/mach-bcm/Kconfig" 441 442source "arch/arm/mach-berlin/Kconfig" 443 444source "arch/arm/mach-clps711x/Kconfig" 445 446source "arch/arm/mach-davinci/Kconfig" 447 448source "arch/arm/mach-digicolor/Kconfig" 449 450source "arch/arm/mach-dove/Kconfig" 451 452source "arch/arm/mach-ep93xx/Kconfig" 453 454source "arch/arm/mach-exynos/Kconfig" 455 456source "arch/arm/mach-footbridge/Kconfig" 457 458source "arch/arm/mach-gemini/Kconfig" 459 460source "arch/arm/mach-highbank/Kconfig" 461 462source "arch/arm/mach-hisi/Kconfig" 463 464source "arch/arm/mach-hpe/Kconfig" 465 466source "arch/arm/mach-imx/Kconfig" 467 468source "arch/arm/mach-ixp4xx/Kconfig" 469 470source "arch/arm/mach-keystone/Kconfig" 471 472source "arch/arm/mach-lpc32xx/Kconfig" 473 474source "arch/arm/mach-mediatek/Kconfig" 475 476source "arch/arm/mach-meson/Kconfig" 477 478source "arch/arm/mach-milbeaut/Kconfig" 479 480source "arch/arm/mach-mmp/Kconfig" 481 482source "arch/arm/mach-moxart/Kconfig" 483 484source "arch/arm/mach-mstar/Kconfig" 485 486source "arch/arm/mach-mv78xx0/Kconfig" 487 488source "arch/arm/mach-mvebu/Kconfig" 489 490source "arch/arm/mach-mxs/Kconfig" 491 492source "arch/arm/mach-nomadik/Kconfig" 493 494source "arch/arm/mach-npcm/Kconfig" 495 496source "arch/arm/mach-nspire/Kconfig" 497 498source "arch/arm/mach-omap1/Kconfig" 499 500source "arch/arm/mach-omap2/Kconfig" 501 502source "arch/arm/mach-orion5x/Kconfig" 503 504source "arch/arm/mach-pxa/Kconfig" 505 506source "arch/arm/mach-qcom/Kconfig" 507 508source "arch/arm/mach-rda/Kconfig" 509 510source "arch/arm/mach-realtek/Kconfig" 511 512source "arch/arm/mach-rpc/Kconfig" 513 514source "arch/arm/mach-rockchip/Kconfig" 515 516source "arch/arm/mach-s3c/Kconfig" 517 518source "arch/arm/mach-s5pv210/Kconfig" 519 520source "arch/arm/mach-sa1100/Kconfig" 521 522source "arch/arm/mach-shmobile/Kconfig" 523 524source "arch/arm/mach-socfpga/Kconfig" 525 526source "arch/arm/mach-spear/Kconfig" 527 528source "arch/arm/mach-sti/Kconfig" 529 530source "arch/arm/mach-stm32/Kconfig" 531 532source "arch/arm/mach-sunplus/Kconfig" 533 534source "arch/arm/mach-sunxi/Kconfig" 535 536source "arch/arm/mach-tegra/Kconfig" 537 538source "arch/arm/mach-uniphier/Kconfig" 539 540source "arch/arm/mach-ux500/Kconfig" 541 542source "arch/arm/mach-versatile/Kconfig" 543 544source "arch/arm/mach-vt8500/Kconfig" 545 546source "arch/arm/mach-zynq/Kconfig" 547 548# ARMv7-M architecture 549config ARCH_LPC18XX 550 bool "NXP LPC18xx/LPC43xx" 551 depends on ARM_SINGLE_ARMV7M 552 select ARCH_HAS_RESET_CONTROLLER 553 select ARM_AMBA 554 select CLKSRC_LPC32XX 555 select PINCTRL 556 help 557 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 558 high performance microcontrollers. 559 560config ARCH_MPS2 561 bool "ARM MPS2 platform" 562 depends on ARM_SINGLE_ARMV7M 563 select ARM_AMBA 564 select CLKSRC_MPS2 565 help 566 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 567 with a range of available cores like Cortex-M3/M4/M7. 568 569 Please, note that depends which Application Note is used memory map 570 for the platform may vary, so adjustment of RAM base might be needed. 571 572# Definitions to make life easier 573config ARCH_ACORN 574 bool 575 576config PLAT_ORION 577 bool 578 select CLKSRC_MMIO 579 select GENERIC_IRQ_CHIP 580 select IRQ_DOMAIN 581 582config PLAT_ORION_LEGACY 583 bool 584 select PLAT_ORION 585 586config PLAT_VERSATILE 587 bool 588 589source "arch/arm/mm/Kconfig" 590 591config IWMMXT 592 bool "Enable iWMMXt support" 593 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 594 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 595 help 596 Enable support for iWMMXt context switching at run time if 597 running on a CPU that supports it. 598 599if !MMU 600source "arch/arm/Kconfig-nommu" 601endif 602 603config PJ4B_ERRATA_4742 604 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 605 depends on CPU_PJ4B && MACH_ARMADA_370 606 default y 607 help 608 When coming out of either a Wait for Interrupt (WFI) or a Wait for 609 Event (WFE) IDLE states, a specific timing sensitivity exists between 610 the retiring WFI/WFE instructions and the newly issued subsequent 611 instructions. This sensitivity can result in a CPU hang scenario. 612 Workaround: 613 The software must insert either a Data Synchronization Barrier (DSB) 614 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 615 instruction 616 617config ARM_ERRATA_326103 618 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 619 depends on CPU_V6 620 help 621 Executing a SWP instruction to read-only memory does not set bit 11 622 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 623 treat the access as a read, preventing a COW from occurring and 624 causing the faulting task to livelock. 625 626config ARM_ERRATA_411920 627 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 628 depends on CPU_V6 || CPU_V6K 629 help 630 Invalidation of the Instruction Cache operation can 631 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 632 It does not affect the MPCore. This option enables the ARM Ltd. 633 recommended workaround. 634 635config ARM_ERRATA_430973 636 bool "ARM errata: Stale prediction on replaced interworking branch" 637 depends on CPU_V7 638 help 639 This option enables the workaround for the 430973 Cortex-A8 640 r1p* erratum. If a code sequence containing an ARM/Thumb 641 interworking branch is replaced with another code sequence at the 642 same virtual address, whether due to self-modifying code or virtual 643 to physical address re-mapping, Cortex-A8 does not recover from the 644 stale interworking branch prediction. This results in Cortex-A8 645 executing the new code sequence in the incorrect ARM or Thumb state. 646 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 647 and also flushes the branch target cache at every context switch. 648 Note that setting specific bits in the ACTLR register may not be 649 available in non-secure mode. 650 651config ARM_ERRATA_458693 652 bool "ARM errata: Processor deadlock when a false hazard is created" 653 depends on CPU_V7 654 depends on !ARCH_MULTIPLATFORM 655 help 656 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 657 erratum. For very specific sequences of memory operations, it is 658 possible for a hazard condition intended for a cache line to instead 659 be incorrectly associated with a different cache line. This false 660 hazard might then cause a processor deadlock. The workaround enables 661 the L1 caching of the NEON accesses and disables the PLD instruction 662 in the ACTLR register. Note that setting specific bits in the ACTLR 663 register may not be available in non-secure mode and thus is not 664 available on a multiplatform kernel. This should be applied by the 665 bootloader instead. 666 667config ARM_ERRATA_460075 668 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 669 depends on CPU_V7 670 depends on !ARCH_MULTIPLATFORM 671 help 672 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 673 erratum. Any asynchronous access to the L2 cache may encounter a 674 situation in which recent store transactions to the L2 cache are lost 675 and overwritten with stale memory contents from external memory. The 676 workaround disables the write-allocate mode for the L2 cache via the 677 ACTLR register. Note that setting specific bits in the ACTLR register 678 may not be available in non-secure mode and thus is not available on 679 a multiplatform kernel. This should be applied by the bootloader 680 instead. 681 682config ARM_ERRATA_742230 683 bool "ARM errata: DMB operation may be faulty" 684 depends on CPU_V7 && SMP 685 depends on !ARCH_MULTIPLATFORM 686 help 687 This option enables the workaround for the 742230 Cortex-A9 688 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 689 between two write operations may not ensure the correct visibility 690 ordering of the two writes. This workaround sets a specific bit in 691 the diagnostic register of the Cortex-A9 which causes the DMB 692 instruction to behave as a DSB, ensuring the correct behaviour of 693 the two writes. Note that setting specific bits in the diagnostics 694 register may not be available in non-secure mode and thus is not 695 available on a multiplatform kernel. This should be applied by the 696 bootloader instead. 697 698config ARM_ERRATA_742231 699 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 700 depends on CPU_V7 && SMP 701 depends on !ARCH_MULTIPLATFORM 702 help 703 This option enables the workaround for the 742231 Cortex-A9 704 (r2p0..r2p2) erratum. Under certain conditions, specific to the 705 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 706 accessing some data located in the same cache line, may get corrupted 707 data due to bad handling of the address hazard when the line gets 708 replaced from one of the CPUs at the same time as another CPU is 709 accessing it. This workaround sets specific bits in the diagnostic 710 register of the Cortex-A9 which reduces the linefill issuing 711 capabilities of the processor. Note that setting specific bits in the 712 diagnostics register may not be available in non-secure mode and thus 713 is not available on a multiplatform kernel. This should be applied by 714 the bootloader instead. 715 716config ARM_ERRATA_643719 717 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 718 depends on CPU_V7 && SMP 719 default y 720 help 721 This option enables the workaround for the 643719 Cortex-A9 (prior to 722 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 723 register returns zero when it should return one. The workaround 724 corrects this value, ensuring cache maintenance operations which use 725 it behave as intended and avoiding data corruption. 726 727config ARM_ERRATA_720789 728 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 729 depends on CPU_V7 730 help 731 This option enables the workaround for the 720789 Cortex-A9 (prior to 732 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 733 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 734 As a consequence of this erratum, some TLB entries which should be 735 invalidated are not, resulting in an incoherency in the system page 736 tables. The workaround changes the TLB flushing routines to invalidate 737 entries regardless of the ASID. 738 739config ARM_ERRATA_743622 740 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 741 depends on CPU_V7 742 depends on !ARCH_MULTIPLATFORM 743 help 744 This option enables the workaround for the 743622 Cortex-A9 745 (r2p*) erratum. Under very rare conditions, a faulty 746 optimisation in the Cortex-A9 Store Buffer may lead to data 747 corruption. This workaround sets a specific bit in the diagnostic 748 register of the Cortex-A9 which disables the Store Buffer 749 optimisation, preventing the defect from occurring. This has no 750 visible impact on the overall performance or power consumption of the 751 processor. Note that setting specific bits in the diagnostics register 752 may not be available in non-secure mode and thus is not available on a 753 multiplatform kernel. This should be applied by the bootloader instead. 754 755config ARM_ERRATA_751472 756 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 757 depends on CPU_V7 758 depends on !ARCH_MULTIPLATFORM 759 help 760 This option enables the workaround for the 751472 Cortex-A9 (prior 761 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 762 completion of a following broadcasted operation if the second 763 operation is received by a CPU before the ICIALLUIS has completed, 764 potentially leading to corrupted entries in the cache or TLB. 765 Note that setting specific bits in the diagnostics register may 766 not be available in non-secure mode and thus is not available on 767 a multiplatform kernel. This should be applied by the bootloader 768 instead. 769 770config ARM_ERRATA_754322 771 bool "ARM errata: possible faulty MMU translations following an ASID switch" 772 depends on CPU_V7 773 help 774 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 775 r3p*) erratum. A speculative memory access may cause a page table walk 776 which starts prior to an ASID switch but completes afterwards. This 777 can populate the micro-TLB with a stale entry which may be hit with 778 the new ASID. This workaround places two dsb instructions in the mm 779 switching code so that no page table walks can cross the ASID switch. 780 781config ARM_ERRATA_754327 782 bool "ARM errata: no automatic Store Buffer drain" 783 depends on CPU_V7 && SMP 784 help 785 This option enables the workaround for the 754327 Cortex-A9 (prior to 786 r2p0) erratum. The Store Buffer does not have any automatic draining 787 mechanism and therefore a livelock may occur if an external agent 788 continuously polls a memory location waiting to observe an update. 789 This workaround defines cpu_relax() as smp_mb(), preventing correctly 790 written polling loops from denying visibility of updates to memory. 791 792config ARM_ERRATA_364296 793 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 794 depends on CPU_V6 795 help 796 This options enables the workaround for the 364296 ARM1136 797 r0p2 erratum (possible cache data corruption with 798 hit-under-miss enabled). It sets the undocumented bit 31 in 799 the auxiliary control register and the FI bit in the control 800 register, thus disabling hit-under-miss without putting the 801 processor into full low interrupt latency mode. ARM11MPCore 802 is not affected. 803 804config ARM_ERRATA_764369 805 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 806 depends on CPU_V7 && SMP 807 help 808 This option enables the workaround for erratum 764369 809 affecting Cortex-A9 MPCore with two or more processors (all 810 current revisions). Under certain timing circumstances, a data 811 cache line maintenance operation by MVA targeting an Inner 812 Shareable memory region may fail to proceed up to either the 813 Point of Coherency or to the Point of Unification of the 814 system. This workaround adds a DSB instruction before the 815 relevant cache maintenance functions and sets a specific bit 816 in the diagnostic control register of the SCU. 817 818config ARM_ERRATA_764319 819 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 820 depends on CPU_V7 821 help 822 This option enables the workaround for the 764319 Cortex A-9 erratum. 823 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 824 unexpected Undefined Instruction exception when the DBGSWENABLE 825 external pin is set to 0, even when the CP14 accesses are performed 826 from a privileged mode. This work around catches the exception in a 827 way the kernel does not stop execution. 828 829config ARM_ERRATA_775420 830 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 831 depends on CPU_V7 832 help 833 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 834 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 835 operation aborts with MMU exception, it might cause the processor 836 to deadlock. This workaround puts DSB before executing ISB if 837 an abort may occur on cache maintenance. 838 839config ARM_ERRATA_798181 840 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 841 depends on CPU_V7 && SMP 842 help 843 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 844 adequately shooting down all use of the old entries. This 845 option enables the Linux kernel workaround for this erratum 846 which sends an IPI to the CPUs that are running the same ASID 847 as the one being invalidated. 848 849config ARM_ERRATA_773022 850 bool "ARM errata: incorrect instructions may be executed from loop buffer" 851 depends on CPU_V7 852 help 853 This option enables the workaround for the 773022 Cortex-A15 854 (up to r0p4) erratum. In certain rare sequences of code, the 855 loop buffer may deliver incorrect instructions. This 856 workaround disables the loop buffer to avoid the erratum. 857 858config ARM_ERRATA_818325_852422 859 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 860 depends on CPU_V7 861 help 862 This option enables the workaround for: 863 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 864 instruction might deadlock. Fixed in r0p1. 865 - Cortex-A12 852422: Execution of a sequence of instructions might 866 lead to either a data corruption or a CPU deadlock. Not fixed in 867 any Cortex-A12 cores yet. 868 This workaround for all both errata involves setting bit[12] of the 869 Feature Register. This bit disables an optimisation applied to a 870 sequence of 2 instructions that use opposing condition codes. 871 872config ARM_ERRATA_821420 873 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 874 depends on CPU_V7 875 help 876 This option enables the workaround for the 821420 Cortex-A12 877 (all revs) erratum. In very rare timing conditions, a sequence 878 of VMOV to Core registers instructions, for which the second 879 one is in the shadow of a branch or abort, can lead to a 880 deadlock when the VMOV instructions are issued out-of-order. 881 882config ARM_ERRATA_825619 883 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 884 depends on CPU_V7 885 help 886 This option enables the workaround for the 825619 Cortex-A12 887 (all revs) erratum. Within rare timing constraints, executing a 888 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 889 and Device/Strongly-Ordered loads and stores might cause deadlock 890 891config ARM_ERRATA_857271 892 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 893 depends on CPU_V7 894 help 895 This option enables the workaround for the 857271 Cortex-A12 896 (all revs) erratum. Under very rare timing conditions, the CPU might 897 hang. The workaround is expected to have a < 1% performance impact. 898 899config ARM_ERRATA_852421 900 bool "ARM errata: A17: DMB ST might fail to create order between stores" 901 depends on CPU_V7 902 help 903 This option enables the workaround for the 852421 Cortex-A17 904 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 905 execution of a DMB ST instruction might fail to properly order 906 stores from GroupA and stores from GroupB. 907 908config ARM_ERRATA_852423 909 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 910 depends on CPU_V7 911 help 912 This option enables the workaround for: 913 - Cortex-A17 852423: Execution of a sequence of instructions might 914 lead to either a data corruption or a CPU deadlock. Not fixed in 915 any Cortex-A17 cores yet. 916 This is identical to Cortex-A12 erratum 852422. It is a separate 917 config option from the A12 erratum due to the way errata are checked 918 for and handled. 919 920config ARM_ERRATA_857272 921 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 922 depends on CPU_V7 923 help 924 This option enables the workaround for the 857272 Cortex-A17 erratum. 925 This erratum is not known to be fixed in any A17 revision. 926 This is identical to Cortex-A12 erratum 857271. It is a separate 927 config option from the A12 erratum due to the way errata are checked 928 for and handled. 929 930endmenu 931 932source "arch/arm/common/Kconfig" 933 934menu "Bus support" 935 936config ISA 937 bool 938 help 939 Find out whether you have ISA slots on your motherboard. ISA is the 940 name of a bus system, i.e. the way the CPU talks to the other stuff 941 inside your box. Other bus systems are PCI, EISA, MicroChannel 942 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 943 newer boards don't support it. If you have ISA, say Y, otherwise N. 944 945# Select ISA DMA interface 946config ISA_DMA_API 947 bool 948 949config ARM_ERRATA_814220 950 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 951 depends on CPU_V7 952 help 953 The v7 ARM states that all cache and branch predictor maintenance 954 operations that do not specify an address execute, relative to 955 each other, in program order. 956 However, because of this erratum, an L2 set/way cache maintenance 957 operation can overtake an L1 set/way cache maintenance operation. 958 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 959 r0p4, r0p5. 960 961endmenu 962 963menu "Kernel Features" 964 965config HAVE_SMP 966 bool 967 help 968 This option should be selected by machines which have an SMP- 969 capable CPU. 970 971 The only effect of this option is to make the SMP-related 972 options available to the user for configuration. 973 974config SMP 975 bool "Symmetric Multi-Processing" 976 depends on CPU_V6K || CPU_V7 977 depends on HAVE_SMP 978 depends on MMU || ARM_MPU 979 select IRQ_WORK 980 help 981 This enables support for systems with more than one CPU. If you have 982 a system with only one CPU, say N. If you have a system with more 983 than one CPU, say Y. 984 985 If you say N here, the kernel will run on uni- and multiprocessor 986 machines, but will use only one CPU of a multiprocessor machine. If 987 you say Y here, the kernel will run on many, but not all, 988 uniprocessor machines. On a uniprocessor machine, the kernel 989 will run faster if you say N here. 990 991 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 992 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 993 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 994 995 If you don't know what to do here, say N. 996 997config SMP_ON_UP 998 bool "Allow booting SMP kernel on uniprocessor systems" 999 depends on SMP && MMU 1000 default y 1001 help 1002 SMP kernels contain instructions which fail on non-SMP processors. 1003 Enabling this option allows the kernel to modify itself to make 1004 these instructions safe. Disabling it allows about 1K of space 1005 savings. 1006 1007 If you don't know what to do here, say Y. 1008 1009 1010config CURRENT_POINTER_IN_TPIDRURO 1011 def_bool y 1012 depends on CPU_32v6K && !CPU_V6 1013 1014config IRQSTACKS 1015 def_bool y 1016 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1017 select HAVE_SOFTIRQ_ON_OWN_STACK 1018 1019config ARM_CPU_TOPOLOGY 1020 bool "Support cpu topology definition" 1021 depends on SMP && CPU_V7 1022 default y 1023 help 1024 Support ARM cpu topology definition. The MPIDR register defines 1025 affinity between processors which is then used to describe the cpu 1026 topology of an ARM System. 1027 1028config SCHED_MC 1029 bool "Multi-core scheduler support" 1030 depends on ARM_CPU_TOPOLOGY 1031 help 1032 Multi-core scheduler support improves the CPU scheduler's decision 1033 making when dealing with multi-core CPU chips at a cost of slightly 1034 increased overhead in some places. If unsure say N here. 1035 1036config SCHED_SMT 1037 bool "SMT scheduler support" 1038 depends on ARM_CPU_TOPOLOGY 1039 help 1040 Improves the CPU scheduler's decision making when dealing with 1041 MultiThreading at a cost of slightly increased overhead in some 1042 places. If unsure say N here. 1043 1044config HAVE_ARM_SCU 1045 bool 1046 help 1047 This option enables support for the ARM snoop control unit 1048 1049config HAVE_ARM_ARCH_TIMER 1050 bool "Architected timer support" 1051 depends on CPU_V7 1052 select ARM_ARCH_TIMER 1053 help 1054 This option enables support for the ARM architected timer 1055 1056config HAVE_ARM_TWD 1057 bool 1058 help 1059 This options enables support for the ARM timer and watchdog unit 1060 1061config MCPM 1062 bool "Multi-Cluster Power Management" 1063 depends on CPU_V7 && SMP 1064 help 1065 This option provides the common power management infrastructure 1066 for (multi-)cluster based systems, such as big.LITTLE based 1067 systems. 1068 1069config MCPM_QUAD_CLUSTER 1070 bool 1071 depends on MCPM 1072 help 1073 To avoid wasting resources unnecessarily, MCPM only supports up 1074 to 2 clusters by default. 1075 Platforms with 3 or 4 clusters that use MCPM must select this 1076 option to allow the additional clusters to be managed. 1077 1078config BIG_LITTLE 1079 bool "big.LITTLE support (Experimental)" 1080 depends on CPU_V7 && SMP 1081 select MCPM 1082 help 1083 This option enables support selections for the big.LITTLE 1084 system architecture. 1085 1086config BL_SWITCHER 1087 bool "big.LITTLE switcher support" 1088 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1089 select CPU_PM 1090 help 1091 The big.LITTLE "switcher" provides the core functionality to 1092 transparently handle transition between a cluster of A15's 1093 and a cluster of A7's in a big.LITTLE system. 1094 1095config BL_SWITCHER_DUMMY_IF 1096 tristate "Simple big.LITTLE switcher user interface" 1097 depends on BL_SWITCHER && DEBUG_KERNEL 1098 help 1099 This is a simple and dummy char dev interface to control 1100 the big.LITTLE switcher core code. It is meant for 1101 debugging purposes only. 1102 1103choice 1104 prompt "Memory split" 1105 depends on MMU 1106 default VMSPLIT_3G 1107 help 1108 Select the desired split between kernel and user memory. 1109 1110 If you are not absolutely sure what you are doing, leave this 1111 option alone! 1112 1113 config VMSPLIT_3G 1114 bool "3G/1G user/kernel split" 1115 config VMSPLIT_3G_OPT 1116 depends on !ARM_LPAE 1117 bool "3G/1G user/kernel split (for full 1G low memory)" 1118 config VMSPLIT_2G 1119 bool "2G/2G user/kernel split" 1120 config VMSPLIT_1G 1121 bool "1G/3G user/kernel split" 1122endchoice 1123 1124config PAGE_OFFSET 1125 hex 1126 default PHYS_OFFSET if !MMU 1127 default 0x40000000 if VMSPLIT_1G 1128 default 0x80000000 if VMSPLIT_2G 1129 default 0xB0000000 if VMSPLIT_3G_OPT 1130 default 0xC0000000 1131 1132config KASAN_SHADOW_OFFSET 1133 hex 1134 depends on KASAN 1135 default 0x1f000000 if PAGE_OFFSET=0x40000000 1136 default 0x5f000000 if PAGE_OFFSET=0x80000000 1137 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1138 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1139 default 0xffffffff 1140 1141config NR_CPUS 1142 int "Maximum number of CPUs (2-32)" 1143 range 2 16 if DEBUG_KMAP_LOCAL 1144 range 2 32 if !DEBUG_KMAP_LOCAL 1145 depends on SMP 1146 default "4" 1147 help 1148 The maximum number of CPUs that the kernel can support. 1149 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1150 debugging is enabled, which uses half of the per-CPU fixmap 1151 slots as guard regions. 1152 1153config HOTPLUG_CPU 1154 bool "Support for hot-pluggable CPUs" 1155 depends on SMP 1156 select GENERIC_IRQ_MIGRATION 1157 help 1158 Say Y here to experiment with turning CPUs off and on. CPUs 1159 can be controlled through /sys/devices/system/cpu. 1160 1161config ARM_PSCI 1162 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1163 depends on HAVE_ARM_SMCCC 1164 select ARM_PSCI_FW 1165 help 1166 Say Y here if you want Linux to communicate with system firmware 1167 implementing the PSCI specification for CPU-centric power 1168 management operations described in ARM document number ARM DEN 1169 0022A ("Power State Coordination Interface System Software on 1170 ARM processors"). 1171 1172config HZ_FIXED 1173 int 1174 default 128 if SOC_AT91RM9200 1175 default 0 1176 1177choice 1178 depends on HZ_FIXED = 0 1179 prompt "Timer frequency" 1180 1181config HZ_100 1182 bool "100 Hz" 1183 1184config HZ_200 1185 bool "200 Hz" 1186 1187config HZ_250 1188 bool "250 Hz" 1189 1190config HZ_300 1191 bool "300 Hz" 1192 1193config HZ_500 1194 bool "500 Hz" 1195 1196config HZ_1000 1197 bool "1000 Hz" 1198 1199endchoice 1200 1201config HZ 1202 int 1203 default HZ_FIXED if HZ_FIXED != 0 1204 default 100 if HZ_100 1205 default 200 if HZ_200 1206 default 250 if HZ_250 1207 default 300 if HZ_300 1208 default 500 if HZ_500 1209 default 1000 1210 1211config SCHED_HRTICK 1212 def_bool HIGH_RES_TIMERS 1213 1214config THUMB2_KERNEL 1215 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1216 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1217 default y if CPU_THUMBONLY 1218 select ARM_UNWIND 1219 help 1220 By enabling this option, the kernel will be compiled in 1221 Thumb-2 mode. 1222 1223 If unsure, say N. 1224 1225config ARM_PATCH_IDIV 1226 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1227 depends on CPU_32v7 1228 default y 1229 help 1230 The ARM compiler inserts calls to __aeabi_idiv() and 1231 __aeabi_uidiv() when it needs to perform division on signed 1232 and unsigned integers. Some v7 CPUs have support for the sdiv 1233 and udiv instructions that can be used to implement those 1234 functions. 1235 1236 Enabling this option allows the kernel to modify itself to 1237 replace the first two instructions of these library functions 1238 with the sdiv or udiv plus "bx lr" instructions when the CPU 1239 it is running on supports them. Typically this will be faster 1240 and less power intensive than running the original library 1241 code to do integer division. 1242 1243config AEABI 1244 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1245 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1246 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1247 help 1248 This option allows for the kernel to be compiled using the latest 1249 ARM ABI (aka EABI). This is only useful if you are using a user 1250 space environment that is also compiled with EABI. 1251 1252 Since there are major incompatibilities between the legacy ABI and 1253 EABI, especially with regard to structure member alignment, this 1254 option also changes the kernel syscall calling convention to 1255 disambiguate both ABIs and allow for backward compatibility support 1256 (selected with CONFIG_OABI_COMPAT). 1257 1258 To use this you need GCC version 4.0.0 or later. 1259 1260config OABI_COMPAT 1261 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1262 depends on AEABI && !THUMB2_KERNEL 1263 help 1264 This option preserves the old syscall interface along with the 1265 new (ARM EABI) one. It also provides a compatibility layer to 1266 intercept syscalls that have structure arguments which layout 1267 in memory differs between the legacy ABI and the new ARM EABI 1268 (only for non "thumb" binaries). This option adds a tiny 1269 overhead to all syscalls and produces a slightly larger kernel. 1270 1271 The seccomp filter system will not be available when this is 1272 selected, since there is no way yet to sensibly distinguish 1273 between calling conventions during filtering. 1274 1275 If you know you'll be using only pure EABI user space then you 1276 can say N here. If this option is not selected and you attempt 1277 to execute a legacy ABI binary then the result will be 1278 UNPREDICTABLE (in fact it can be predicted that it won't work 1279 at all). If in doubt say N. 1280 1281config ARCH_SELECT_MEMORY_MODEL 1282 def_bool y 1283 1284config ARCH_FLATMEM_ENABLE 1285 def_bool !(ARCH_RPC || ARCH_SA1100) 1286 1287config ARCH_SPARSEMEM_ENABLE 1288 def_bool !ARCH_FOOTBRIDGE 1289 select SPARSEMEM_STATIC if SPARSEMEM 1290 1291config HIGHMEM 1292 bool "High Memory Support" 1293 depends on MMU 1294 select KMAP_LOCAL 1295 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1296 help 1297 The address space of ARM processors is only 4 Gigabytes large 1298 and it has to accommodate user address space, kernel address 1299 space as well as some memory mapped IO. That means that, if you 1300 have a large amount of physical memory and/or IO, not all of the 1301 memory can be "permanently mapped" by the kernel. The physical 1302 memory that is not permanently mapped is called "high memory". 1303 1304 Depending on the selected kernel/user memory split, minimum 1305 vmalloc space and actual amount of RAM, you may not need this 1306 option which should result in a slightly faster kernel. 1307 1308 If unsure, say n. 1309 1310config HIGHPTE 1311 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1312 depends on HIGHMEM 1313 default y 1314 help 1315 The VM uses one page of physical memory for each page table. 1316 For systems with a lot of processes, this can use a lot of 1317 precious low memory, eventually leading to low memory being 1318 consumed by page tables. Setting this option will allow 1319 user-space 2nd level page tables to reside in high memory. 1320 1321config CPU_SW_DOMAIN_PAN 1322 bool "Enable use of CPU domains to implement privileged no-access" 1323 depends on MMU && !ARM_LPAE 1324 default y 1325 help 1326 Increase kernel security by ensuring that normal kernel accesses 1327 are unable to access userspace addresses. This can help prevent 1328 use-after-free bugs becoming an exploitable privilege escalation 1329 by ensuring that magic values (such as LIST_POISON) will always 1330 fault when dereferenced. 1331 1332 CPUs with low-vector mappings use a best-efforts implementation. 1333 Their lower 1MB needs to remain accessible for the vectors, but 1334 the remainder of userspace will become appropriately inaccessible. 1335 1336config HW_PERF_EVENTS 1337 def_bool y 1338 depends on ARM_PMU 1339 1340config ARM_MODULE_PLTS 1341 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1342 depends on MODULES 1343 select KASAN_VMALLOC if KASAN 1344 default y 1345 help 1346 Allocate PLTs when loading modules so that jumps and calls whose 1347 targets are too far away for their relative offsets to be encoded 1348 in the instructions themselves can be bounced via veneers in the 1349 module's PLT. This allows modules to be allocated in the generic 1350 vmalloc area after the dedicated module memory area has been 1351 exhausted. The modules will use slightly more memory, but after 1352 rounding up to page size, the actual memory footprint is usually 1353 the same. 1354 1355 Disabling this is usually safe for small single-platform 1356 configurations. If unsure, say y. 1357 1358config ARCH_FORCE_MAX_ORDER 1359 int "Order of maximal physically contiguous allocations" 1360 default "11" if SOC_AM33XX 1361 default "8" if SA1111 1362 default "10" 1363 help 1364 The kernel page allocator limits the size of maximal physically 1365 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1366 defines the maximal power of two of number of pages that can be 1367 allocated as a single contiguous block. This option allows 1368 overriding the default setting when ability to allocate very 1369 large blocks of physically contiguous memory is required. 1370 1371 Don't change if unsure. 1372 1373config ALIGNMENT_TRAP 1374 def_bool CPU_CP15_MMU 1375 select HAVE_PROC_CPU if PROC_FS 1376 help 1377 ARM processors cannot fetch/store information which is not 1378 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1379 address divisible by 4. On 32-bit ARM processors, these non-aligned 1380 fetch/store instructions will be emulated in software if you say 1381 here, which has a severe performance impact. This is necessary for 1382 correct operation of some network protocols. With an IP-only 1383 configuration it is safe to say N, otherwise say Y. 1384 1385config UACCESS_WITH_MEMCPY 1386 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1387 depends on MMU 1388 default y if CPU_FEROCEON 1389 help 1390 Implement faster copy_to_user and clear_user methods for CPU 1391 cores where a 8-word STM instruction give significantly higher 1392 memory write throughput than a sequence of individual 32bit stores. 1393 1394 A possible side effect is a slight increase in scheduling latency 1395 between threads sharing the same address space if they invoke 1396 such copy operations with large buffers. 1397 1398 However, if the CPU data cache is using a write-allocate mode, 1399 this option is unlikely to provide any performance gain. 1400 1401config PARAVIRT 1402 bool "Enable paravirtualization code" 1403 help 1404 This changes the kernel so it can modify itself when it is run 1405 under a hypervisor, potentially improving performance significantly 1406 over full virtualization. 1407 1408config PARAVIRT_TIME_ACCOUNTING 1409 bool "Paravirtual steal time accounting" 1410 select PARAVIRT 1411 help 1412 Select this option to enable fine granularity task steal time 1413 accounting. Time spent executing other tasks in parallel with 1414 the current vCPU is discounted from the vCPU power. To account for 1415 that, there can be a small performance impact. 1416 1417 If in doubt, say N here. 1418 1419config XEN_DOM0 1420 def_bool y 1421 depends on XEN 1422 1423config XEN 1424 bool "Xen guest support on ARM" 1425 depends on ARM && AEABI && OF 1426 depends on CPU_V7 && !CPU_V6 1427 depends on !GENERIC_ATOMIC64 1428 depends on MMU 1429 select ARCH_DMA_ADDR_T_64BIT 1430 select ARM_PSCI 1431 select SWIOTLB 1432 select SWIOTLB_XEN 1433 select PARAVIRT 1434 help 1435 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1436 1437config CC_HAVE_STACKPROTECTOR_TLS 1438 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1439 1440config STACKPROTECTOR_PER_TASK 1441 bool "Use a unique stack canary value for each task" 1442 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1443 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1444 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1445 default y 1446 help 1447 Due to the fact that GCC uses an ordinary symbol reference from 1448 which to load the value of the stack canary, this value can only 1449 change at reboot time on SMP systems, and all tasks running in the 1450 kernel's address space are forced to use the same canary value for 1451 the entire duration that the system is up. 1452 1453 Enable this option to switch to a different method that uses a 1454 different canary value for each task. 1455 1456endmenu 1457 1458menu "Boot options" 1459 1460config USE_OF 1461 bool "Flattened Device Tree support" 1462 select IRQ_DOMAIN 1463 select OF 1464 help 1465 Include support for flattened device tree machine descriptions. 1466 1467config ARCH_WANT_FLAT_DTB_INSTALL 1468 def_bool y 1469 1470config ATAGS 1471 bool "Support for the traditional ATAGS boot data passing" 1472 default y 1473 help 1474 This is the traditional way of passing data to the kernel at boot 1475 time. If you are solely relying on the flattened device tree (or 1476 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1477 to remove ATAGS support from your kernel binary. 1478 1479config DEPRECATED_PARAM_STRUCT 1480 bool "Provide old way to pass kernel parameters" 1481 depends on ATAGS 1482 help 1483 This was deprecated in 2001 and announced to live on for 5 years. 1484 Some old boot loaders still use this way. 1485 1486# Compressed boot loader in ROM. Yes, we really want to ask about 1487# TEXT and BSS so we preserve their values in the config files. 1488config ZBOOT_ROM_TEXT 1489 hex "Compressed ROM boot loader base address" 1490 default 0x0 1491 help 1492 The physical address at which the ROM-able zImage is to be 1493 placed in the target. Platforms which normally make use of 1494 ROM-able zImage formats normally set this to a suitable 1495 value in their defconfig file. 1496 1497 If ZBOOT_ROM is not enabled, this has no effect. 1498 1499config ZBOOT_ROM_BSS 1500 hex "Compressed ROM boot loader BSS address" 1501 default 0x0 1502 help 1503 The base address of an area of read/write memory in the target 1504 for the ROM-able zImage which must be available while the 1505 decompressor is running. It must be large enough to hold the 1506 entire decompressed kernel plus an additional 128 KiB. 1507 Platforms which normally make use of ROM-able zImage formats 1508 normally set this to a suitable value in their defconfig file. 1509 1510 If ZBOOT_ROM is not enabled, this has no effect. 1511 1512config ZBOOT_ROM 1513 bool "Compressed boot loader in ROM/flash" 1514 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1515 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1516 help 1517 Say Y here if you intend to execute your compressed kernel image 1518 (zImage) directly from ROM or flash. If unsure, say N. 1519 1520config ARM_APPENDED_DTB 1521 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1522 depends on OF 1523 help 1524 With this option, the boot code will look for a device tree binary 1525 (DTB) appended to zImage 1526 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1527 1528 This is meant as a backward compatibility convenience for those 1529 systems with a bootloader that can't be upgraded to accommodate 1530 the documented boot protocol using a device tree. 1531 1532 Beware that there is very little in terms of protection against 1533 this option being confused by leftover garbage in memory that might 1534 look like a DTB header after a reboot if no actual DTB is appended 1535 to zImage. Do not leave this option active in a production kernel 1536 if you don't intend to always append a DTB. Proper passing of the 1537 location into r2 of a bootloader provided DTB is always preferable 1538 to this option. 1539 1540config ARM_ATAG_DTB_COMPAT 1541 bool "Supplement the appended DTB with traditional ATAG information" 1542 depends on ARM_APPENDED_DTB 1543 help 1544 Some old bootloaders can't be updated to a DTB capable one, yet 1545 they provide ATAGs with memory configuration, the ramdisk address, 1546 the kernel cmdline string, etc. Such information is dynamically 1547 provided by the bootloader and can't always be stored in a static 1548 DTB. To allow a device tree enabled kernel to be used with such 1549 bootloaders, this option allows zImage to extract the information 1550 from the ATAG list and store it at run time into the appended DTB. 1551 1552choice 1553 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1554 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1555 1556config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1557 bool "Use bootloader kernel arguments if available" 1558 help 1559 Uses the command-line options passed by the boot loader instead of 1560 the device tree bootargs property. If the boot loader doesn't provide 1561 any, the device tree bootargs property will be used. 1562 1563config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1564 bool "Extend with bootloader kernel arguments" 1565 help 1566 The command-line arguments provided by the boot loader will be 1567 appended to the the device tree bootargs property. 1568 1569endchoice 1570 1571config CMDLINE 1572 string "Default kernel command string" 1573 default "" 1574 help 1575 On some architectures (e.g. CATS), there is currently no way 1576 for the boot loader to pass arguments to the kernel. For these 1577 architectures, you should supply some command-line options at build 1578 time by entering them here. As a minimum, you should specify the 1579 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1580 1581choice 1582 prompt "Kernel command line type" if CMDLINE != "" 1583 default CMDLINE_FROM_BOOTLOADER 1584 1585config CMDLINE_FROM_BOOTLOADER 1586 bool "Use bootloader kernel arguments if available" 1587 help 1588 Uses the command-line options passed by the boot loader. If 1589 the boot loader doesn't provide any, the default kernel command 1590 string provided in CMDLINE will be used. 1591 1592config CMDLINE_EXTEND 1593 bool "Extend bootloader kernel arguments" 1594 help 1595 The command-line arguments provided by the boot loader will be 1596 appended to the default kernel command string. 1597 1598config CMDLINE_FORCE 1599 bool "Always use the default kernel command string" 1600 help 1601 Always use the default kernel command string, even if the boot 1602 loader passes other arguments to the kernel. 1603 This is useful if you cannot or don't want to change the 1604 command-line options your boot loader passes to the kernel. 1605endchoice 1606 1607config XIP_KERNEL 1608 bool "Kernel Execute-In-Place from ROM" 1609 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1610 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1611 help 1612 Execute-In-Place allows the kernel to run from non-volatile storage 1613 directly addressable by the CPU, such as NOR flash. This saves RAM 1614 space since the text section of the kernel is not loaded from flash 1615 to RAM. Read-write sections, such as the data section and stack, 1616 are still copied to RAM. The XIP kernel is not compressed since 1617 it has to run directly from flash, so it will take more space to 1618 store it. The flash address used to link the kernel object files, 1619 and for storing it, is configuration dependent. Therefore, if you 1620 say Y here, you must know the proper physical address where to 1621 store the kernel image depending on your own flash memory usage. 1622 1623 Also note that the make target becomes "make xipImage" rather than 1624 "make zImage" or "make Image". The final kernel binary to put in 1625 ROM memory will be arch/arm/boot/xipImage. 1626 1627 If unsure, say N. 1628 1629config XIP_PHYS_ADDR 1630 hex "XIP Kernel Physical Location" 1631 depends on XIP_KERNEL 1632 default "0x00080000" 1633 help 1634 This is the physical address in your flash memory the kernel will 1635 be linked for and stored to. This address is dependent on your 1636 own flash usage. 1637 1638config XIP_DEFLATED_DATA 1639 bool "Store kernel .data section compressed in ROM" 1640 depends on XIP_KERNEL 1641 select ZLIB_INFLATE 1642 help 1643 Before the kernel is actually executed, its .data section has to be 1644 copied to RAM from ROM. This option allows for storing that data 1645 in compressed form and decompressed to RAM rather than merely being 1646 copied, saving some precious ROM space. A possible drawback is a 1647 slightly longer boot delay. 1648 1649config ARCH_SUPPORTS_KEXEC 1650 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1651 1652config ATAGS_PROC 1653 bool "Export atags in procfs" 1654 depends on ATAGS && KEXEC 1655 default y 1656 help 1657 Should the atags used to boot the kernel be exported in an "atags" 1658 file in procfs. Useful with kexec. 1659 1660config ARCH_SUPPORTS_CRASH_DUMP 1661 def_bool y 1662 1663config AUTO_ZRELADDR 1664 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1665 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1666 help 1667 ZRELADDR is the physical address where the decompressed kernel 1668 image will be placed. If AUTO_ZRELADDR is selected, the address 1669 will be determined at run-time, either by masking the current IP 1670 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1671 This assumes the zImage being placed in the first 128MB from 1672 start of memory. 1673 1674config EFI_STUB 1675 bool 1676 1677config EFI 1678 bool "UEFI runtime support" 1679 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1680 select UCS2_STRING 1681 select EFI_PARAMS_FROM_FDT 1682 select EFI_STUB 1683 select EFI_GENERIC_STUB 1684 select EFI_RUNTIME_WRAPPERS 1685 help 1686 This option provides support for runtime services provided 1687 by UEFI firmware (such as non-volatile variables, realtime 1688 clock, and platform reset). A UEFI stub is also provided to 1689 allow the kernel to be booted as an EFI application. This 1690 is only useful for kernels that may run on systems that have 1691 UEFI firmware. 1692 1693config DMI 1694 bool "Enable support for SMBIOS (DMI) tables" 1695 depends on EFI 1696 default y 1697 help 1698 This enables SMBIOS/DMI feature for systems. 1699 1700 This option is only useful on systems that have UEFI firmware. 1701 However, even with this option, the resultant kernel should 1702 continue to boot on existing non-UEFI platforms. 1703 1704 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1705 i.e., the the practice of identifying the platform via DMI to 1706 decide whether certain workarounds for buggy hardware and/or 1707 firmware need to be enabled. This would require the DMI subsystem 1708 to be enabled much earlier than we do on ARM, which is non-trivial. 1709 1710endmenu 1711 1712menu "CPU Power Management" 1713 1714source "drivers/cpufreq/Kconfig" 1715 1716source "drivers/cpuidle/Kconfig" 1717 1718endmenu 1719 1720menu "Floating point emulation" 1721 1722comment "At least one emulation must be selected" 1723 1724config FPE_NWFPE 1725 bool "NWFPE math emulation" 1726 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1727 help 1728 Say Y to include the NWFPE floating point emulator in the kernel. 1729 This is necessary to run most binaries. Linux does not currently 1730 support floating point hardware so you need to say Y here even if 1731 your machine has an FPA or floating point co-processor podule. 1732 1733 You may say N here if you are going to load the Acorn FPEmulator 1734 early in the bootup. 1735 1736config FPE_NWFPE_XP 1737 bool "Support extended precision" 1738 depends on FPE_NWFPE 1739 help 1740 Say Y to include 80-bit support in the kernel floating-point 1741 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1742 Note that gcc does not generate 80-bit operations by default, 1743 so in most cases this option only enlarges the size of the 1744 floating point emulator without any good reason. 1745 1746 You almost surely want to say N here. 1747 1748config FPE_FASTFPE 1749 bool "FastFPE math emulation (EXPERIMENTAL)" 1750 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1751 help 1752 Say Y here to include the FAST floating point emulator in the kernel. 1753 This is an experimental much faster emulator which now also has full 1754 precision for the mantissa. It does not support any exceptions. 1755 It is very simple, and approximately 3-6 times faster than NWFPE. 1756 1757 It should be sufficient for most programs. It may be not suitable 1758 for scientific calculations, but you have to check this for yourself. 1759 If you do not feel you need a faster FP emulation you should better 1760 choose NWFPE. 1761 1762config VFP 1763 bool "VFP-format floating point maths" 1764 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1765 help 1766 Say Y to include VFP support code in the kernel. This is needed 1767 if your hardware includes a VFP unit. 1768 1769 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1770 release notes and additional status information. 1771 1772 Say N if your target does not have VFP hardware. 1773 1774config VFPv3 1775 bool 1776 depends on VFP 1777 default y if CPU_V7 1778 1779config NEON 1780 bool "Advanced SIMD (NEON) Extension support" 1781 depends on VFPv3 && CPU_V7 1782 help 1783 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1784 Extension. 1785 1786config KERNEL_MODE_NEON 1787 bool "Support for NEON in kernel mode" 1788 depends on NEON && AEABI 1789 help 1790 Say Y to include support for NEON in kernel mode. 1791 1792endmenu 1793 1794menu "Power management options" 1795 1796source "kernel/power/Kconfig" 1797 1798config ARCH_SUSPEND_POSSIBLE 1799 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1800 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1801 def_bool y 1802 1803config ARM_CPU_SUSPEND 1804 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1805 depends on ARCH_SUSPEND_POSSIBLE 1806 1807config ARCH_HIBERNATION_POSSIBLE 1808 bool 1809 depends on MMU 1810 default y if ARCH_SUSPEND_POSSIBLE 1811 1812endmenu 1813 1814source "arch/arm/Kconfig.assembler" 1815