1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CC_CAN_LINK 10 select ARCH_HAS_CPU_CACHE_ALIASING 11 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 12 select ARCH_HAS_CURRENT_STACK_POINTER 13 select ARCH_HAS_DEBUG_VIRTUAL if MMU 14 select ARCH_HAS_DELAY_TIMER 15 select ARCH_HAS_DMA_ALLOC if MMU 16 select ARCH_HAS_DMA_OPS 17 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 18 select ARCH_HAS_ELF_RANDOMIZE 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_KEEPINITRD 21 select ARCH_HAS_KCOV 22 select ARCH_HAS_MEMBARRIER_SYNC_CORE 23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 24 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 25 select ARCH_HAS_SETUP_DMA_OPS 26 select ARCH_HAS_SET_MEMORY 27 select ARCH_STACKWALK 28 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 29 select ARCH_HAS_STRICT_MODULE_RWX if MMU 30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 31 select ARCH_HAS_SYNC_DMA_FOR_CPU 32 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 34 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 35 select ARCH_HAS_GCOV_PROFILE_ALL 36 select ARCH_KEEP_MEMBLOCK 37 select ARCH_HAS_UBSAN 38 select ARCH_MIGHT_HAVE_PC_PARPORT 39 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 40 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 41 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 42 select ARCH_SUPPORTS_ATOMIC_RMW 43 select ARCH_SUPPORTS_CFI 44 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 45 select ARCH_SUPPORTS_PER_VMA_LOCK 46 select ARCH_SUPPORTS_RT 47 select ARCH_USE_BUILTIN_BSWAP 48 select ARCH_USE_CMPXCHG_LOCKREF 49 select ARCH_USE_MEMTEST 50 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de 51 select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000 52 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 53 select ARCH_WANT_GENERAL_HUGETLB 54 select ARCH_WANT_IPC_PARSE_VERSION 55 select ARCH_WANT_LD_ORPHAN_WARN 56 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 57 select BUILDTIME_TABLE_SORT if MMU 58 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 59 select CLONE_BACKWARDS 60 select CPU_PM if SUSPEND || CPU_IDLE 61 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 62 select DMA_DECLARE_COHERENT 63 select DMA_GLOBAL_POOL if !MMU 64 select DMA_NONCOHERENT_MMAP if MMU 65 select EDAC_SUPPORT 66 select EDAC_ATOMIC_SCRUB 67 select GENERIC_ALLOCATOR 68 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 69 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 70 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 71 select GENERIC_IRQ_IPI if SMP 72 select GENERIC_CPU_AUTOPROBE 73 select GENERIC_CPU_DEVICES 74 select GENERIC_EARLY_IOREMAP 75 select GENERIC_IDLE_POLL_SETUP 76 select GENERIC_IRQ_MULTI_HANDLER 77 select GENERIC_IRQ_PROBE 78 select GENERIC_IRQ_SHOW 79 select GENERIC_IRQ_SHOW_LEVEL 80 select GENERIC_LIB_DEVMEM_IS_ALLOWED 81 select GENERIC_PCI_IOMAP 82 select GENERIC_SCHED_CLOCK 83 select GENERIC_SMP_IDLE_THREAD 84 select HARDIRQS_SW_RESEND 85 select HAS_IOPORT 86 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 87 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 && BITREVERSE 88 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU && (!PREEMPT_RT || !SMP) 89 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 90 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 91 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 92 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 93 select HAVE_ARCH_KSTACK_ERASE 94 select HAVE_ARCH_MMAP_RND_BITS if MMU 95 select HAVE_ARCH_PFN_VALID 96 select HAVE_ARCH_SECCOMP 97 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 98 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 99 select HAVE_ARCH_TRACEHOOK 100 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 101 select HAVE_ARM_SMCCC if CPU_V7 102 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 103 select HAVE_CONTEXT_TRACKING_USER 104 select HAVE_C_RECORDMCOUNT 105 select HAVE_BUILDTIME_MCOUNT_SORT 106 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 107 select HAVE_DMA_CONTIGUOUS if MMU 108 select HAVE_EXTRA_IPI_TRACEPOINTS 109 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 110 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 111 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 112 select HAVE_EXIT_THREAD 113 select HAVE_GUP_FAST if ARM_LPAE 114 select HAVE_FUNCTION_ERROR_INJECTION 115 select HAVE_FUNCTION_GRAPH_TRACER 116 select HAVE_FUNCTION_GRAPH_FREGS 117 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 118 select HAVE_GCC_PLUGINS 119 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 120 select HAVE_IRQ_TIME_ACCOUNTING 121 select HAVE_KERNEL_GZIP 122 select HAVE_KERNEL_LZ4 123 select HAVE_KERNEL_LZMA 124 select HAVE_KERNEL_LZO 125 select HAVE_KERNEL_XZ 126 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 127 select HAVE_KRETPROBES if HAVE_KPROBES 128 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY 129 select HAVE_MOD_ARCH_SPECIFIC 130 select HAVE_NMI 131 select HAVE_OPTPROBES if !THUMB2_KERNEL 132 select HAVE_PAGE_SIZE_4KB 133 select HAVE_PCI if MMU 134 select HAVE_PERF_EVENTS 135 select HAVE_PERF_REGS 136 select HAVE_PERF_USER_STACK_DUMP 137 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 138 select HAVE_REGS_AND_STACK_ACCESS_API 139 select HAVE_RSEQ 140 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 && !KASAN 141 select HAVE_STACKPROTECTOR 142 select HAVE_SYSCALL_TRACEPOINTS 143 select HAVE_UID16 144 select HAVE_VIRT_CPU_ACCOUNTING_GEN 145 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 146 select IRQ_FORCED_THREADING 147 select LOCK_MM_AND_FIND_VMA 148 select MODULES_USE_ELF_REL 149 select NEED_DMA_MAP_STATE 150 select OF_EARLY_FLATTREE if OF 151 select OLD_SIGACTION 152 select OLD_SIGSUSPEND3 153 select PCI_DOMAINS_GENERIC if PCI 154 select PCI_SYSCALL if PCI 155 select PERF_USE_VMALLOC 156 select RTC_LIB 157 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 158 select SYS_SUPPORTS_APM_EMULATION 159 select THREAD_INFO_IN_TASK 160 select TIMER_OF if OF 161 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 162 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 163 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 164 # Above selects are sorted alphabetically; please add new ones 165 # according to that. Thanks. 166 help 167 The ARM series is a line of low-power-consumption RISC chip designs 168 licensed by ARM Ltd and targeted at embedded applications and 169 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 170 manufactured, but legacy ARM-based PC hardware remains popular in 171 Europe. There is an ARM Linux project with a web page at 172 <http://www.arm.linux.org.uk/>. 173 174config ARM_HAS_GROUP_RELOCS 175 def_bool !COMPILE_TEST 176 help 177 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 178 relocations. The combined range is -/+ 256 MiB, which is usually 179 sufficient, but not for allyesconfig, so we disable this feature 180 when doing compile testing. 181 182config ARM_DMA_USE_IOMMU 183 bool 184 select NEED_SG_DMA_LENGTH 185 186if ARM_DMA_USE_IOMMU 187 188config ARM_DMA_IOMMU_ALIGNMENT 189 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 190 range 4 9 191 default 8 192 help 193 DMA mapping framework by default aligns all buffers to the smallest 194 PAGE_SIZE order which is greater than or equal to the requested buffer 195 size. This works well for buffers up to a few hundreds kilobytes, but 196 for larger buffers it just a waste of address space. Drivers which has 197 relatively small addressing window (like 64Mib) might run out of 198 virtual space with just a few allocations. 199 200 With this parameter you can specify the maximum PAGE_SIZE order for 201 DMA IOMMU buffers. Larger buffers will be aligned only to this 202 specified order. The order is expressed as a power of two multiplied 203 by the PAGE_SIZE. 204 205endif 206 207config SYS_SUPPORTS_APM_EMULATION 208 bool 209 210config HAVE_TCM 211 bool 212 select GENERIC_ALLOCATOR 213 214config HAVE_PROC_CPU 215 bool 216 217config NO_IOPORT_MAP 218 bool 219 220config SBUS 221 bool 222 223config STACKTRACE_SUPPORT 224 bool 225 default y 226 227config LOCKDEP_SUPPORT 228 bool 229 default y 230 231config ARCH_HAS_ILOG2_U32 232 bool 233 234config ARCH_HAS_ILOG2_U64 235 bool 236 237config ARCH_HAS_BANDGAP 238 bool 239 240config FIX_EARLYCON_MEM 241 def_bool y if MMU 242 243config GENERIC_HWEIGHT 244 bool 245 default y 246 247config GENERIC_CALIBRATE_DELAY 248 bool 249 default y 250 251config ARCH_MAY_HAVE_PC_FDC 252 bool 253 254config ARCH_SUPPORTS_UPROBES 255 def_bool y 256 257config GENERIC_ISA_DMA 258 bool 259 260config FIQ 261 bool 262 263config ARCH_MTD_XIP 264 bool 265 266config ARM_PATCH_PHYS_VIRT 267 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 268 default y 269 depends on MMU 270 help 271 Patch phys-to-virt and virt-to-phys translation functions at 272 boot and module load time according to the position of the 273 kernel in system memory. 274 275 This can only be used with non-XIP MMU kernels where the base 276 of physical memory is at a 2 MiB boundary. 277 278 Only disable this option if you know that you do not require 279 this feature (eg, building a kernel for a single machine) and 280 you need to shrink the kernel to the minimal size. 281 282config NEED_MACH_IO_H 283 bool 284 help 285 Select this when mach/io.h is required to provide special 286 definitions for this platform. The need for mach/io.h should 287 be avoided when possible. 288 289config NEED_MACH_MEMORY_H 290 bool 291 help 292 Select this when mach/memory.h is required to provide special 293 definitions for this platform. The need for mach/memory.h should 294 be avoided when possible. 295 296config PHYS_OFFSET 297 hex "Physical address of main memory" if MMU 298 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 299 default DRAM_BASE if !MMU 300 default 0x00000000 if ARCH_FOOTBRIDGE 301 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 302 default 0xa0000000 if ARCH_PXA 303 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 304 default 0 305 help 306 Please provide the physical address corresponding to the 307 location of main memory in your system. 308 309config GENERIC_BUG 310 def_bool y 311 depends on BUG 312 313config PGTABLE_LEVELS 314 int 315 default 3 if ARM_LPAE 316 default 2 317 318menu "System Type" 319 320config MMU 321 bool "MMU-based Paged Memory Management Support" 322 default y 323 help 324 Select if you want MMU-based virtualised addressing space 325 support by paged memory management. If unsure, say 'Y'. 326 327config ARM_SINGLE_ARMV7M 328 def_bool !MMU 329 select ARM_NVIC 330 select CPU_V7M 331 select NO_IOPORT_MAP 332 333config ARCH_MMAP_RND_BITS_MIN 334 default 8 335 336config ARCH_MMAP_RND_BITS_MAX 337 default 14 if PAGE_OFFSET=0x40000000 338 default 15 if PAGE_OFFSET=0x80000000 339 default 16 340 341config ARCH_MULTIPLATFORM 342 bool "Require kernel to be portable to multiple machines" if EXPERT 343 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 344 default y 345 help 346 In general, all Arm machines can be supported in a single 347 kernel image, covering either Armv4/v5 or Armv6/v7. 348 349 However, some configuration options require hardcoding machine 350 specific physical addresses or enable errata workarounds that may 351 break other machines. 352 353 Selecting N here allows using those options, including 354 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 355 356source "arch/arm/Kconfig.platforms" 357 358# 359# This is sorted alphabetically by mach-* pathname. However, plat-* 360# Kconfigs may be included either alphabetically (according to the 361# plat- suffix) or along side the corresponding mach-* source. 362# 363source "arch/arm/mach-actions/Kconfig" 364 365source "arch/arm/mach-alpine/Kconfig" 366 367source "arch/arm/mach-artpec/Kconfig" 368 369source "arch/arm/mach-aspeed/Kconfig" 370 371source "arch/arm/mach-at91/Kconfig" 372 373source "arch/arm/mach-axxia/Kconfig" 374 375source "arch/arm/mach-bcm/Kconfig" 376 377source "arch/arm/mach-berlin/Kconfig" 378 379source "arch/arm/mach-clps711x/Kconfig" 380 381source "arch/arm/mach-davinci/Kconfig" 382 383source "arch/arm/mach-digicolor/Kconfig" 384 385source "arch/arm/mach-dove/Kconfig" 386 387source "arch/arm/mach-ep93xx/Kconfig" 388 389source "arch/arm/mach-exynos/Kconfig" 390 391source "arch/arm/mach-footbridge/Kconfig" 392 393source "arch/arm/mach-gemini/Kconfig" 394 395source "arch/arm/mach-highbank/Kconfig" 396 397source "arch/arm/mach-hisi/Kconfig" 398 399source "arch/arm/mach-imx/Kconfig" 400 401source "arch/arm/mach-ixp4xx/Kconfig" 402 403source "arch/arm/mach-keystone/Kconfig" 404 405source "arch/arm/mach-lpc32xx/Kconfig" 406 407source "arch/arm/mach-mediatek/Kconfig" 408 409source "arch/arm/mach-meson/Kconfig" 410 411source "arch/arm/mach-milbeaut/Kconfig" 412 413source "arch/arm/mach-mmp/Kconfig" 414 415source "arch/arm/mach-mstar/Kconfig" 416 417source "arch/arm/mach-mv78xx0/Kconfig" 418 419source "arch/arm/mach-mvebu/Kconfig" 420 421source "arch/arm/mach-mxs/Kconfig" 422 423source "arch/arm/mach-nomadik/Kconfig" 424 425source "arch/arm/mach-npcm/Kconfig" 426 427source "arch/arm/mach-omap1/Kconfig" 428 429source "arch/arm/mach-omap2/Kconfig" 430 431source "arch/arm/mach-orion5x/Kconfig" 432 433source "arch/arm/mach-pxa/Kconfig" 434 435source "arch/arm/mach-qcom/Kconfig" 436 437source "arch/arm/mach-realtek/Kconfig" 438 439source "arch/arm/mach-rpc/Kconfig" 440 441source "arch/arm/mach-rockchip/Kconfig" 442 443source "arch/arm/mach-s3c/Kconfig" 444 445source "arch/arm/mach-s5pv210/Kconfig" 446 447source "arch/arm/mach-sa1100/Kconfig" 448 449source "arch/arm/mach-shmobile/Kconfig" 450 451source "arch/arm/mach-socfpga/Kconfig" 452 453source "arch/arm/mach-spear/Kconfig" 454 455source "arch/arm/mach-sti/Kconfig" 456 457source "arch/arm/mach-stm32/Kconfig" 458 459source "arch/arm/mach-sunxi/Kconfig" 460 461source "arch/arm/mach-tegra/Kconfig" 462 463source "arch/arm/mach-ux500/Kconfig" 464 465source "arch/arm/mach-versatile/Kconfig" 466 467source "arch/arm/mach-vt8500/Kconfig" 468 469source "arch/arm/mach-zte/Kconfig" 470 471source "arch/arm/mach-zynq/Kconfig" 472 473# ARMv7-M architecture 474config ARCH_LPC18XX 475 bool "NXP LPC18xx/LPC43xx (DEPRECATED)" 476 depends on ARM_SINGLE_ARMV7M 477 select ARCH_HAS_RESET_CONTROLLER 478 select ARM_AMBA 479 select CLKSRC_LPC32XX 480 select PINCTRL 481 help 482 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 483 high performance microcontrollers. 484 485 This platform is scheduled for removal in early 2027 486 487config ARCH_MPS2 488 bool "ARM MPS2 platform (DEPRECATED)" 489 depends on ARM_SINGLE_ARMV7M 490 select ARM_AMBA 491 select CLKSRC_MPS2 492 help 493 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 494 with a range of available cores like Cortex-M3/M4/M7. 495 496 Please, note that depends which Application Note is used memory map 497 for the platform may vary, so adjustment of RAM base might be needed. 498 499 This platform is scheduled for removal in early 2027 500 501# Definitions to make life easier 502config ARCH_ACORN 503 bool 504 505config PLAT_ORION 506 bool 507 select CLKSRC_MMIO 508 select GENERIC_IRQ_CHIP 509 select IRQ_DOMAIN 510 511config PLAT_ORION_LEGACY 512 bool 513 select PLAT_ORION 514 515config PLAT_VERSATILE 516 bool 517 518source "arch/arm/mm/Kconfig" 519 520config IWMMXT 521 bool "Enable iWMMXt support (DEPRECATED)" 522 depends on PXA27x || PXA3xx || ARCH_MMP 523 help 524 Enable support for iWMMXt context switching at run time if 525 running on a CPU that supports it. 526 527 Machines that actually support this feature are very rare, 528 and support is deprecated in new gcc-14. While there were a 529 few applications that used this in the past, none are known 530 to still do so. 531 532 If you use this, please send a patch to remove the 533 deprecation, otherwise this will be removed in early 534 2027. 535 536if !MMU 537source "arch/arm/Kconfig-nommu" 538endif 539 540config PJ4B_ERRATA_4742 541 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 542 depends on CPU_PJ4B && MACH_ARMADA_370 543 default y 544 help 545 When coming out of either a Wait for Interrupt (WFI) or a Wait for 546 Event (WFE) IDLE states, a specific timing sensitivity exists between 547 the retiring WFI/WFE instructions and the newly issued subsequent 548 instructions. This sensitivity can result in a CPU hang scenario. 549 Workaround: 550 The software must insert either a Data Synchronization Barrier (DSB) 551 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 552 instruction 553 554config ARM_ERRATA_326103 555 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 556 depends on CPU_V6 557 help 558 Executing a SWP instruction to read-only memory does not set bit 11 559 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 560 treat the access as a read, preventing a COW from occurring and 561 causing the faulting task to livelock. 562 563config ARM_ERRATA_411920 564 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 565 depends on CPU_V6 || CPU_V6K 566 help 567 Invalidation of the Instruction Cache operation can 568 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 569 It does not affect the MPCore. This option enables the ARM Ltd. 570 recommended workaround. 571 572config ARM_ERRATA_430973 573 bool "ARM errata: Stale prediction on replaced interworking branch" 574 depends on CPU_V7 575 help 576 This option enables the workaround for the 430973 Cortex-A8 577 r1p* erratum. If a code sequence containing an ARM/Thumb 578 interworking branch is replaced with another code sequence at the 579 same virtual address, whether due to self-modifying code or virtual 580 to physical address re-mapping, Cortex-A8 does not recover from the 581 stale interworking branch prediction. This results in Cortex-A8 582 executing the new code sequence in the incorrect ARM or Thumb state. 583 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 584 and also flushes the branch target cache at every context switch. 585 Note that setting specific bits in the ACTLR register may not be 586 available in non-secure mode. 587 588config ARM_ERRATA_458693 589 bool "ARM errata: Processor deadlock when a false hazard is created" 590 depends on CPU_V7 591 depends on !ARCH_MULTIPLATFORM 592 help 593 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 594 erratum. For very specific sequences of memory operations, it is 595 possible for a hazard condition intended for a cache line to instead 596 be incorrectly associated with a different cache line. This false 597 hazard might then cause a processor deadlock. The workaround enables 598 the L1 caching of the NEON accesses and disables the PLD instruction 599 in the ACTLR register. Note that setting specific bits in the ACTLR 600 register may not be available in non-secure mode and thus is not 601 available on a multiplatform kernel. This should be applied by the 602 bootloader instead. 603 604config ARM_ERRATA_460075 605 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 606 depends on CPU_V7 607 depends on !ARCH_MULTIPLATFORM 608 help 609 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 610 erratum. Any asynchronous access to the L2 cache may encounter a 611 situation in which recent store transactions to the L2 cache are lost 612 and overwritten with stale memory contents from external memory. The 613 workaround disables the write-allocate mode for the L2 cache via the 614 ACTLR register. Note that setting specific bits in the ACTLR register 615 may not be available in non-secure mode and thus is not available on 616 a multiplatform kernel. This should be applied by the bootloader 617 instead. 618 619config ARM_ERRATA_742230 620 bool "ARM errata: DMB operation may be faulty" 621 depends on CPU_V7 && SMP 622 depends on !ARCH_MULTIPLATFORM 623 help 624 This option enables the workaround for the 742230 Cortex-A9 625 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 626 between two write operations may not ensure the correct visibility 627 ordering of the two writes. This workaround sets a specific bit in 628 the diagnostic register of the Cortex-A9 which causes the DMB 629 instruction to behave as a DSB, ensuring the correct behaviour of 630 the two writes. Note that setting specific bits in the diagnostics 631 register may not be available in non-secure mode and thus is not 632 available on a multiplatform kernel. This should be applied by the 633 bootloader instead. 634 635config ARM_ERRATA_742231 636 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 637 depends on CPU_V7 && SMP 638 depends on !ARCH_MULTIPLATFORM 639 help 640 This option enables the workaround for the 742231 Cortex-A9 641 (r2p0..r2p2) erratum. Under certain conditions, specific to the 642 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 643 accessing some data located in the same cache line, may get corrupted 644 data due to bad handling of the address hazard when the line gets 645 replaced from one of the CPUs at the same time as another CPU is 646 accessing it. This workaround sets specific bits in the diagnostic 647 register of the Cortex-A9 which reduces the linefill issuing 648 capabilities of the processor. Note that setting specific bits in the 649 diagnostics register may not be available in non-secure mode and thus 650 is not available on a multiplatform kernel. This should be applied by 651 the bootloader instead. 652 653config ARM_ERRATA_643719 654 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 655 depends on CPU_V7 && SMP 656 default y 657 help 658 This option enables the workaround for the 643719 Cortex-A9 (prior to 659 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 660 register returns zero when it should return one. The workaround 661 corrects this value, ensuring cache maintenance operations which use 662 it behave as intended and avoiding data corruption. 663 664config ARM_ERRATA_720789 665 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 666 depends on CPU_V7 667 help 668 This option enables the workaround for the 720789 Cortex-A9 (prior to 669 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 670 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 671 As a consequence of this erratum, some TLB entries which should be 672 invalidated are not, resulting in an incoherency in the system page 673 tables. The workaround changes the TLB flushing routines to invalidate 674 entries regardless of the ASID. 675 676config ARM_ERRATA_743622 677 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 678 depends on CPU_V7 679 depends on !ARCH_MULTIPLATFORM 680 help 681 This option enables the workaround for the 743622 Cortex-A9 682 (r2p*) erratum. Under very rare conditions, a faulty 683 optimisation in the Cortex-A9 Store Buffer may lead to data 684 corruption. This workaround sets a specific bit in the diagnostic 685 register of the Cortex-A9 which disables the Store Buffer 686 optimisation, preventing the defect from occurring. This has no 687 visible impact on the overall performance or power consumption of the 688 processor. Note that setting specific bits in the diagnostics register 689 may not be available in non-secure mode and thus is not available on a 690 multiplatform kernel. This should be applied by the bootloader instead. 691 692config ARM_ERRATA_751472 693 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 694 depends on CPU_V7 695 depends on !ARCH_MULTIPLATFORM 696 help 697 This option enables the workaround for the 751472 Cortex-A9 (prior 698 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 699 completion of a following broadcasted operation if the second 700 operation is received by a CPU before the ICIALLUIS has completed, 701 potentially leading to corrupted entries in the cache or TLB. 702 Note that setting specific bits in the diagnostics register may 703 not be available in non-secure mode and thus is not available on 704 a multiplatform kernel. This should be applied by the bootloader 705 instead. 706 707config ARM_ERRATA_754322 708 bool "ARM errata: possible faulty MMU translations following an ASID switch" 709 depends on CPU_V7 710 help 711 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 712 r3p*) erratum. A speculative memory access may cause a page table walk 713 which starts prior to an ASID switch but completes afterwards. This 714 can populate the micro-TLB with a stale entry which may be hit with 715 the new ASID. This workaround places two dsb instructions in the mm 716 switching code so that no page table walks can cross the ASID switch. 717 718config ARM_ERRATA_754327 719 bool "ARM errata: no automatic Store Buffer drain" 720 depends on CPU_V7 && SMP 721 help 722 This option enables the workaround for the 754327 Cortex-A9 (prior to 723 r2p0) erratum. The Store Buffer does not have any automatic draining 724 mechanism and therefore a livelock may occur if an external agent 725 continuously polls a memory location waiting to observe an update. 726 This workaround defines cpu_relax() as smp_mb(), preventing correctly 727 written polling loops from denying visibility of updates to memory. 728 729config ARM_ERRATA_364296 730 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 731 depends on CPU_V6 732 help 733 This options enables the workaround for the 364296 ARM1136 734 r0p2 erratum (possible cache data corruption with 735 hit-under-miss enabled). It sets the undocumented bit 31 in 736 the auxiliary control register and the FI bit in the control 737 register, thus disabling hit-under-miss without putting the 738 processor into full low interrupt latency mode. ARM11MPCore 739 is not affected. 740 741config ARM_ERRATA_764369 742 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 743 depends on CPU_V7 && SMP 744 help 745 This option enables the workaround for erratum 764369 746 affecting Cortex-A9 MPCore with two or more processors (all 747 current revisions). Under certain timing circumstances, a data 748 cache line maintenance operation by MVA targeting an Inner 749 Shareable memory region may fail to proceed up to either the 750 Point of Coherency or to the Point of Unification of the 751 system. This workaround adds a DSB instruction before the 752 relevant cache maintenance functions and sets a specific bit 753 in the diagnostic control register of the SCU. 754 755config ARM_ERRATA_764319 756 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 757 depends on CPU_V7 758 help 759 This option enables the workaround for the 764319 Cortex-A9 erratum. 760 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 761 unexpected Undefined Instruction exception when the DBGSWENABLE 762 external pin is set to 0, even when the CP14 accesses are performed 763 from a privileged mode. This work around catches the exception in a 764 way the kernel does not stop execution. 765 766config ARM_ERRATA_775420 767 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 768 depends on CPU_V7 769 help 770 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 771 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 772 operation aborts with MMU exception, it might cause the processor 773 to deadlock. This workaround puts DSB before executing ISB if 774 an abort may occur on cache maintenance. 775 776config ARM_ERRATA_798181 777 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 778 depends on CPU_V7 && SMP 779 help 780 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 781 adequately shooting down all use of the old entries. This 782 option enables the Linux kernel workaround for this erratum 783 which sends an IPI to the CPUs that are running the same ASID 784 as the one being invalidated. 785 786config ARM_ERRATA_773022 787 bool "ARM errata: incorrect instructions may be executed from loop buffer" 788 depends on CPU_V7 789 help 790 This option enables the workaround for the 773022 Cortex-A15 791 (up to r0p4) erratum. In certain rare sequences of code, the 792 loop buffer may deliver incorrect instructions. This 793 workaround disables the loop buffer to avoid the erratum. 794 795config ARM_ERRATA_818325_852422 796 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 797 depends on CPU_V7 798 help 799 This option enables the workaround for: 800 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 801 instruction might deadlock. Fixed in r0p1. 802 - Cortex-A12 852422: Execution of a sequence of instructions might 803 lead to either a data corruption or a CPU deadlock. Not fixed in 804 any Cortex-A12 cores yet. 805 This workaround for all both errata involves setting bit[12] of the 806 Feature Register. This bit disables an optimisation applied to a 807 sequence of 2 instructions that use opposing condition codes. 808 809config ARM_ERRATA_821420 810 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 811 depends on CPU_V7 812 help 813 This option enables the workaround for the 821420 Cortex-A12 814 (all revs) erratum. In very rare timing conditions, a sequence 815 of VMOV to Core registers instructions, for which the second 816 one is in the shadow of a branch or abort, can lead to a 817 deadlock when the VMOV instructions are issued out-of-order. 818 819config ARM_ERRATA_825619 820 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 821 depends on CPU_V7 822 help 823 This option enables the workaround for the 825619 Cortex-A12 824 (all revs) erratum. Within rare timing constraints, executing a 825 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 826 and Device/Strongly-Ordered loads and stores might cause deadlock 827 828config ARM_ERRATA_857271 829 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 830 depends on CPU_V7 831 help 832 This option enables the workaround for the 857271 Cortex-A12 833 (all revs) erratum. Under very rare timing conditions, the CPU might 834 hang. The workaround is expected to have a < 1% performance impact. 835 836config ARM_ERRATA_852421 837 bool "ARM errata: A17: DMB ST might fail to create order between stores" 838 depends on CPU_V7 839 help 840 This option enables the workaround for the 852421 Cortex-A17 841 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 842 execution of a DMB ST instruction might fail to properly order 843 stores from GroupA and stores from GroupB. 844 845config ARM_ERRATA_852423 846 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 847 depends on CPU_V7 848 help 849 This option enables the workaround for: 850 - Cortex-A17 852423: Execution of a sequence of instructions might 851 lead to either a data corruption or a CPU deadlock. Not fixed in 852 any Cortex-A17 cores yet. 853 This is identical to Cortex-A12 erratum 852422. It is a separate 854 config option from the A12 erratum due to the way errata are checked 855 for and handled. 856 857config ARM_ERRATA_857272 858 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 859 depends on CPU_V7 860 help 861 This option enables the workaround for the 857272 Cortex-A17 erratum. 862 This erratum is not known to be fixed in any A17 revision. 863 This is identical to Cortex-A12 erratum 857271. It is a separate 864 config option from the A12 erratum due to the way errata are checked 865 for and handled. 866 867endmenu 868 869source "arch/arm/common/Kconfig" 870 871menu "Bus support" 872 873config ISA 874 bool 875 help 876 Find out whether you have ISA slots on your motherboard. ISA is the 877 name of a bus system, i.e. the way the CPU talks to the other stuff 878 inside your box. Other bus systems are PCI, EISA, MicroChannel 879 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 880 newer boards don't support it. If you have ISA, say Y, otherwise N. 881 882# Select ISA DMA interface 883config ISA_DMA_API 884 bool 885 886config ARM_ERRATA_814220 887 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 888 depends on CPU_V7 889 help 890 The v7 ARM states that all cache and branch predictor maintenance 891 operations that do not specify an address execute, relative to 892 each other, in program order. 893 However, because of this erratum, an L2 set/way cache maintenance 894 operation can overtake an L1 set/way cache maintenance operation. 895 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 896 r0p4, r0p5. 897 898endmenu 899 900menu "Kernel Features" 901 902config HAVE_SMP 903 bool 904 help 905 This option should be selected by machines which have an SMP- 906 capable CPU. 907 908 The only effect of this option is to make the SMP-related 909 options available to the user for configuration. 910 911config SMP 912 bool "Symmetric Multi-Processing" 913 depends on CPU_V6K || CPU_V7 914 depends on HAVE_SMP 915 depends on MMU || ARM_MPU 916 select IRQ_WORK 917 help 918 This enables support for systems with more than one CPU. If you have 919 a system with only one CPU, say N. If you have a system with more 920 than one CPU, say Y. 921 922 If you say N here, the kernel will run on uni- and multiprocessor 923 machines, but will use only one CPU of a multiprocessor machine. If 924 you say Y here, the kernel will run on many, but not all, 925 uniprocessor machines. On a uniprocessor machine, the kernel 926 will run faster if you say N here. 927 928 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 929 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 930 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 931 932 If you don't know what to do here, say N. 933 934config SMP_ON_UP 935 bool "Allow booting SMP kernel on uniprocessor systems" 936 depends on SMP && MMU 937 default y 938 help 939 SMP kernels contain instructions which fail on non-SMP processors. 940 Enabling this option allows the kernel to modify itself to make 941 these instructions safe. Disabling it allows about 1K of space 942 savings. 943 944 If you don't know what to do here, say Y. 945 946 947config CURRENT_POINTER_IN_TPIDRURO 948 def_bool y 949 depends on CPU_32v6K && !CPU_V6 950 951config IRQSTACKS 952 def_bool y 953 select HAVE_IRQ_EXIT_ON_IRQ_STACK 954 select HAVE_SOFTIRQ_ON_OWN_STACK 955 956config ARM_CPU_TOPOLOGY 957 bool "Support cpu topology definition" 958 depends on SMP && CPU_V7 959 select ARCH_SUPPORTS_SCHED_MC 960 select ARCH_SUPPORTS_SCHED_SMT 961 default y 962 help 963 Support ARM cpu topology definition. The MPIDR register defines 964 affinity between processors which is then used to describe the cpu 965 topology of an ARM System. 966 967config HAVE_ARM_SCU 968 bool 969 help 970 This option enables support for the ARM snoop control unit 971 972config HAVE_ARM_ARCH_TIMER 973 bool "Architected timer support" 974 depends on CPU_V7 975 select ARM_ARCH_TIMER 976 help 977 This option enables support for the ARM architected timer 978 979config HAVE_ARM_TWD 980 bool 981 help 982 This options enables support for the ARM timer and watchdog unit 983 984config MCPM 985 bool "Multi-Cluster Power Management" 986 depends on CPU_V7 && SMP 987 help 988 This option provides the common power management infrastructure 989 for (multi-)cluster based systems, such as big.LITTLE based 990 systems. 991 992config MCPM_QUAD_CLUSTER 993 bool 994 depends on MCPM 995 help 996 To avoid wasting resources unnecessarily, MCPM only supports up 997 to 2 clusters by default. 998 Platforms with 3 or 4 clusters that use MCPM must select this 999 option to allow the additional clusters to be managed. 1000 1001config BIG_LITTLE 1002 bool "big.LITTLE support (Experimental)" 1003 depends on CPU_V7 && SMP 1004 select MCPM 1005 help 1006 This option enables support selections for the big.LITTLE 1007 system architecture. 1008 1009config BL_SWITCHER 1010 bool "big.LITTLE switcher support" 1011 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1012 select CPU_PM 1013 help 1014 The big.LITTLE "switcher" provides the core functionality to 1015 transparently handle transition between a cluster of A15's 1016 and a cluster of A7's in a big.LITTLE system. 1017 1018config BL_SWITCHER_DUMMY_IF 1019 tristate "Simple big.LITTLE switcher user interface" 1020 depends on BL_SWITCHER && DEBUG_KERNEL 1021 help 1022 This is a simple and dummy char dev interface to control 1023 the big.LITTLE switcher core code. It is meant for 1024 debugging purposes only. 1025 1026choice 1027 prompt "Memory split" 1028 depends on MMU 1029 default VMSPLIT_3G 1030 help 1031 Select the desired split between kernel and user memory. 1032 1033 If you are not absolutely sure what you are doing, leave this 1034 option alone! 1035 1036 config VMSPLIT_3G 1037 bool "3G/1G user/kernel split" 1038 config VMSPLIT_3G_OPT 1039 depends on !ARM_LPAE 1040 bool "3G/1G user/kernel split (for full 1G low memory)" 1041 config VMSPLIT_2G 1042 bool "2G/2G user/kernel split" 1043 config VMSPLIT_1G 1044 bool "1G/3G user/kernel split" 1045endchoice 1046 1047config PAGE_OFFSET 1048 hex 1049 default PHYS_OFFSET if !MMU 1050 default 0x40000000 if VMSPLIT_1G 1051 default 0x80000000 if VMSPLIT_2G 1052 default 0xB0000000 if VMSPLIT_3G_OPT 1053 default 0xC0000000 1054 1055config KASAN_SHADOW_OFFSET 1056 hex 1057 depends on KASAN 1058 default 0x1f000000 if PAGE_OFFSET=0x40000000 1059 default 0x5f000000 if PAGE_OFFSET=0x80000000 1060 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1061 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1062 default 0xffffffff 1063 1064config NR_CPUS 1065 int "Maximum number of CPUs (2-32)" 1066 range 2 16 if DEBUG_KMAP_LOCAL 1067 range 2 32 if !DEBUG_KMAP_LOCAL 1068 depends on SMP 1069 default "4" 1070 help 1071 The maximum number of CPUs that the kernel can support. 1072 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1073 debugging is enabled, which uses half of the per-CPU fixmap 1074 slots as guard regions. 1075 1076config HOTPLUG_CPU 1077 bool "Support for hot-pluggable CPUs" 1078 depends on SMP 1079 select GENERIC_IRQ_MIGRATION 1080 help 1081 Say Y here to experiment with turning CPUs off and on. CPUs 1082 can be controlled through /sys/devices/system/cpu. 1083 1084config ARM_PSCI 1085 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1086 depends on HAVE_ARM_SMCCC 1087 select ARM_PSCI_FW 1088 help 1089 Say Y here if you want Linux to communicate with system firmware 1090 implementing the PSCI specification for CPU-centric power 1091 management operations described in ARM document number ARM DEN 1092 0022A ("Power State Coordination Interface System Software on 1093 ARM processors"). 1094 1095config HZ_FIXED 1096 int 1097 default 128 if SOC_AT91RM9200 1098 default 0 1099 1100choice 1101 depends on HZ_FIXED = 0 1102 prompt "Timer frequency" 1103 1104config HZ_100 1105 bool "100 Hz" 1106 1107config HZ_200 1108 bool "200 Hz" 1109 1110config HZ_250 1111 bool "250 Hz" 1112 1113config HZ_300 1114 bool "300 Hz" 1115 1116config HZ_500 1117 bool "500 Hz" 1118 1119config HZ_1000 1120 bool "1000 Hz" 1121 1122endchoice 1123 1124config HZ 1125 int 1126 default HZ_FIXED if HZ_FIXED != 0 1127 default 100 if HZ_100 1128 default 200 if HZ_200 1129 default 250 if HZ_250 1130 default 300 if HZ_300 1131 default 500 if HZ_500 1132 default 1000 1133 1134config SCHED_HRTICK 1135 def_bool HIGH_RES_TIMERS 1136 1137config THUMB2_KERNEL 1138 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1139 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1140 default y if CPU_THUMBONLY 1141 select ARM_UNWIND 1142 help 1143 By enabling this option, the kernel will be compiled in 1144 Thumb-2 mode. 1145 1146 If unsure, say N. 1147 1148config ARM_PATCH_IDIV 1149 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1150 depends on CPU_32v7 1151 default y 1152 help 1153 The ARM compiler inserts calls to __aeabi_idiv() and 1154 __aeabi_uidiv() when it needs to perform division on signed 1155 and unsigned integers. Some v7 CPUs have support for the sdiv 1156 and udiv instructions that can be used to implement those 1157 functions. 1158 1159 Enabling this option allows the kernel to modify itself to 1160 replace the first two instructions of these library functions 1161 with the sdiv or udiv plus "bx lr" instructions when the CPU 1162 it is running on supports them. Typically this will be faster 1163 and less power intensive than running the original library 1164 code to do integer division. 1165 1166config AEABI 1167 bool "Use the ARM EABI to compile the kernel" if CPU_SA110 || CPU_SA1100 1168 default y 1169 help 1170 The Arm EABI is the default ABI on all modern Linux 1171 distributions, replacing the obsolete and "OABI" that was 1172 commonly used on ARMv4 distributions before ca. 2013. 1173 1174 Everyone should enable this, as support for OABI user space 1175 was dropped in gcc-4.8 and most distributions after ca. 2013. 1176 1177 Support for OABI mode will be removed from the kernel 1178 once Intel StrongARM CPUs are phased out. 1179 1180config OABI_COMPAT 1181 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1182 depends on AEABI && !THUMB2_KERNEL 1183 depends on CPU_SA110 || CPU_SA1100 1184 help 1185 This option preserves the old syscall interface along with the 1186 new (ARM EABI) one. It also provides a compatibility layer to 1187 intercept syscalls that have structure arguments which layout 1188 in memory differs between the legacy ABI and the new ARM EABI 1189 (only for non "thumb" binaries). This option adds a tiny 1190 overhead to all syscalls and produces a slightly larger kernel. 1191 1192 The seccomp filter system will not be available when this is 1193 selected, since there is no way yet to sensibly distinguish 1194 between calling conventions during filtering. 1195 1196 Support for OABI_COMPAT will be removed from the kernel 1197 once Intel StrongARM CPUs are phased out. 1198 1199config ARCH_SELECT_MEMORY_MODEL 1200 def_bool y 1201 1202config ARCH_FLATMEM_ENABLE 1203 def_bool !(ARCH_RPC || ARCH_SA1100) 1204 1205config ARCH_SPARSEMEM_ENABLE 1206 def_bool !ARCH_FOOTBRIDGE 1207 select SPARSEMEM_STATIC if SPARSEMEM 1208 1209config HIGHMEM 1210 bool "High Memory Support" 1211 depends on MMU 1212 select KMAP_LOCAL 1213 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1214 help 1215 The address space of ARM processors is only 4 Gigabytes large 1216 and it has to accommodate user address space, kernel address 1217 space as well as some memory mapped IO. That means that, if you 1218 have a large amount of physical memory and/or IO, not all of the 1219 memory can be "permanently mapped" by the kernel. The physical 1220 memory that is not permanently mapped is called "high memory". 1221 1222 Depending on the selected kernel/user memory split, minimum 1223 vmalloc space and actual amount of RAM, you may not need this 1224 option which should result in a slightly faster kernel. 1225 1226 If unsure, say n. 1227 1228config HIGHPTE 1229 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1230 depends on HIGHMEM && !PREEMPT_RT 1231 default y 1232 help 1233 The VM uses one page of physical memory for each page table. 1234 For systems with a lot of processes, this can use a lot of 1235 precious low memory, eventually leading to low memory being 1236 consumed by page tables. Setting this option will allow 1237 user-space 2nd level page tables to reside in high memory. 1238 1239config ARM_PAN 1240 bool "Enable privileged no-access" 1241 depends on MMU 1242 default y 1243 help 1244 Increase kernel security by ensuring that normal kernel accesses 1245 are unable to access userspace addresses. This can help prevent 1246 use-after-free bugs becoming an exploitable privilege escalation 1247 by ensuring that magic values (such as LIST_POISON) will always 1248 fault when dereferenced. 1249 1250 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1251 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1252 1253config CPU_SW_DOMAIN_PAN 1254 def_bool y 1255 depends on ARM_PAN && !ARM_LPAE 1256 help 1257 Enable use of CPU domains to implement privileged no-access. 1258 1259 CPUs with low-vector mappings use a best-efforts implementation. 1260 Their lower 1MB needs to remain accessible for the vectors, but 1261 the remainder of userspace will become appropriately inaccessible. 1262 1263config CPU_TTBR0_PAN 1264 def_bool y 1265 depends on ARM_PAN && ARM_LPAE 1266 help 1267 Enable privileged no-access by disabling TTBR0 page table walks when 1268 running in kernel mode. 1269 1270config HW_PERF_EVENTS 1271 def_bool y 1272 depends on ARM_PMU 1273 1274config ARM_MODULE_PLTS 1275 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1276 depends on MODULES 1277 select KASAN_VMALLOC if KASAN 1278 default y 1279 help 1280 Allocate PLTs when loading modules so that jumps and calls whose 1281 targets are too far away for their relative offsets to be encoded 1282 in the instructions themselves can be bounced via veneers in the 1283 module's PLT. This allows modules to be allocated in the generic 1284 vmalloc area after the dedicated module memory area has been 1285 exhausted. The modules will use slightly more memory, but after 1286 rounding up to page size, the actual memory footprint is usually 1287 the same. 1288 1289 Disabling this is usually safe for small single-platform 1290 configurations. If unsure, say y. 1291 1292config ARCH_FORCE_MAX_ORDER 1293 int "Order of maximal physically contiguous allocations" 1294 default "11" if SOC_AM33XX 1295 default "8" if SA1111 1296 default "10" 1297 help 1298 The kernel page allocator limits the size of maximal physically 1299 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1300 defines the maximal power of two of number of pages that can be 1301 allocated as a single contiguous block. This option allows 1302 overriding the default setting when ability to allocate very 1303 large blocks of physically contiguous memory is required. 1304 1305 Don't change if unsure. 1306 1307config ALIGNMENT_TRAP 1308 def_bool CPU_CP15_MMU 1309 select HAVE_PROC_CPU if PROC_FS 1310 help 1311 ARM processors cannot fetch/store information which is not 1312 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1313 address divisible by 4. On 32-bit ARM processors, these non-aligned 1314 fetch/store instructions will be emulated in software if you say 1315 here, which has a severe performance impact. This is necessary for 1316 correct operation of some network protocols. With an IP-only 1317 configuration it is safe to say N, otherwise say Y. 1318 1319config UACCESS_WITH_MEMCPY 1320 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1321 depends on MMU 1322 default y if CPU_FEROCEON 1323 help 1324 Implement faster copy_to_user and clear_user methods for CPU 1325 cores where a 8-word STM instruction give significantly higher 1326 memory write throughput than a sequence of individual 32bit stores. 1327 1328 A possible side effect is a slight increase in scheduling latency 1329 between threads sharing the same address space if they invoke 1330 such copy operations with large buffers. 1331 1332 However, if the CPU data cache is using a write-allocate mode, 1333 this option is unlikely to provide any performance gain. 1334 1335config PARAVIRT 1336 bool "Enable paravirtualization code" 1337 select HAVE_PV_STEAL_CLOCK_GEN 1338 help 1339 This changes the kernel so it can modify itself when it is run 1340 under a hypervisor, potentially improving performance significantly 1341 over full virtualization. 1342 1343config PARAVIRT_TIME_ACCOUNTING 1344 bool "Paravirtual steal time accounting" 1345 select PARAVIRT 1346 help 1347 Select this option to enable fine granularity task steal time 1348 accounting. Time spent executing other tasks in parallel with 1349 the current vCPU is discounted from the vCPU power. To account for 1350 that, there can be a small performance impact. 1351 1352 If in doubt, say N here. 1353 1354config XEN_DOM0 1355 def_bool y 1356 depends on XEN 1357 1358config XEN 1359 bool "Xen guest support on ARM" 1360 depends on ARM && AEABI && OF 1361 depends on CPU_V7 && !CPU_V6 1362 depends on !GENERIC_ATOMIC64 1363 depends on MMU 1364 select ARCH_DMA_ADDR_T_64BIT 1365 select ARM_PSCI 1366 select SWIOTLB 1367 select SWIOTLB_XEN 1368 select PARAVIRT 1369 help 1370 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1371 1372config CC_HAVE_STACKPROTECTOR_TLS 1373 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1374 1375config STACKPROTECTOR_PER_TASK 1376 bool "Use a unique stack canary value for each task" 1377 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1378 depends on CC_HAVE_STACKPROTECTOR_TLS 1379 default y 1380 help 1381 Due to the fact that GCC uses an ordinary symbol reference from 1382 which to load the value of the stack canary, this value can only 1383 change at reboot time on SMP systems, and all tasks running in the 1384 kernel's address space are forced to use the same canary value for 1385 the entire duration that the system is up. 1386 1387 Enable this option to switch to a different method that uses a 1388 different canary value for each task. 1389 1390endmenu 1391 1392menu "Boot options" 1393 1394config USE_OF 1395 bool "Flattened Device Tree support" 1396 select IRQ_DOMAIN 1397 select OF 1398 help 1399 Include support for flattened device tree machine descriptions. 1400 1401config ARCH_WANT_FLAT_DTB_INSTALL 1402 def_bool y 1403 1404config ATAGS 1405 bool "Support for the traditional ATAGS boot data passing" 1406 depends on EXPERT 1407 help 1408 This is the traditional way of passing data to the kernel at 1409 boot but is now only used by a few of the oldest ARMv4 and 1410 ARMv5 machines. Users that still rely on ATAGS should plan 1411 on migrating to devicetree based booting. 1412 1413 Support for ATAGS will be removed when the last machine using 1414 it is either converted to DT or removed. 1415 1416config DEPRECATED_PARAM_STRUCT 1417 bool "Provide old way to pass kernel parameters (DEPRECATED)" 1418 depends on ATAGS 1419 help 1420 This was deprecated in 2001 and announced to live on for 5 years. 1421 It is now scheduled for removal in early 2027. 1422 1423# Compressed boot loader in ROM. Yes, we really want to ask about 1424# TEXT and BSS so we preserve their values in the config files. 1425config ZBOOT_ROM_TEXT 1426 hex "Compressed ROM boot loader base address" 1427 default 0x0 1428 help 1429 The physical address at which the ROM-able zImage is to be 1430 placed in the target. Platforms which normally make use of 1431 ROM-able zImage formats normally set this to a suitable 1432 value in their defconfig file. 1433 1434 If ZBOOT_ROM is not enabled, this has no effect. 1435 1436config ZBOOT_ROM_BSS 1437 hex "Compressed ROM boot loader BSS address" 1438 default 0x0 1439 help 1440 The base address of an area of read/write memory in the target 1441 for the ROM-able zImage which must be available while the 1442 decompressor is running. It must be large enough to hold the 1443 entire decompressed kernel plus an additional 128 KiB. 1444 Platforms which normally make use of ROM-able zImage formats 1445 normally set this to a suitable value in their defconfig file. 1446 1447 If ZBOOT_ROM is not enabled, this has no effect. 1448 1449config ZBOOT_ROM 1450 bool "Compressed boot loader in ROM/flash" 1451 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1452 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1453 help 1454 Say Y here if you intend to execute your compressed kernel image 1455 (zImage) directly from ROM or flash. If unsure, say N. 1456 1457config ARM_APPENDED_DTB 1458 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1459 depends on OF 1460 help 1461 With this option, the boot code will look for a device tree binary 1462 (DTB) appended to zImage 1463 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1464 1465 This is meant as a backward compatibility convenience for those 1466 systems with a bootloader that can't be upgraded to accommodate 1467 the documented boot protocol using a device tree. 1468 1469 Beware that there is very little in terms of protection against 1470 this option being confused by leftover garbage in memory that might 1471 look like a DTB header after a reboot if no actual DTB is appended 1472 to zImage. Do not leave this option active in a production kernel 1473 if you don't intend to always append a DTB. Proper passing of the 1474 location into r2 of a bootloader provided DTB is always preferable 1475 to this option. 1476 1477config ARM_ATAG_DTB_COMPAT 1478 bool "Supplement the appended DTB with traditional ATAG information" 1479 depends on ARM_APPENDED_DTB 1480 help 1481 Some old bootloaders can't be updated to a DTB capable one, yet 1482 they provide ATAGs with memory configuration, the ramdisk address, 1483 the kernel cmdline string, etc. Such information is dynamically 1484 provided by the bootloader and can't always be stored in a static 1485 DTB. To allow a device tree enabled kernel to be used with such 1486 bootloaders, this option allows zImage to extract the information 1487 from the ATAG list and store it at run time into the appended DTB. 1488 1489choice 1490 prompt "Kernel command line type" 1491 depends on ARM_ATAG_DTB_COMPAT 1492 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1493 1494config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1495 bool "Use bootloader kernel arguments if available" 1496 help 1497 Uses the command-line options passed by the boot loader instead of 1498 the device tree bootargs property. If the boot loader doesn't provide 1499 any, the device tree bootargs property will be used. 1500 1501config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1502 bool "Extend with bootloader kernel arguments" 1503 help 1504 The command-line arguments provided by the boot loader will be 1505 appended to the the device tree bootargs property. 1506 1507endchoice 1508 1509config CMDLINE 1510 string "Default kernel command string" 1511 default "" 1512 help 1513 On some architectures (e.g. CATS), there is currently no way 1514 for the boot loader to pass arguments to the kernel. For these 1515 architectures, you should supply some command-line options at build 1516 time by entering them here. As a minimum, you should specify the 1517 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1518 1519choice 1520 prompt "Kernel command line type" 1521 depends on CMDLINE != "" 1522 default CMDLINE_FROM_BOOTLOADER 1523 1524config CMDLINE_FROM_BOOTLOADER 1525 bool "Use bootloader kernel arguments if available" 1526 help 1527 Uses the command-line options passed by the boot loader. If 1528 the boot loader doesn't provide any, the default kernel command 1529 string provided in CMDLINE will be used. 1530 1531config CMDLINE_EXTEND 1532 bool "Extend bootloader kernel arguments" 1533 help 1534 The command-line arguments provided by the boot loader will be 1535 appended to the default kernel command string. 1536 1537config CMDLINE_FORCE 1538 bool "Always use the default kernel command string" 1539 help 1540 Always use the default kernel command string, even if the boot 1541 loader passes other arguments to the kernel. 1542 This is useful if you cannot or don't want to change the 1543 command-line options your boot loader passes to the kernel. 1544endchoice 1545 1546config XIP_KERNEL 1547 bool "Kernel Execute-In-Place from ROM" 1548 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1549 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1550 help 1551 Execute-In-Place allows the kernel to run from non-volatile storage 1552 directly addressable by the CPU, such as NOR flash. This saves RAM 1553 space since the text section of the kernel is not loaded from flash 1554 to RAM. Read-write sections, such as the data section and stack, 1555 are still copied to RAM. The XIP kernel is not compressed since 1556 it has to run directly from flash, so it will take more space to 1557 store it. The flash address used to link the kernel object files, 1558 and for storing it, is configuration dependent. Therefore, if you 1559 say Y here, you must know the proper physical address where to 1560 store the kernel image depending on your own flash memory usage. 1561 1562 Also note that the make target becomes "make xipImage" rather than 1563 "make zImage" or "make Image". The final kernel binary to put in 1564 ROM memory will be arch/arm/boot/xipImage. 1565 1566 If unsure, say N. 1567 1568config XIP_PHYS_ADDR 1569 hex "XIP Kernel Physical Location" 1570 depends on XIP_KERNEL 1571 default "0x00080000" 1572 help 1573 This is the physical address in your flash memory the kernel will 1574 be linked for and stored to. This address is dependent on your 1575 own flash usage. 1576 1577config XIP_DEFLATED_DATA 1578 bool "Store kernel .data section compressed in ROM" 1579 depends on XIP_KERNEL 1580 select ZLIB_INFLATE 1581 help 1582 Before the kernel is actually executed, its .data section has to be 1583 copied to RAM from ROM. This option allows for storing that data 1584 in compressed form and decompressed to RAM rather than merely being 1585 copied, saving some precious ROM space. A possible drawback is a 1586 slightly longer boot delay. 1587 1588config ARCH_SUPPORTS_KEXEC 1589 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1590 1591config ATAGS_PROC 1592 bool "Export atags in procfs" 1593 depends on ATAGS && KEXEC 1594 default y 1595 help 1596 Should the atags used to boot the kernel be exported in an "atags" 1597 file in procfs. Useful with kexec. 1598 1599config ARCH_SUPPORTS_CRASH_DUMP 1600 def_bool y 1601 1602config ARCH_DEFAULT_CRASH_DUMP 1603 def_bool y 1604 1605config AUTO_ZRELADDR 1606 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1607 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1608 help 1609 ZRELADDR is the physical address where the decompressed kernel 1610 image will be placed. If AUTO_ZRELADDR is selected, the address 1611 will be determined at run-time, either by masking the current IP 1612 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1613 This assumes the zImage being placed in the first 128MB from 1614 start of memory. 1615 1616config EFI_STUB 1617 bool 1618 1619config EFI 1620 bool "UEFI runtime support" 1621 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1622 select UCS2_STRING 1623 select EFI_PARAMS_FROM_FDT 1624 select EFI_STUB 1625 select EFI_GENERIC_STUB 1626 select EFI_RUNTIME_WRAPPERS 1627 help 1628 This option provides support for runtime services provided 1629 by UEFI firmware (such as non-volatile variables, realtime 1630 clock, and platform reset). A UEFI stub is also provided to 1631 allow the kernel to be booted as an EFI application. This 1632 is only useful for kernels that may run on systems that have 1633 UEFI firmware. 1634 1635config DMI 1636 bool "Enable support for SMBIOS (DMI) tables" 1637 depends on EFI 1638 default y 1639 help 1640 This enables SMBIOS/DMI feature for systems. 1641 1642 This option is only useful on systems that have UEFI firmware. 1643 However, even with this option, the resultant kernel should 1644 continue to boot on existing non-UEFI platforms. 1645 1646 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1647 i.e., the the practice of identifying the platform via DMI to 1648 decide whether certain workarounds for buggy hardware and/or 1649 firmware need to be enabled. This would require the DMI subsystem 1650 to be enabled much earlier than we do on ARM, which is non-trivial. 1651 1652endmenu 1653 1654menu "CPU Power Management" 1655 1656source "drivers/cpufreq/Kconfig" 1657 1658source "drivers/cpuidle/Kconfig" 1659 1660endmenu 1661 1662menu "Floating point emulation" 1663 1664comment "At least one emulation must be selected" 1665 1666config FPE_NWFPE 1667 bool "NWFPE math emulation (DEPRECATED)" 1668 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1669 help 1670 Say Y to include the NWFPE floating point emulator in the kernel. 1671 1672 This is only used on OABI userspace binaries, either using a 1673 pure OABI (!CONFIG_AEABI) kernel, or the OABI emulation. 1674 1675 Support for NWFPE will be removed in the future when OABI 1676 support is removed. 1677 1678config FPE_NWFPE_XP 1679 bool "Support extended precision" 1680 depends on FPE_NWFPE 1681 help 1682 Say Y to include 80-bit support in the kernel floating-point 1683 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1684 Note that gcc does not generate 80-bit operations by default, 1685 so in most cases this option only enlarges the size of the 1686 floating point emulator without any good reason. 1687 1688 You almost surely want to say N here. 1689 1690config FPE_FASTFPE 1691 bool "FastFPE math emulation (EXPERIMENTAL)" 1692 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1693 help 1694 Say Y here to include the FAST floating point emulator in the kernel. 1695 This is an experimental much faster emulator which now also has full 1696 precision for the mantissa. It does not support any exceptions. 1697 It is very simple, and approximately 3-6 times faster than NWFPE. 1698 1699 It should be sufficient for most programs. It may be not suitable 1700 for scientific calculations, but you have to check this for yourself. 1701 If you do not feel you need a faster FP emulation you should better 1702 choose NWFPE. 1703 1704config VFP 1705 bool "VFP-format floating point maths" 1706 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1707 help 1708 Say Y to include VFP support code in the kernel. This is needed 1709 if your hardware includes a VFP unit. 1710 1711 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1712 release notes and additional status information. 1713 1714 Say N if your target does not have VFP hardware. 1715 1716config VFPv3 1717 bool 1718 depends on VFP 1719 default y if CPU_V7 1720 1721config NEON 1722 bool "Advanced SIMD (NEON) Extension support" 1723 depends on VFPv3 && CPU_V7 1724 help 1725 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1726 Extension. 1727 1728config KERNEL_MODE_NEON 1729 bool "Support for NEON in kernel mode" 1730 depends on NEON && AEABI 1731 help 1732 Say Y to include support for NEON in kernel mode. 1733 1734endmenu 1735 1736config ARCH_CC_CAN_LINK 1737 bool 1738 default $(cc_can_link_user,-mlittle-endian) if CPU_LITTLE_ENDIAN 1739 default $(cc_can_link_user,-mbig-endian -mbe8) if CPU_ENDIAN_BE8 1740 default $(cc_can_link_user,-mbig-endian -mbe32) if CPU_ENDIAN_BE32 1741 1742config ARCH_USERFLAGS 1743 string 1744 default "-mlittle-endian" if CPU_LITTLE_ENDIAN 1745 default "-mbig-endian -mbe8" if CPU_ENDIAN_BE8 1746 default "-mbig-endian -mbe32" if CPU_ENDIAN_BE32 1747 1748menu "Power management options" 1749 1750source "kernel/power/Kconfig" 1751 1752config ARCH_SUSPEND_POSSIBLE 1753 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1754 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1755 def_bool y 1756 1757config ARM_CPU_SUSPEND 1758 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1759 depends on ARCH_SUSPEND_POSSIBLE 1760 1761config ARCH_HIBERNATION_POSSIBLE 1762 bool 1763 depends on MMU 1764 default y if ARCH_SUSPEND_POSSIBLE 1765 1766endmenu 1767