1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_trace.h" 8 #include "intel_display_types.h" 9 #include "intel_dp_aux.h" 10 #include "intel_pps.h" 11 #include "intel_tc.h" 12 13 static u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 14 { 15 int i; 16 u32 v = 0; 17 18 if (src_bytes > 4) 19 src_bytes = 4; 20 for (i = 0; i < src_bytes; i++) 21 v |= ((u32)src[i]) << ((3 - i) * 8); 22 return v; 23 } 24 25 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 26 { 27 int i; 28 29 if (dst_bytes > 4) 30 dst_bytes = 4; 31 for (i = 0; i < dst_bytes; i++) 32 dst[i] = src >> ((3 - i) * 8); 33 } 34 35 static u32 36 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 37 { 38 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 39 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 40 const unsigned int timeout_ms = 10; 41 u32 status; 42 bool done; 43 44 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 45 done = wait_event_timeout(i915->display.gmbus.wait_queue, C, 46 msecs_to_jiffies_timeout(timeout_ms)); 47 48 /* just trace the final value */ 49 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 50 51 if (!done) 52 drm_err(&i915->drm, 53 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 54 intel_dp->aux.name, timeout_ms, status); 55 #undef C 56 57 return status; 58 } 59 60 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 61 { 62 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 63 64 if (index) 65 return 0; 66 67 /* 68 * The clock divider is based off the hrawclk, and would like to run at 69 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 70 */ 71 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 72 } 73 74 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 75 { 76 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 77 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 78 u32 freq; 79 80 if (index) 81 return 0; 82 83 /* 84 * The clock divider is based off the cdclk or PCH rawclk, and would 85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 86 * divide by 2000 and use that 87 */ 88 if (dig_port->aux_ch == AUX_CH_A) 89 freq = dev_priv->display.cdclk.hw.cdclk; 90 else 91 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 92 return DIV_ROUND_CLOSEST(freq, 2000); 93 } 94 95 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 96 { 97 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 98 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 99 100 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 101 /* Workaround for non-ULT HSW */ 102 switch (index) { 103 case 0: return 63; 104 case 1: return 72; 105 default: return 0; 106 } 107 } 108 109 return ilk_get_aux_clock_divider(intel_dp, index); 110 } 111 112 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 113 { 114 /* 115 * SKL doesn't need us to program the AUX clock divider (Hardware will 116 * derive the clock from CDCLK automatically). We still implement the 117 * get_aux_clock_divider vfunc to plug-in into the existing code. 118 */ 119 return index ? 0 : 1; 120 } 121 122 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 123 int send_bytes, 124 u32 aux_clock_divider) 125 { 126 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 127 struct drm_i915_private *dev_priv = 128 to_i915(dig_port->base.base.dev); 129 u32 timeout; 130 131 /* Max timeout value on G4x-BDW: 1.6ms */ 132 if (IS_BROADWELL(dev_priv)) 133 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 134 else 135 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 136 137 return DP_AUX_CH_CTL_SEND_BUSY | 138 DP_AUX_CH_CTL_DONE | 139 DP_AUX_CH_CTL_INTERRUPT | 140 DP_AUX_CH_CTL_TIME_OUT_ERROR | 141 timeout | 142 DP_AUX_CH_CTL_RECEIVE_ERROR | 143 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 144 (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 145 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 146 } 147 148 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 149 int send_bytes, 150 u32 unused) 151 { 152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 153 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 154 u32 ret; 155 156 /* 157 * Max timeout values: 158 * SKL-GLK: 1.6ms 159 * ICL+: 4ms 160 */ 161 ret = DP_AUX_CH_CTL_SEND_BUSY | 162 DP_AUX_CH_CTL_DONE | 163 DP_AUX_CH_CTL_INTERRUPT | 164 DP_AUX_CH_CTL_TIME_OUT_ERROR | 165 DP_AUX_CH_CTL_TIME_OUT_MAX | 166 DP_AUX_CH_CTL_RECEIVE_ERROR | 167 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 168 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 169 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 170 171 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 172 ret |= DP_AUX_CH_CTL_TBT_IO; 173 174 /* 175 * Power request bit is already set during aux power well enable. 176 * Preserve the bit across aux transactions. 177 */ 178 if (DISPLAY_VER(i915) >= 14) 179 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 180 181 return ret; 182 } 183 184 static int 185 intel_dp_aux_xfer(struct intel_dp *intel_dp, 186 const u8 *send, int send_bytes, 187 u8 *recv, int recv_size, 188 u32 aux_send_ctl_flags) 189 { 190 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 191 struct drm_i915_private *i915 = 192 to_i915(dig_port->base.base.dev); 193 struct intel_uncore *uncore = &i915->uncore; 194 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 195 bool is_tc_port = intel_phy_is_tc(i915, phy); 196 i915_reg_t ch_ctl, ch_data[5]; 197 u32 aux_clock_divider; 198 enum intel_display_power_domain aux_domain; 199 intel_wakeref_t aux_wakeref; 200 intel_wakeref_t pps_wakeref; 201 int i, ret, recv_bytes; 202 int try, clock = 0; 203 u32 status; 204 bool vdd; 205 206 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 207 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 208 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 209 210 if (is_tc_port) 211 intel_tc_port_lock(dig_port); 212 213 aux_domain = intel_aux_power_domain(dig_port); 214 215 aux_wakeref = intel_display_power_get(i915, aux_domain); 216 pps_wakeref = intel_pps_lock(intel_dp); 217 218 /* 219 * We will be called with VDD already enabled for dpcd/edid/oui reads. 220 * In such cases we want to leave VDD enabled and it's up to upper layers 221 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 222 * ourselves. 223 */ 224 vdd = intel_pps_vdd_on_unlocked(intel_dp); 225 226 /* 227 * dp aux is extremely sensitive to irq latency, hence request the 228 * lowest possible wakeup latency and so prevent the cpu from going into 229 * deep sleep states. 230 */ 231 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 232 233 intel_pps_check_power_unlocked(intel_dp); 234 235 /* Try to wait for any previous AUX channel activity */ 236 for (try = 0; try < 3; try++) { 237 status = intel_uncore_read_notrace(uncore, ch_ctl); 238 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 239 break; 240 msleep(1); 241 } 242 /* just trace the final value */ 243 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 244 245 if (try == 3) { 246 const u32 status = intel_uncore_read(uncore, ch_ctl); 247 248 if (status != intel_dp->aux_busy_last_status) { 249 drm_WARN(&i915->drm, 1, 250 "%s: not started (status 0x%08x)\n", 251 intel_dp->aux.name, status); 252 intel_dp->aux_busy_last_status = status; 253 } 254 255 ret = -EBUSY; 256 goto out; 257 } 258 259 /* Only 5 data registers! */ 260 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 261 ret = -E2BIG; 262 goto out; 263 } 264 265 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 266 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 267 send_bytes, 268 aux_clock_divider); 269 270 send_ctl |= aux_send_ctl_flags; 271 272 /* Must try at least 3 times according to DP spec */ 273 for (try = 0; try < 5; try++) { 274 /* Load the send data into the aux channel data registers */ 275 for (i = 0; i < send_bytes; i += 4) 276 intel_uncore_write(uncore, 277 ch_data[i >> 2], 278 intel_dp_aux_pack(send + i, 279 send_bytes - i)); 280 281 /* Send the command and wait for it to complete */ 282 intel_uncore_write(uncore, ch_ctl, send_ctl); 283 284 status = intel_dp_aux_wait_done(intel_dp); 285 286 /* Clear done status and any errors */ 287 intel_uncore_write(uncore, 288 ch_ctl, 289 status | 290 DP_AUX_CH_CTL_DONE | 291 DP_AUX_CH_CTL_TIME_OUT_ERROR | 292 DP_AUX_CH_CTL_RECEIVE_ERROR); 293 294 /* 295 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 296 * 400us delay required for errors and timeouts 297 * Timeout errors from the HW already meet this 298 * requirement so skip to next iteration 299 */ 300 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 301 continue; 302 303 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 304 usleep_range(400, 500); 305 continue; 306 } 307 if (status & DP_AUX_CH_CTL_DONE) 308 goto done; 309 } 310 } 311 312 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 313 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 314 intel_dp->aux.name, status); 315 ret = -EBUSY; 316 goto out; 317 } 318 319 done: 320 /* 321 * Check for timeout or receive error. Timeouts occur when the sink is 322 * not connected. 323 */ 324 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 325 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 326 intel_dp->aux.name, status); 327 ret = -EIO; 328 goto out; 329 } 330 331 /* 332 * Timeouts occur when the device isn't connected, so they're "normal" 333 * -- don't fill the kernel log with these 334 */ 335 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 336 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 337 intel_dp->aux.name, status); 338 ret = -ETIMEDOUT; 339 goto out; 340 } 341 342 /* Unload any bytes sent back from the other side */ 343 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 344 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 345 346 /* 347 * By BSpec: "Message sizes of 0 or >20 are not allowed." 348 * We have no idea of what happened so we return -EBUSY so 349 * drm layer takes care for the necessary retries. 350 */ 351 if (recv_bytes == 0 || recv_bytes > 20) { 352 drm_dbg_kms(&i915->drm, 353 "%s: Forbidden recv_bytes = %d on aux transaction\n", 354 intel_dp->aux.name, recv_bytes); 355 ret = -EBUSY; 356 goto out; 357 } 358 359 if (recv_bytes > recv_size) 360 recv_bytes = recv_size; 361 362 for (i = 0; i < recv_bytes; i += 4) 363 intel_dp_aux_unpack(intel_uncore_read(uncore, ch_data[i >> 2]), 364 recv + i, recv_bytes - i); 365 366 ret = recv_bytes; 367 out: 368 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 369 370 if (vdd) 371 intel_pps_vdd_off_unlocked(intel_dp, false); 372 373 intel_pps_unlock(intel_dp, pps_wakeref); 374 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 375 376 if (is_tc_port) 377 intel_tc_port_unlock(dig_port); 378 379 return ret; 380 } 381 382 #define BARE_ADDRESS_SIZE 3 383 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 384 385 static void 386 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 387 const struct drm_dp_aux_msg *msg) 388 { 389 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 390 txbuf[1] = (msg->address >> 8) & 0xff; 391 txbuf[2] = msg->address & 0xff; 392 txbuf[3] = msg->size - 1; 393 } 394 395 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 396 { 397 /* 398 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 399 * select bit to inform the hardware to send the Aksv after our header 400 * since we can't access that data from software. 401 */ 402 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 403 msg->address == DP_AUX_HDCP_AKSV) 404 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 405 406 return 0; 407 } 408 409 static ssize_t 410 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 411 { 412 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 413 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 414 u8 txbuf[20], rxbuf[20]; 415 size_t txsize, rxsize; 416 u32 flags = intel_dp_aux_xfer_flags(msg); 417 int ret; 418 419 intel_dp_aux_header(txbuf, msg); 420 421 switch (msg->request & ~DP_AUX_I2C_MOT) { 422 case DP_AUX_NATIVE_WRITE: 423 case DP_AUX_I2C_WRITE: 424 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 425 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 426 rxsize = 2; /* 0 or 1 data bytes */ 427 428 if (drm_WARN_ON(&i915->drm, txsize > 20)) 429 return -E2BIG; 430 431 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 432 433 if (msg->buffer) 434 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 435 436 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 437 rxbuf, rxsize, flags); 438 if (ret > 0) { 439 msg->reply = rxbuf[0] >> 4; 440 441 if (ret > 1) { 442 /* Number of bytes written in a short write. */ 443 ret = clamp_t(int, rxbuf[1], 0, msg->size); 444 } else { 445 /* Return payload size. */ 446 ret = msg->size; 447 } 448 } 449 break; 450 451 case DP_AUX_NATIVE_READ: 452 case DP_AUX_I2C_READ: 453 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 454 rxsize = msg->size + 1; 455 456 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 457 return -E2BIG; 458 459 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 460 rxbuf, rxsize, flags); 461 if (ret > 0) { 462 msg->reply = rxbuf[0] >> 4; 463 /* 464 * Assume happy day, and copy the data. The caller is 465 * expected to check msg->reply before touching it. 466 * 467 * Return payload size. 468 */ 469 ret--; 470 memcpy(msg->buffer, rxbuf + 1, ret); 471 } 472 break; 473 474 default: 475 ret = -EINVAL; 476 break; 477 } 478 479 return ret; 480 } 481 482 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 483 { 484 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 485 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 486 enum aux_ch aux_ch = dig_port->aux_ch; 487 488 switch (aux_ch) { 489 case AUX_CH_B: 490 case AUX_CH_C: 491 case AUX_CH_D: 492 return DP_AUX_CH_CTL(aux_ch); 493 default: 494 MISSING_CASE(aux_ch); 495 return DP_AUX_CH_CTL(AUX_CH_B); 496 } 497 } 498 499 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 500 { 501 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 502 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 503 enum aux_ch aux_ch = dig_port->aux_ch; 504 505 switch (aux_ch) { 506 case AUX_CH_B: 507 case AUX_CH_C: 508 case AUX_CH_D: 509 return DP_AUX_CH_DATA(aux_ch, index); 510 default: 511 MISSING_CASE(aux_ch); 512 return DP_AUX_CH_DATA(AUX_CH_B, index); 513 } 514 } 515 516 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 517 { 518 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 519 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 520 enum aux_ch aux_ch = dig_port->aux_ch; 521 522 switch (aux_ch) { 523 case AUX_CH_A: 524 return DP_AUX_CH_CTL(aux_ch); 525 case AUX_CH_B: 526 case AUX_CH_C: 527 case AUX_CH_D: 528 return PCH_DP_AUX_CH_CTL(aux_ch); 529 default: 530 MISSING_CASE(aux_ch); 531 return DP_AUX_CH_CTL(AUX_CH_A); 532 } 533 } 534 535 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 536 { 537 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 538 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 539 enum aux_ch aux_ch = dig_port->aux_ch; 540 541 switch (aux_ch) { 542 case AUX_CH_A: 543 return DP_AUX_CH_DATA(aux_ch, index); 544 case AUX_CH_B: 545 case AUX_CH_C: 546 case AUX_CH_D: 547 return PCH_DP_AUX_CH_DATA(aux_ch, index); 548 default: 549 MISSING_CASE(aux_ch); 550 return DP_AUX_CH_DATA(AUX_CH_A, index); 551 } 552 } 553 554 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 555 { 556 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 557 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 558 enum aux_ch aux_ch = dig_port->aux_ch; 559 560 switch (aux_ch) { 561 case AUX_CH_A: 562 case AUX_CH_B: 563 case AUX_CH_C: 564 case AUX_CH_D: 565 case AUX_CH_E: 566 case AUX_CH_F: 567 return DP_AUX_CH_CTL(aux_ch); 568 default: 569 MISSING_CASE(aux_ch); 570 return DP_AUX_CH_CTL(AUX_CH_A); 571 } 572 } 573 574 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 575 { 576 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 577 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 578 enum aux_ch aux_ch = dig_port->aux_ch; 579 580 switch (aux_ch) { 581 case AUX_CH_A: 582 case AUX_CH_B: 583 case AUX_CH_C: 584 case AUX_CH_D: 585 case AUX_CH_E: 586 case AUX_CH_F: 587 return DP_AUX_CH_DATA(aux_ch, index); 588 default: 589 MISSING_CASE(aux_ch); 590 return DP_AUX_CH_DATA(AUX_CH_A, index); 591 } 592 } 593 594 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 595 { 596 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 597 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 598 enum aux_ch aux_ch = dig_port->aux_ch; 599 600 switch (aux_ch) { 601 case AUX_CH_A: 602 case AUX_CH_B: 603 case AUX_CH_C: 604 case AUX_CH_USBC1: 605 case AUX_CH_USBC2: 606 case AUX_CH_USBC3: 607 case AUX_CH_USBC4: 608 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 609 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 610 return DP_AUX_CH_CTL(aux_ch); 611 default: 612 MISSING_CASE(aux_ch); 613 return DP_AUX_CH_CTL(AUX_CH_A); 614 } 615 } 616 617 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 618 { 619 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 620 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 621 enum aux_ch aux_ch = dig_port->aux_ch; 622 623 switch (aux_ch) { 624 case AUX_CH_A: 625 case AUX_CH_B: 626 case AUX_CH_C: 627 case AUX_CH_USBC1: 628 case AUX_CH_USBC2: 629 case AUX_CH_USBC3: 630 case AUX_CH_USBC4: 631 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 632 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 633 return DP_AUX_CH_DATA(aux_ch, index); 634 default: 635 MISSING_CASE(aux_ch); 636 return DP_AUX_CH_DATA(AUX_CH_A, index); 637 } 638 } 639 640 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 641 { 642 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 643 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 644 enum aux_ch aux_ch = dig_port->aux_ch; 645 646 switch (aux_ch) { 647 case AUX_CH_A: 648 case AUX_CH_B: 649 case AUX_CH_USBC1: 650 case AUX_CH_USBC2: 651 case AUX_CH_USBC3: 652 case AUX_CH_USBC4: 653 return XELPDP_DP_AUX_CH_CTL(aux_ch); 654 default: 655 MISSING_CASE(aux_ch); 656 return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); 657 } 658 } 659 660 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 661 { 662 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 663 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 664 enum aux_ch aux_ch = dig_port->aux_ch; 665 666 switch (aux_ch) { 667 case AUX_CH_A: 668 case AUX_CH_B: 669 case AUX_CH_USBC1: 670 case AUX_CH_USBC2: 671 case AUX_CH_USBC3: 672 case AUX_CH_USBC4: 673 return XELPDP_DP_AUX_CH_DATA(aux_ch, index); 674 default: 675 MISSING_CASE(aux_ch); 676 return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); 677 } 678 } 679 680 void intel_dp_aux_fini(struct intel_dp *intel_dp) 681 { 682 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 683 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 684 685 kfree(intel_dp->aux.name); 686 } 687 688 void intel_dp_aux_init(struct intel_dp *intel_dp) 689 { 690 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 691 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 692 struct intel_encoder *encoder = &dig_port->base; 693 enum aux_ch aux_ch = dig_port->aux_ch; 694 695 if (DISPLAY_VER(dev_priv) >= 14) { 696 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 697 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 698 } else if (DISPLAY_VER(dev_priv) >= 12) { 699 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 700 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 701 } else if (DISPLAY_VER(dev_priv) >= 9) { 702 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 703 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 704 } else if (HAS_PCH_SPLIT(dev_priv)) { 705 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 706 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 707 } else { 708 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 709 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 710 } 711 712 if (DISPLAY_VER(dev_priv) >= 9) 713 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 714 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 715 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 716 else if (HAS_PCH_SPLIT(dev_priv)) 717 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 718 else 719 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 720 721 if (DISPLAY_VER(dev_priv) >= 9) 722 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 723 else 724 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 725 726 intel_dp->aux.drm_dev = &dev_priv->drm; 727 drm_dp_aux_init(&intel_dp->aux); 728 729 /* Failure to allocate our preferred name is not critical */ 730 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) 731 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 732 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D), 733 encoder->base.name); 734 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 735 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 736 aux_ch - AUX_CH_USBC1 + '1', 737 encoder->base.name); 738 else 739 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 740 aux_ch_name(aux_ch), 741 encoder->base.name); 742 743 intel_dp->aux.transfer = intel_dp_aux_transfer; 744 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 745 } 746