1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAuto v9 SoC device tree source 4 * 5 * Copyright (c) 2021 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov9.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,boot-mode.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "samsung,exynosautov9"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_alive; 23 pinctrl1 = &pinctrl_aud; 24 pinctrl2 = &pinctrl_fsys0; 25 pinctrl3 = &pinctrl_fsys1; 26 pinctrl4 = &pinctrl_fsys2; 27 pinctrl5 = &pinctrl_peric0; 28 pinctrl6 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a76-pmu"; 33 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 41 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 42 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a76"; 84 reg = <0x0>; 85 enable-method = "psci"; 86 }; 87 88 cpu1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a76"; 91 reg = <0x100>; 92 enable-method = "psci"; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a76"; 98 reg = <0x200>; 99 enable-method = "psci"; 100 }; 101 102 cpu3: cpu@300 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x300>; 106 enable-method = "psci"; 107 }; 108 109 cpu4: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a76"; 112 reg = <0x10000>; 113 enable-method = "psci"; 114 }; 115 116 cpu5: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a76"; 119 reg = <0x10100>; 120 enable-method = "psci"; 121 }; 122 123 cpu6: cpu@10200 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a76"; 126 reg = <0x10200>; 127 enable-method = "psci"; 128 }; 129 130 cpu7: cpu@10300 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a76"; 133 reg = <0x10300>; 134 enable-method = "psci"; 135 }; 136 }; 137 138 psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 cpu_suspend = <0xc4000001>; 142 cpu_off = <0x84000002>; 143 cpu_on = <0xc4000003>; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 152 }; 153 154 fixed-rate-clocks { 155 xtcxo: clock { 156 compatible = "fixed-clock"; 157 #clock-cells = <0>; 158 clock-output-names = "oscclk"; 159 }; 160 }; 161 162 soc: soc@0 { 163 compatible = "simple-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges = <0x0 0x0 0x0 0x20000000>; 167 168 chipid@10000000 { 169 compatible = "samsung,exynosautov9-chipid", 170 "samsung,exynos850-chipid"; 171 reg = <0x10000000 0x24>; 172 }; 173 174 cmu_peris: clock-controller@10020000 { 175 compatible = "samsung,exynosautov9-cmu-peris"; 176 reg = <0x10020000 0x8000>; 177 #clock-cells = <1>; 178 179 clocks = <&xtcxo>, 180 <&cmu_top DOUT_CLKCMU_PERIS_BUS>; 181 clock-names = "oscclk", 182 "dout_clkcmu_peris_bus"; 183 }; 184 185 cmu_peric0: clock-controller@10200000 { 186 compatible = "samsung,exynosautov9-cmu-peric0"; 187 reg = <0x10200000 0x8000>; 188 #clock-cells = <1>; 189 190 clocks = <&xtcxo>, 191 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, 192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 193 clock-names = "oscclk", 194 "dout_clkcmu_peric0_bus", 195 "dout_clkcmu_peric0_ip"; 196 }; 197 198 cmu_peric1: clock-controller@10800000 { 199 compatible = "samsung,exynosautov9-cmu-peric1"; 200 reg = <0x10800000 0x8000>; 201 #clock-cells = <1>; 202 203 clocks = <&xtcxo>, 204 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, 205 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 206 clock-names = "oscclk", 207 "dout_clkcmu_peric1_bus", 208 "dout_clkcmu_peric1_ip"; 209 }; 210 211 cmu_fsys1: clock-controller@17040000 { 212 compatible = "samsung,exynosautov9-cmu-fsys1"; 213 reg = <0x17040000 0x8000>; 214 #clock-cells = <1>; 215 216 clocks = <&xtcxo>, 217 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>, 218 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>, 219 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>; 220 clock-names = "oscclk", 221 "dout_clkcmu_fsys1_bus", 222 "gout_clkcmu_fsys1_mmc_card", 223 "dout_clkcmu_fsys1_usbdrd"; 224 }; 225 226 cmu_fsys0: clock-controller@17700000 { 227 compatible = "samsung,exynosautov9-cmu-fsys0"; 228 reg = <0x17700000 0x8000>; 229 #clock-cells = <1>; 230 231 clocks = <&xtcxo>, 232 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>, 233 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>; 234 clock-names = "oscclk", 235 "dout_clkcmu_fsys0_bus", 236 "dout_clkcmu_fsys0_pcie"; 237 }; 238 239 cmu_fsys2: clock-controller@17c00000 { 240 compatible = "samsung,exynosautov9-cmu-fsys2"; 241 reg = <0x17c00000 0x8000>; 242 #clock-cells = <1>; 243 244 clocks = <&xtcxo>, 245 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, 246 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, 247 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; 248 clock-names = "oscclk", 249 "dout_clkcmu_fsys2_bus", 250 "dout_fsys2_clkcmu_ufs_embd", 251 "dout_fsys2_clkcmu_ethernet"; 252 }; 253 254 cmu_core: clock-controller@1b030000 { 255 compatible = "samsung,exynosautov9-cmu-core"; 256 reg = <0x1b030000 0x8000>; 257 #clock-cells = <1>; 258 259 clocks = <&xtcxo>, 260 <&cmu_top DOUT_CLKCMU_CORE_BUS>; 261 clock-names = "oscclk", 262 "dout_clkcmu_core_bus"; 263 }; 264 265 cmu_busmc: clock-controller@1b200000 { 266 compatible = "samsung,exynosautov9-cmu-busmc"; 267 reg = <0x1b200000 0x8000>; 268 #clock-cells = <1>; 269 270 clocks = <&xtcxo>, 271 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; 272 clock-names = "oscclk", 273 "dout_clkcmu_busmc_bus"; 274 }; 275 276 cmu_top: clock-controller@1b240000 { 277 compatible = "samsung,exynosautov9-cmu-top"; 278 reg = <0x1b240000 0x8000>; 279 #clock-cells = <1>; 280 281 clocks = <&xtcxo>; 282 clock-names = "oscclk"; 283 }; 284 285 gic: interrupt-controller@10101000 { 286 compatible = "arm,gic-400"; 287 #interrupt-cells = <3>; 288 #address-cells = <0>; 289 interrupt-controller; 290 reg = <0x10101000 0x1000>, 291 <0x10102000 0x2000>, 292 <0x10104000 0x2000>, 293 <0x10106000 0x2000>; 294 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 295 IRQ_TYPE_LEVEL_HIGH)>; 296 }; 297 298 pdma0: dma-controller@1b2e0000 { 299 compatible = "arm,pl330", "arm,primecell"; 300 reg = <0x1b2e0000 0x1000>; 301 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>; 303 clock-names = "apb_pclk"; 304 arm,pl330-broken-no-flushp; 305 #dma-cells = <1>; 306 }; 307 308 pinctrl_alive: pinctrl@10450000 { 309 compatible = "samsung,exynosautov9-pinctrl"; 310 reg = <0x10450000 0x1000>; 311 312 wakeup-interrupt-controller { 313 compatible = "samsung,exynosautov9-wakeup-eint", 314 "samsung,exynos850-wakeup-eint", 315 "samsung,exynos7-wakeup-eint"; 316 }; 317 }; 318 319 pinctrl_aud: pinctrl@19c60000 { 320 compatible = "samsung,exynosautov9-pinctrl"; 321 reg = <0x19c60000 0x1000>; 322 }; 323 324 pinctrl_fsys0: pinctrl@17740000 { 325 compatible = "samsung,exynosautov9-pinctrl"; 326 reg = <0x17740000 0x1000>; 327 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 328 }; 329 330 pinctrl_fsys1: pinctrl@17060000 { 331 compatible = "samsung,exynosautov9-pinctrl"; 332 reg = <0x17060000 0x1000>; 333 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 336 pinctrl_fsys2: pinctrl@17c30000 { 337 compatible = "samsung,exynosautov9-pinctrl"; 338 reg = <0x17c30000 0x1000>; 339 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 340 }; 341 342 pinctrl_peric0: pinctrl@10230000 { 343 compatible = "samsung,exynosautov9-pinctrl"; 344 reg = <0x10230000 0x1000>; 345 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 346 }; 347 348 pinctrl_peric1: pinctrl@10830000 { 349 compatible = "samsung,exynosautov9-pinctrl"; 350 reg = <0x10830000 0x1000>; 351 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 352 }; 353 354 pmu_system_controller: system-controller@10460000 { 355 compatible = "samsung,exynosautov9-pmu", 356 "samsung,exynos7-pmu", "syscon"; 357 reg = <0x10460000 0x10000>; 358 359 reboot: syscon-reboot { 360 compatible = "syscon-reboot"; 361 regmap = <&pmu_system_controller>; 362 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 363 value = <0x2>; 364 mask = <0x2>; 365 }; 366 367 reboot-mode { 368 compatible = "syscon-reboot-mode"; 369 offset = <0x810>; /* SYSIP_DAT0 */ 370 mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>; 371 mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>; 372 mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>; 373 }; 374 }; 375 376 syscon_fsys2: syscon@17c20000 { 377 compatible = "samsung,exynosautov9-fsys2-sysreg", 378 "samsung,exynosautov9-sysreg", "syscon"; 379 reg = <0x17c20000 0x1000>; 380 }; 381 382 syscon_peric0: syscon@10220000 { 383 compatible = "samsung,exynosautov9-peric0-sysreg", 384 "samsung,exynosautov9-sysreg", "syscon"; 385 reg = <0x10220000 0x2000>; 386 }; 387 388 syscon_peric1: syscon@10820000 { 389 compatible = "samsung,exynosautov9-peric1-sysreg", 390 "samsung,exynosautov9-sysreg", "syscon"; 391 reg = <0x10820000 0x2000>; 392 }; 393 394 usi_0: usi@103000c0 { 395 compatible = "samsung,exynosautov9-usi", 396 "samsung,exynos850-usi"; 397 reg = <0x103000c0 0x20>; 398 samsung,sysreg = <&syscon_peric0 0x1000>; 399 samsung,mode = <USI_V2_UART>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges; 403 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 404 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 405 clock-names = "pclk", "ipclk"; 406 status = "disabled"; 407 408 serial_0: serial@10300000 { 409 compatible = "samsung,exynosautov9-uart", 410 "samsung,exynos850-uart"; 411 reg = <0x10300000 0xc0>; 412 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&uart0_bus>; 415 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 416 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 417 clock-names = "uart", "clk_uart_baud0"; 418 samsung,uart-fifosize = <256>; 419 status = "disabled"; 420 }; 421 422 spi_0: spi@10300000 { 423 compatible = "samsung,exynosautov9-spi"; 424 reg = <0x10300000 0x30>; 425 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&spi0_bus &spi0_cs_func>; 428 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 429 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>, 430 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 431 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 432 samsung,spi-src-clk = <0>; 433 dmas = <&pdma0 1>, <&pdma0 0>; 434 dma-names = "tx", "rx"; 435 num-cs = <1>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 fifo-depth = <256>; 439 status = "disabled"; 440 }; 441 442 hsi2c_0: i2c@10300000 { 443 compatible = "samsung,exynosautov9-hsi2c"; 444 reg = <0x10300000 0xc0>; 445 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&hsi2c0_bus>; 448 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 449 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 450 clock-names = "hsi2c", "hsi2c_pclk"; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 status = "disabled"; 454 }; 455 }; 456 457 usi_i2c_0: usi@103100c0 { 458 compatible = "samsung,exynosautov9-usi", 459 "samsung,exynos850-usi"; 460 reg = <0x103100c0 0x20>; 461 samsung,sysreg = <&syscon_peric0 0x1004>; 462 samsung,mode = <USI_V2_I2C>; 463 #address-cells = <1>; 464 #size-cells = <1>; 465 ranges; 466 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>, 467 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>; 468 clock-names = "pclk", "ipclk"; 469 status = "disabled"; 470 471 hsi2c_1: i2c@10310000 { 472 compatible = "samsung,exynosautov9-hsi2c"; 473 reg = <0x10310000 0xc0>; 474 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&hsi2c1_bus>; 477 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>, 478 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>; 479 clock-names = "hsi2c", "hsi2c_pclk"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 }; 485 486 usi_1: usi@103200c0 { 487 compatible = "samsung,exynosautov9-usi", 488 "samsung,exynos850-usi"; 489 reg = <0x103200c0 0x20>; 490 samsung,sysreg = <&syscon_peric0 0x1008>; 491 samsung,mode = <USI_V2_UART>; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 ranges; 495 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 496 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 497 clock-names = "pclk", "ipclk"; 498 status = "disabled"; 499 500 serial_1: serial@10320000 { 501 compatible = "samsung,exynosautov9-uart", 502 "samsung,exynos850-uart"; 503 reg = <0x10320000 0xc0>; 504 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&uart1_bus>; 507 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 508 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 509 clock-names = "uart", "clk_uart_baud0"; 510 samsung,uart-fifosize = <256>; 511 status = "disabled"; 512 }; 513 514 spi_1: spi@10320000 { 515 compatible = "samsung,exynosautov9-spi"; 516 reg = <0x10320000 0x30>; 517 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&spi1_bus &spi1_cs_func>; 520 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 521 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>, 522 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 523 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 524 samsung,spi-src-clk = <0>; 525 dmas = <&pdma0 3>, <&pdma0 2>; 526 dma-names = "tx", "rx"; 527 num-cs = <1>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 fifo-depth = <256>; 531 status = "disabled"; 532 }; 533 534 hsi2c_2: i2c@10320000 { 535 compatible = "samsung,exynosautov9-hsi2c"; 536 reg = <0x10320000 0xc0>; 537 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&hsi2c2_bus>; 540 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 541 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 542 clock-names = "hsi2c", "hsi2c_pclk"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 status = "disabled"; 546 }; 547 }; 548 549 usi_i2c_1: usi@103300c0 { 550 compatible = "samsung,exynosautov9-usi", 551 "samsung,exynos850-usi"; 552 reg = <0x103300c0 0x20>; 553 samsung,sysreg = <&syscon_peric0 0x100c>; 554 samsung,mode = <USI_V2_I2C>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges; 558 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>, 559 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>; 560 clock-names = "pclk", "ipclk"; 561 status = "disabled"; 562 563 hsi2c_3: i2c@10330000 { 564 compatible = "samsung,exynosautov9-hsi2c"; 565 reg = <0x10330000 0xc0>; 566 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&hsi2c3_bus>; 569 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>, 570 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>; 571 clock-names = "hsi2c", "hsi2c_pclk"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 status = "disabled"; 575 }; 576 }; 577 578 usi_2: usi@103400c0 { 579 compatible = "samsung,exynosautov9-usi", 580 "samsung,exynos850-usi"; 581 reg = <0x103400c0 0x20>; 582 samsung,sysreg = <&syscon_peric0 0x1010>; 583 samsung,mode = <USI_V2_UART>; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 ranges; 587 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 588 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 589 clock-names = "pclk", "ipclk"; 590 status = "disabled"; 591 592 serial_2: serial@10340000 { 593 compatible = "samsung,exynosautov9-uart", 594 "samsung,exynos850-uart"; 595 reg = <0x10340000 0xc0>; 596 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&uart2_bus>; 599 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 600 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 601 clock-names = "uart", "clk_uart_baud0"; 602 samsung,uart-fifosize = <64>; 603 status = "disabled"; 604 }; 605 606 spi_2: spi@10340000 { 607 compatible = "samsung,exynosautov9-spi"; 608 reg = <0x10340000 0x30>; 609 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&spi2_bus &spi2_cs_func>; 612 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 613 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>, 614 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 615 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 616 samsung,spi-src-clk = <0>; 617 dmas = <&pdma0 5>, <&pdma0 4>; 618 dma-names = "tx", "rx"; 619 num-cs = <1>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 fifo-depth = <64>; 623 status = "disabled"; 624 }; 625 626 hsi2c_4: i2c@10340000 { 627 compatible = "samsung,exynosautov9-hsi2c"; 628 reg = <0x10340000 0xc0>; 629 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&hsi2c4_bus>; 632 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 633 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 634 clock-names = "hsi2c", "hsi2c_pclk"; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 }; 640 641 usi_i2c_2: usi@103500c0 { 642 compatible = "samsung,exynosautov9-usi", 643 "samsung,exynos850-usi"; 644 reg = <0x103500c0 0x20>; 645 samsung,sysreg = <&syscon_peric0 0x1014>; 646 samsung,mode = <USI_V2_I2C>; 647 #address-cells = <1>; 648 #size-cells = <1>; 649 ranges; 650 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>, 651 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>; 652 clock-names = "pclk", "ipclk"; 653 status = "disabled"; 654 655 hsi2c_5: i2c@10350000 { 656 compatible = "samsung,exynosautov9-hsi2c"; 657 reg = <0x10350000 0xc0>; 658 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&hsi2c5_bus>; 661 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>, 662 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>; 663 clock-names = "hsi2c", "hsi2c_pclk"; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 status = "disabled"; 667 }; 668 }; 669 670 usi_3: usi@103600c0 { 671 compatible = "samsung,exynosautov9-usi", 672 "samsung,exynos850-usi"; 673 reg = <0x103600c0 0x20>; 674 samsung,sysreg = <&syscon_peric0 0x1018>; 675 samsung,mode = <USI_V2_UART>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges; 679 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 680 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 681 clock-names = "pclk", "ipclk"; 682 status = "disabled"; 683 684 serial_3: serial@10360000 { 685 compatible = "samsung,exynosautov9-uart", 686 "samsung,exynos850-uart"; 687 reg = <0x10360000 0xc0>; 688 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&uart3_bus>; 691 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 692 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 693 clock-names = "uart", "clk_uart_baud0"; 694 samsung,uart-fifosize = <64>; 695 status = "disabled"; 696 }; 697 698 spi_3: spi@10360000 { 699 compatible = "samsung,exynosautov9-spi"; 700 reg = <0x10360000 0x30>; 701 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&spi3_bus &spi3_cs_func>; 704 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 705 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>, 706 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 707 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 708 samsung,spi-src-clk = <0>; 709 dmas = <&pdma0 7>, <&pdma0 6>; 710 dma-names = "tx", "rx"; 711 num-cs = <1>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 fifo-depth = <64>; 715 status = "disabled"; 716 }; 717 718 hsi2c_6: i2c@10360000 { 719 compatible = "samsung,exynosautov9-hsi2c"; 720 reg = <0x10360000 0xc0>; 721 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&hsi2c6_bus>; 724 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 725 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 726 clock-names = "hsi2c", "hsi2c_pclk"; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 status = "disabled"; 730 }; 731 }; 732 733 usi_i2c_3: usi@103700c0 { 734 compatible = "samsung,exynosautov9-usi", 735 "samsung,exynos850-usi"; 736 reg = <0x103700c0 0x20>; 737 samsung,sysreg = <&syscon_peric0 0x101c>; 738 samsung,mode = <USI_V2_I2C>; 739 #address-cells = <1>; 740 #size-cells = <1>; 741 ranges; 742 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>, 743 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>; 744 clock-names = "pclk", "ipclk"; 745 status = "disabled"; 746 747 hsi2c_7: i2c@10370000 { 748 compatible = "samsung,exynosautov9-hsi2c"; 749 reg = <0x10370000 0xc0>; 750 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&hsi2c7_bus>; 753 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>, 754 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>; 755 clock-names = "hsi2c", "hsi2c_pclk"; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 }; 761 762 usi_4: usi@103800c0 { 763 compatible = "samsung,exynosautov9-usi", 764 "samsung,exynos850-usi"; 765 reg = <0x103800c0 0x20>; 766 samsung,sysreg = <&syscon_peric0 0x1020>; 767 samsung,mode = <USI_V2_UART>; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges; 771 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 772 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 773 clock-names = "pclk", "ipclk"; 774 status = "disabled"; 775 776 serial_4: serial@10380000 { 777 compatible = "samsung,exynosautov9-uart", 778 "samsung,exynos850-uart"; 779 reg = <0x10380000 0xc0>; 780 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&uart4_bus>; 783 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 784 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 785 clock-names = "uart", "clk_uart_baud0"; 786 samsung,uart-fifosize = <64>; 787 status = "disabled"; 788 }; 789 790 spi_4: spi@10380000 { 791 compatible = "samsung,exynosautov9-spi"; 792 reg = <0x10380000 0x30>; 793 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 794 pinctrl-names = "default"; 795 pinctrl-0 = <&spi4_bus &spi4_cs_func>; 796 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 797 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>, 798 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 799 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 800 samsung,spi-src-clk = <0>; 801 dmas = <&pdma0 9>, <&pdma0 8>; 802 dma-names = "tx", "rx"; 803 num-cs = <1>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 fifo-depth = <64>; 807 status = "disabled"; 808 }; 809 810 hsi2c_8: i2c@10380000 { 811 compatible = "samsung,exynosautov9-hsi2c"; 812 reg = <0x10380000 0xc0>; 813 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&hsi2c8_bus>; 816 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 817 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 818 clock-names = "hsi2c", "hsi2c_pclk"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 }; 824 825 usi_i2c_4: usi@103900c0 { 826 compatible = "samsung,exynosautov9-usi", 827 "samsung,exynos850-usi"; 828 reg = <0x103900c0 0x20>; 829 samsung,sysreg = <&syscon_peric0 0x1024>; 830 samsung,mode = <USI_V2_I2C>; 831 #address-cells = <1>; 832 #size-cells = <1>; 833 ranges; 834 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>, 835 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>; 836 clock-names = "pclk", "ipclk"; 837 status = "disabled"; 838 839 hsi2c_9: i2c@10390000 { 840 compatible = "samsung,exynosautov9-hsi2c"; 841 reg = <0x10390000 0xc0>; 842 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&hsi2c9_bus>; 845 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>, 846 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>; 847 clock-names = "hsi2c", "hsi2c_pclk"; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 status = "disabled"; 851 }; 852 }; 853 854 usi_5: usi@103a00c0 { 855 compatible = "samsung,exynosautov9-usi", 856 "samsung,exynos850-usi"; 857 reg = <0x103a00c0 0x20>; 858 samsung,sysreg = <&syscon_peric0 0x1028>; 859 samsung,mode = <USI_V2_UART>; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 ranges; 863 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 864 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 865 clock-names = "pclk", "ipclk"; 866 status = "disabled"; 867 868 serial_5: serial@103a0000 { 869 compatible = "samsung,exynosautov9-uart", 870 "samsung,exynos850-uart"; 871 reg = <0x103a0000 0xc0>; 872 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&uart5_bus>; 875 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 876 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 877 clock-names = "uart", "clk_uart_baud0"; 878 samsung,uart-fifosize = <64>; 879 status = "disabled"; 880 }; 881 882 spi_5: spi@103a0000 { 883 compatible = "samsung,exynosautov9-spi"; 884 reg = <0x103a0000 0x30>; 885 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&spi5_bus &spi5_cs_func>; 888 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 889 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>, 890 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 891 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 892 samsung,spi-src-clk = <0>; 893 dmas = <&pdma0 11>, <&pdma0 10>; 894 dma-names = "tx", "rx"; 895 num-cs = <1>; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 fifo-depth = <64>; 899 status = "disabled"; 900 }; 901 902 hsi2c_10: i2c@103a0000 { 903 compatible = "samsung,exynosautov9-hsi2c"; 904 reg = <0x103a0000 0xc0>; 905 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&hsi2c10_bus>; 908 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 909 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 910 clock-names = "hsi2c", "hsi2c_pclk"; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 status = "disabled"; 914 }; 915 }; 916 917 usi_i2c_5: usi@103b00c0 { 918 compatible = "samsung,exynosautov9-usi", 919 "samsung,exynos850-usi"; 920 reg = <0x103b00c0 0x20>; 921 samsung,sysreg = <&syscon_peric0 0x102c>; 922 samsung,mode = <USI_V2_I2C>; 923 #address-cells = <1>; 924 #size-cells = <1>; 925 ranges; 926 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>, 927 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>; 928 clock-names = "pclk", "ipclk"; 929 status = "disabled"; 930 931 hsi2c_11: i2c@103b0000 { 932 compatible = "samsung,exynosautov9-hsi2c"; 933 reg = <0x103b0000 0xc0>; 934 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&hsi2c11_bus>; 937 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>, 938 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>; 939 clock-names = "hsi2c", "hsi2c_pclk"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 }; 944 }; 945 946 usi_6: usi@109000c0 { 947 compatible = "samsung,exynosautov9-usi", 948 "samsung,exynos850-usi"; 949 reg = <0x109000c0 0x20>; 950 samsung,sysreg = <&syscon_peric1 0x1000>; 951 samsung,mode = <USI_V2_UART>; 952 #address-cells = <1>; 953 #size-cells = <1>; 954 ranges; 955 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 956 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 957 clock-names = "pclk", "ipclk"; 958 status = "disabled"; 959 960 serial_6: serial@10900000 { 961 compatible = "samsung,exynosautov9-uart", 962 "samsung,exynos850-uart"; 963 reg = <0x10900000 0xc0>; 964 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&uart6_bus>; 967 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 968 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 969 clock-names = "uart", "clk_uart_baud0"; 970 samsung,uart-fifosize = <256>; 971 status = "disabled"; 972 }; 973 974 spi_6: spi@10900000 { 975 compatible = "samsung,exynosautov9-spi"; 976 reg = <0x10900000 0x30>; 977 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&spi6_bus &spi6_cs_func>; 980 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 981 <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>, 982 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 983 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 984 samsung,spi-src-clk = <0>; 985 dmas = <&pdma0 13>, <&pdma0 12>; 986 dma-names = "tx", "rx"; 987 num-cs = <1>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 fifo-depth = <256>; 991 status = "disabled"; 992 }; 993 994 hsi2c_12: i2c@10900000 { 995 compatible = "samsung,exynosautov9-hsi2c"; 996 reg = <0x10900000 0xc0>; 997 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&hsi2c12_bus>; 1000 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 1001 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 1002 clock-names = "hsi2c", "hsi2c_pclk"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 }; 1008 1009 usi_i2c_6: usi@109100c0 { 1010 compatible = "samsung,exynosautov9-usi", 1011 "samsung,exynos850-usi"; 1012 reg = <0x109100c0 0x20>; 1013 samsung,sysreg = <&syscon_peric1 0x1004>; 1014 samsung,mode = <USI_V2_I2C>; 1015 #address-cells = <1>; 1016 #size-cells = <1>; 1017 ranges; 1018 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>, 1019 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>; 1020 clock-names = "pclk", "ipclk"; 1021 status = "disabled"; 1022 1023 hsi2c_13: i2c@10910000 { 1024 compatible = "samsung,exynosautov9-hsi2c"; 1025 reg = <0x10910000 0xc0>; 1026 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&hsi2c13_bus>; 1029 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>, 1030 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>; 1031 clock-names = "hsi2c", "hsi2c_pclk"; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 }; 1037 1038 usi_7: usi@109200c0 { 1039 compatible = "samsung,exynosautov9-usi", 1040 "samsung,exynos850-usi"; 1041 reg = <0x109200c0 0x20>; 1042 samsung,sysreg = <&syscon_peric1 0x1008>; 1043 samsung,mode = <USI_V2_UART>; 1044 #address-cells = <1>; 1045 #size-cells = <1>; 1046 ranges; 1047 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1048 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1049 clock-names = "pclk", "ipclk"; 1050 status = "disabled"; 1051 1052 serial_7: serial@10920000 { 1053 compatible = "samsung,exynosautov9-uart", 1054 "samsung,exynos850-uart"; 1055 reg = <0x10920000 0xc0>; 1056 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&uart7_bus>; 1059 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1060 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1061 clock-names = "uart", "clk_uart_baud0"; 1062 samsung,uart-fifosize = <64>; 1063 status = "disabled"; 1064 }; 1065 1066 spi_7: spi@10920000 { 1067 compatible = "samsung,exynosautov9-spi"; 1068 reg = <0x10920000 0x30>; 1069 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&spi7_bus &spi7_cs_func>; 1072 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1073 <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>, 1074 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1075 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1076 samsung,spi-src-clk = <0>; 1077 dmas = <&pdma0 15>, <&pdma0 14>; 1078 dma-names = "tx", "rx"; 1079 num-cs = <1>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 fifo-depth = <64>; 1083 status = "disabled"; 1084 }; 1085 1086 hsi2c_14: i2c@10920000 { 1087 compatible = "samsung,exynosautov9-hsi2c"; 1088 reg = <0x10920000 0xc0>; 1089 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&hsi2c14_bus>; 1092 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1093 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1094 clock-names = "hsi2c", "hsi2c_pclk"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 }; 1100 1101 usi_i2c_7: usi@109300c0 { 1102 compatible = "samsung,exynosautov9-usi", 1103 "samsung,exynos850-usi"; 1104 reg = <0x109300c0 0x20>; 1105 samsung,sysreg = <&syscon_peric1 0x100c>; 1106 samsung,mode = <USI_V2_I2C>; 1107 #address-cells = <1>; 1108 #size-cells = <1>; 1109 ranges; 1110 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>, 1111 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>; 1112 clock-names = "pclk", "ipclk"; 1113 status = "disabled"; 1114 1115 hsi2c_15: i2c@10930000 { 1116 compatible = "samsung,exynosautov9-hsi2c"; 1117 reg = <0x10930000 0xc0>; 1118 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&hsi2c15_bus>; 1121 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>, 1122 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>; 1123 clock-names = "hsi2c", "hsi2c_pclk"; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 }; 1129 1130 usi_8: usi@109400c0 { 1131 compatible = "samsung,exynosautov9-usi", 1132 "samsung,exynos850-usi"; 1133 reg = <0x109400c0 0x20>; 1134 samsung,sysreg = <&syscon_peric1 0x1010>; 1135 samsung,mode = <USI_V2_UART>; 1136 #address-cells = <1>; 1137 #size-cells = <1>; 1138 ranges; 1139 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1140 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1141 clock-names = "pclk", "ipclk"; 1142 status = "disabled"; 1143 1144 serial_8: serial@10940000 { 1145 compatible = "samsung,exynosautov9-uart", 1146 "samsung,exynos850-uart"; 1147 reg = <0x10940000 0xc0>; 1148 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&uart8_bus>; 1151 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1152 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1153 clock-names = "uart", "clk_uart_baud0"; 1154 samsung,uart-fifosize = <64>; 1155 status = "disabled"; 1156 }; 1157 1158 spi_8: spi@10940000 { 1159 compatible = "samsung,exynosautov9-spi"; 1160 reg = <0x10940000 0x30>; 1161 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&spi8_bus &spi8_cs_func>; 1164 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1165 <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>, 1166 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1167 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1168 samsung,spi-src-clk = <0>; 1169 dmas = <&pdma0 17>, <&pdma0 16>; 1170 dma-names = "tx", "rx"; 1171 num-cs = <1>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 fifo-depth = <64>; 1175 status = "disabled"; 1176 }; 1177 1178 hsi2c_16: i2c@10940000 { 1179 compatible = "samsung,exynosautov9-hsi2c"; 1180 reg = <0x10940000 0xc0>; 1181 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&hsi2c16_bus>; 1184 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1185 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1186 clock-names = "hsi2c", "hsi2c_pclk"; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 }; 1192 1193 usi_i2c_8: usi@109500c0 { 1194 compatible = "samsung,exynosautov9-usi", 1195 "samsung,exynos850-usi"; 1196 reg = <0x109500c0 0x20>; 1197 samsung,sysreg = <&syscon_peric1 0x1014>; 1198 samsung,mode = <USI_V2_I2C>; 1199 #address-cells = <1>; 1200 #size-cells = <1>; 1201 ranges; 1202 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>, 1203 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>; 1204 clock-names = "pclk", "ipclk"; 1205 status = "disabled"; 1206 1207 hsi2c_17: i2c@10950000 { 1208 compatible = "samsung,exynosautov9-hsi2c"; 1209 reg = <0x10950000 0xc0>; 1210 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&hsi2c17_bus>; 1213 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>, 1214 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>; 1215 clock-names = "hsi2c", "hsi2c_pclk"; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 status = "disabled"; 1219 }; 1220 }; 1221 1222 usi_9: usi@109600c0 { 1223 compatible = "samsung,exynosautov9-usi", 1224 "samsung,exynos850-usi"; 1225 reg = <0x109600c0 0x20>; 1226 samsung,sysreg = <&syscon_peric1 0x1018>; 1227 samsung,mode = <USI_V2_UART>; 1228 #address-cells = <1>; 1229 #size-cells = <1>; 1230 ranges; 1231 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1232 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1233 clock-names = "pclk", "ipclk"; 1234 status = "disabled"; 1235 1236 serial_9: serial@10960000 { 1237 compatible = "samsung,exynosautov9-uart", 1238 "samsung,exynos850-uart"; 1239 reg = <0x10960000 0xc0>; 1240 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1241 pinctrl-names = "default"; 1242 pinctrl-0 = <&uart9_bus>; 1243 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1244 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1245 clock-names = "uart", "clk_uart_baud0"; 1246 samsung,uart-fifosize = <64>; 1247 status = "disabled"; 1248 }; 1249 1250 spi_9: spi@10960000 { 1251 compatible = "samsung,exynosautov9-spi"; 1252 reg = <0x10960000 0x30>; 1253 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1254 pinctrl-names = "default"; 1255 pinctrl-0 = <&spi9_bus &spi9_cs_func>; 1256 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1257 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>, 1258 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1259 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1260 samsung,spi-src-clk = <0>; 1261 dmas = <&pdma0 19>, <&pdma0 18>; 1262 dma-names = "tx", "rx"; 1263 num-cs = <1>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 fifo-depth = <64>; 1267 status = "disabled"; 1268 }; 1269 1270 hsi2c_18: i2c@10960000 { 1271 compatible = "samsung,exynosautov9-hsi2c"; 1272 reg = <0x10960000 0xc0>; 1273 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&hsi2c18_bus>; 1276 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1277 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1278 clock-names = "hsi2c", "hsi2c_pclk"; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 }; 1284 1285 usi_i2c_9: usi@109700c0 { 1286 compatible = "samsung,exynosautov9-usi", 1287 "samsung,exynos850-usi"; 1288 reg = <0x109700c0 0x20>; 1289 samsung,sysreg = <&syscon_peric1 0x101c>; 1290 samsung,mode = <USI_V2_I2C>; 1291 #address-cells = <1>; 1292 #size-cells = <1>; 1293 ranges; 1294 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>, 1295 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>; 1296 clock-names = "pclk", "ipclk"; 1297 status = "disabled"; 1298 1299 hsi2c_19: i2c@10970000 { 1300 compatible = "samsung,exynosautov9-hsi2c"; 1301 reg = <0x10970000 0xc0>; 1302 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&hsi2c19_bus>; 1305 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>, 1306 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>; 1307 clock-names = "hsi2c", "hsi2c_pclk"; 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 status = "disabled"; 1311 }; 1312 }; 1313 1314 usi_10: usi@109800c0 { 1315 compatible = "samsung,exynosautov9-usi", 1316 "samsung,exynos850-usi"; 1317 reg = <0x109800c0 0x20>; 1318 samsung,sysreg = <&syscon_peric1 0x1020>; 1319 samsung,mode = <USI_V2_UART>; 1320 #address-cells = <1>; 1321 #size-cells = <1>; 1322 ranges; 1323 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1324 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1325 clock-names = "pclk", "ipclk"; 1326 status = "disabled"; 1327 1328 serial_10: serial@10980000 { 1329 compatible = "samsung,exynosautov9-uart", 1330 "samsung,exynos850-uart"; 1331 reg = <0x10980000 0xc0>; 1332 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&uart10_bus>; 1335 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1336 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1337 clock-names = "uart", "clk_uart_baud0"; 1338 samsung,uart-fifosize = <64>; 1339 status = "disabled"; 1340 }; 1341 1342 spi_10: spi@10980000 { 1343 compatible = "samsung,exynosautov9-spi"; 1344 reg = <0x10980000 0x30>; 1345 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1346 pinctrl-names = "default"; 1347 pinctrl-0 = <&spi10_bus &spi10_cs_func>; 1348 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1349 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>, 1350 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1351 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1352 samsung,spi-src-clk = <0>; 1353 dmas = <&pdma0 21>, <&pdma0 20>; 1354 dma-names = "tx", "rx"; 1355 num-cs = <1>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 fifo-depth = <64>; 1359 status = "disabled"; 1360 }; 1361 1362 hsi2c_20: i2c@10980000 { 1363 compatible = "samsung,exynosautov9-hsi2c"; 1364 reg = <0x10980000 0xc0>; 1365 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&hsi2c20_bus>; 1368 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1369 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1370 clock-names = "hsi2c", "hsi2c_pclk"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 }; 1376 1377 usi_i2c_10: usi@109900c0 { 1378 compatible = "samsung,exynosautov9-usi", 1379 "samsung,exynos850-usi"; 1380 reg = <0x109900c0 0x20>; 1381 samsung,sysreg = <&syscon_peric1 0x1024>; 1382 samsung,mode = <USI_V2_I2C>; 1383 #address-cells = <1>; 1384 #size-cells = <1>; 1385 ranges; 1386 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>, 1387 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>; 1388 clock-names = "pclk", "ipclk"; 1389 status = "disabled"; 1390 1391 hsi2c_21: i2c@10990000 { 1392 compatible = "samsung,exynosautov9-hsi2c"; 1393 reg = <0x10990000 0xc0>; 1394 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&hsi2c21_bus>; 1397 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>, 1398 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>; 1399 clock-names = "hsi2c", "hsi2c_pclk"; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 }; 1405 1406 usi_11: usi@109a00c0 { 1407 compatible = "samsung,exynosautov9-usi", 1408 "samsung,exynos850-usi"; 1409 reg = <0x109a00c0 0x20>; 1410 samsung,sysreg = <&syscon_peric1 0x1028>; 1411 samsung,mode = <USI_V2_UART>; 1412 #address-cells = <1>; 1413 #size-cells = <1>; 1414 ranges; 1415 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1416 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1417 clock-names = "pclk", "ipclk"; 1418 status = "disabled"; 1419 1420 serial_11: serial@109a0000 { 1421 compatible = "samsung,exynosautov9-uart", 1422 "samsung,exynos850-uart"; 1423 reg = <0x109a0000 0xc0>; 1424 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&uart11_bus>; 1427 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1428 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1429 clock-names = "uart", "clk_uart_baud0"; 1430 samsung,uart-fifosize = <64>; 1431 status = "disabled"; 1432 }; 1433 1434 spi_11: spi@109a0000 { 1435 compatible = "samsung,exynosautov9-spi"; 1436 reg = <0x109a0000 0x30>; 1437 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1438 pinctrl-names = "default"; 1439 pinctrl-0 = <&spi11_bus &spi11_cs_func>; 1440 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1441 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>, 1442 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1443 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1444 samsung,spi-src-clk = <0>; 1445 num-cs = <1>; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 fifo-depth = <64>; 1449 status = "disabled"; 1450 }; 1451 1452 hsi2c_22: i2c@109a0000 { 1453 compatible = "samsung,exynosautov9-hsi2c"; 1454 reg = <0x109a0000 0xc0>; 1455 pinctrl-names = "default"; 1456 pinctrl-0 = <&hsi2c22_bus>; 1457 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1458 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1459 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1460 clock-names = "hsi2c", "hsi2c_pclk"; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 }; 1466 1467 usi_i2c_11: usi@109b00c0 { 1468 compatible = "samsung,exynosautov9-usi", 1469 "samsung,exynos850-usi"; 1470 reg = <0x109b00c0 0x20>; 1471 samsung,sysreg = <&syscon_peric1 0x102c>; 1472 samsung,mode = <USI_V2_I2C>; 1473 #address-cells = <1>; 1474 #size-cells = <1>; 1475 ranges; 1476 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>, 1477 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>; 1478 clock-names = "pclk", "ipclk"; 1479 status = "disabled"; 1480 1481 hsi2c_23: i2c@109b0000 { 1482 compatible = "samsung,exynosautov9-hsi2c"; 1483 reg = <0x109b0000 0xc0>; 1484 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1485 pinctrl-names = "default"; 1486 pinctrl-0 = <&hsi2c23_bus>; 1487 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>, 1488 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>; 1489 clock-names = "hsi2c", "hsi2c_pclk"; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 }; 1495 1496 ufs_0_phy: phy@17e04000 { 1497 compatible = "samsung,exynosautov9-ufs-phy"; 1498 reg = <0x17e04000 0xc00>; 1499 reg-names = "phy-pma"; 1500 samsung,pmu-syscon = <&pmu_system_controller>; 1501 #phy-cells = <0>; 1502 clocks = <&xtcxo>; 1503 clock-names = "ref_clk"; 1504 status = "disabled"; 1505 }; 1506 1507 ufs_0: ufs@17e00000 { 1508 compatible = "samsung,exynosautov9-ufs"; 1509 1510 reg = <0x17e00000 0x100>, 1511 <0x17e01100 0x410>, 1512 <0x17e80000 0x8000>, 1513 <0x17dc0000 0x2200>; 1514 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1515 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, 1517 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; 1518 clock-names = "core_clk", "sclk_unipro_main"; 1519 freq-table-hz = <0 0>, <0 0>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1522 phys = <&ufs_0_phy>; 1523 phy-names = "ufs-phy"; 1524 samsung,sysreg = <&syscon_fsys2 0x710>; 1525 status = "disabled"; 1526 }; 1527 1528 ufs_1_phy: phy@17f04000 { 1529 compatible = "samsung,exynosautov9-ufs-phy"; 1530 reg = <0x17f04000 0xc00>; 1531 reg-names = "phy-pma"; 1532 samsung,pmu-syscon = <&pmu_system_controller 0x72c>; 1533 #phy-cells = <0>; 1534 clocks = <&xtcxo>; 1535 clock-names = "ref_clk"; 1536 status = "disabled"; 1537 }; 1538 1539 ufs_1: ufs@17f00000 { 1540 compatible = "samsung,exynosautov9-ufs"; 1541 1542 reg = <0x17f00000 0x100>, 1543 <0x17f01100 0x410>, 1544 <0x17f80000 0x8000>, 1545 <0x17de0000 0x2200>; 1546 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1547 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, 1549 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; 1550 clock-names = "core_clk", "sclk_unipro_main"; 1551 freq-table-hz = <0 0>, <0 0>; 1552 pinctrl-names = "default"; 1553 pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; 1554 phys = <&ufs_1_phy>; 1555 phy-names = "ufs-phy"; 1556 samsung,sysreg = <&syscon_fsys2 0x714>; 1557 status = "disabled"; 1558 }; 1559 1560 watchdog_cl0: watchdog@10050000 { 1561 compatible = "samsung,exynosautov9-wdt"; 1562 reg = <0x10050000 0x100>; 1563 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 1564 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; 1565 clock-names = "watchdog", "watchdog_src"; 1566 samsung,syscon-phandle = <&pmu_system_controller>; 1567 samsung,cluster-index = <0>; 1568 }; 1569 1570 watchdog_cl1: watchdog@10060000 { 1571 compatible = "samsung,exynosautov9-wdt"; 1572 reg = <0x10060000 0x100>; 1573 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 1574 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; 1575 clock-names = "watchdog", "watchdog_src"; 1576 samsung,syscon-phandle = <&pmu_system_controller>; 1577 samsung,cluster-index = <1>; 1578 }; 1579 1580 pwm: pwm@103f0000 { 1581 compatible = "samsung,exynosautov9-pwm", 1582 "samsung,exynos4210-pwm"; 1583 reg = <0x103f0000 0x100>; 1584 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 1585 #pwm-cells = <3>; 1586 clocks = <&xtcxo>; 1587 clock-names = "timers"; 1588 status = "disabled"; 1589 }; 1590 }; 1591}; 1592 1593#include "exynosautov9-pinctrl.dtsi" 1594