1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2011 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include "imx51-pinfunc.h" 7#include <dt-bindings/clock/imx5-clock.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 /* 16 * The decompressor and also some bootloaders rely on a 17 * pre-existing /chosen node to be available to insert the 18 * command line and merge other ATAGS info. 19 */ 20 chosen {}; 21 22 aliases { 23 ethernet0 = &fec; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 mmc0 = &esdhc1; 31 mmc1 = &esdhc2; 32 mmc2 = &esdhc3; 33 mmc3 = &esdhc4; 34 serial0 = &uart1; 35 serial1 = &uart2; 36 serial2 = &uart3; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &cspi; 40 }; 41 42 tzic: tz-interrupt-controller@e0000000 { 43 compatible = "fsl,imx51-tzic", "fsl,tzic"; 44 interrupt-controller; 45 #interrupt-cells = <1>; 46 reg = <0xe0000000 0x4000>; 47 }; 48 49 clocks { 50 ckil { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <32768>; 54 }; 55 56 ckih1 { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <0>; 60 }; 61 62 ckih2 { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 }; 67 68 osc { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <24000000>; 72 }; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 cpu: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a8"; 81 reg = <0>; 82 clock-latency = <62500>; 83 clocks = <&clks IMX5_CLK_CPU_PODF>; 84 clock-names = "cpu"; 85 operating-points = < 86 166000 1000000 87 600000 1050000 88 800000 1100000 89 >; 90 voltage-tolerance = <5>; 91 }; 92 }; 93 94 pmu: pmu { 95 compatible = "arm,cortex-a8-pmu"; 96 interrupt-parent = <&tzic>; 97 interrupts = <77>; 98 }; 99 100 usbphy0: usbphy0 { 101 compatible = "usb-nop-xceiv"; 102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>; 103 clock-names = "main_clk"; 104 #phy-cells = <0>; 105 }; 106 107 capture-subsystem { 108 compatible = "fsl,imx-capture-subsystem"; 109 ports = <&ipu_csi0>, <&ipu_csi1>; 110 }; 111 112 display-subsystem { 113 compatible = "fsl,imx-display-subsystem"; 114 ports = <&ipu_di0>, <&ipu_di1>; 115 }; 116 117 soc: soc { 118 #address-cells = <1>; 119 #size-cells = <1>; 120 compatible = "simple-bus"; 121 interrupt-parent = <&tzic>; 122 ranges; 123 124 iram: sram@1ffe0000 { 125 compatible = "mmio-sram"; 126 reg = <0x1ffe0000 0x20000>; 127 ranges = <0 0x1ffe0000 0x20000>; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 }; 131 132 gpu: gpu@30000000 { 133 compatible = "amd,imageon-200.1", "amd,imageon"; 134 reg = <0x30000000 0x20000>; 135 reg-names = "kgsl_3d0_reg_memory"; 136 interrupts = <12>; 137 interrupt-names = "kgsl_3d0_irq"; 138 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; 139 clock-names = "core_clk", "mem_iface_clk"; 140 }; 141 142 ipu: ipu@40000000 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 compatible = "fsl,imx51-ipu"; 146 reg = <0x40000000 0x20000000>; 147 interrupts = <11 10>; 148 clocks = <&clks IMX5_CLK_IPU_GATE>, 149 <&clks IMX5_CLK_IPU_DI0_GATE>, 150 <&clks IMX5_CLK_IPU_DI1_GATE>; 151 clock-names = "bus", "di0", "di1"; 152 resets = <&src 2>; 153 154 ipu_csi0: port@0 { 155 reg = <0>; 156 }; 157 158 ipu_csi1: port@1 { 159 reg = <1>; 160 }; 161 162 ipu_di0: port@2 { 163 reg = <2>; 164 165 ipu_di0_disp1: endpoint { 166 }; 167 }; 168 169 ipu_di1: port@3 { 170 reg = <3>; 171 172 ipu_di1_disp2: endpoint { 173 }; 174 }; 175 }; 176 177 aips1: bus@70000000 { /* AIPS1 */ 178 compatible = "fsl,aips-bus", "simple-bus"; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 reg = <0x70000000 0x10000000>; 182 ranges; 183 184 spba-bus@70000000 { 185 compatible = "fsl,spba-bus", "simple-bus"; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 reg = <0x70000000 0x40000>; 189 ranges; 190 191 esdhc1: mmc@70004000 { 192 compatible = "fsl,imx51-esdhc"; 193 reg = <0x70004000 0x4000>; 194 interrupts = <1>; 195 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 196 <&clks IMX5_CLK_DUMMY>, 197 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 198 clock-names = "ipg", "ahb", "per"; 199 status = "disabled"; 200 }; 201 202 esdhc2: mmc@70008000 { 203 compatible = "fsl,imx51-esdhc"; 204 reg = <0x70008000 0x4000>; 205 interrupts = <2>; 206 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 207 <&clks IMX5_CLK_DUMMY>, 208 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 209 clock-names = "ipg", "ahb", "per"; 210 bus-width = <4>; 211 status = "disabled"; 212 }; 213 214 uart3: serial@7000c000 { 215 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 216 reg = <0x7000c000 0x4000>; 217 interrupts = <33>; 218 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 219 <&clks IMX5_CLK_UART3_PER_GATE>; 220 clock-names = "ipg", "per"; 221 dmas = <&sdma 43 5 1>, <&sdma 44 5 2>; 222 dma-names = "rx", "tx"; 223 status = "disabled"; 224 }; 225 226 ecspi1: spi@70010000 { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 compatible = "fsl,imx51-ecspi"; 230 reg = <0x70010000 0x4000>; 231 interrupts = <36>; 232 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 233 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 234 clock-names = "ipg", "per"; 235 status = "disabled"; 236 }; 237 238 ssi2: ssi@70014000 { 239 #sound-dai-cells = <0>; 240 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 241 reg = <0x70014000 0x4000>; 242 interrupts = <30>; 243 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, 244 <&clks IMX5_CLK_SSI2_ROOT_GATE>; 245 clock-names = "ipg", "baud"; 246 dmas = <&sdma 24 1 0>, 247 <&sdma 25 1 0>; 248 dma-names = "rx", "tx"; 249 fsl,fifo-depth = <15>; 250 status = "disabled"; 251 }; 252 253 esdhc3: mmc@70020000 { 254 compatible = "fsl,imx51-esdhc"; 255 reg = <0x70020000 0x4000>; 256 interrupts = <3>; 257 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 258 <&clks IMX5_CLK_DUMMY>, 259 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 260 clock-names = "ipg", "ahb", "per"; 261 bus-width = <4>; 262 status = "disabled"; 263 }; 264 265 esdhc4: mmc@70024000 { 266 compatible = "fsl,imx51-esdhc"; 267 reg = <0x70024000 0x4000>; 268 interrupts = <4>; 269 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 270 <&clks IMX5_CLK_DUMMY>, 271 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 272 clock-names = "ipg", "ahb", "per"; 273 bus-width = <4>; 274 status = "disabled"; 275 }; 276 }; 277 278 aipstz1: bridge@73f00000 { 279 compatible = "fsl,imx51-aipstz"; 280 reg = <0x73f00000 0x60>; 281 }; 282 283 usbotg: usb@73f80000 { 284 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 285 reg = <0x73f80000 0x0200>; 286 interrupts = <18>; 287 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 288 fsl,usbmisc = <&usbmisc 0>; 289 fsl,usbphy = <&usbphy0>; 290 status = "disabled"; 291 }; 292 293 usbh1: usb@73f80200 { 294 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 295 reg = <0x73f80200 0x0200>; 296 interrupts = <14>; 297 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 298 fsl,usbmisc = <&usbmisc 1>; 299 dr_mode = "host"; 300 status = "disabled"; 301 }; 302 303 usbh2: usb@73f80400 { 304 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 305 reg = <0x73f80400 0x0200>; 306 interrupts = <16>; 307 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 308 fsl,usbmisc = <&usbmisc 2>; 309 dr_mode = "host"; 310 status = "disabled"; 311 }; 312 313 usbh3: usb@73f80600 { 314 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 315 reg = <0x73f80600 0x0200>; 316 interrupts = <17>; 317 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 318 fsl,usbmisc = <&usbmisc 3>; 319 dr_mode = "host"; 320 status = "disabled"; 321 }; 322 323 usbmisc: usbmisc@73f80800 { 324 #index-cells = <1>; 325 compatible = "fsl,imx51-usbmisc"; 326 reg = <0x73f80800 0x200>; 327 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 328 }; 329 330 gpio1: gpio@73f84000 { 331 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 332 reg = <0x73f84000 0x4000>; 333 interrupts = <50 51>; 334 gpio-controller; 335 #gpio-cells = <2>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 340 gpio2: gpio@73f88000 { 341 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 342 reg = <0x73f88000 0x4000>; 343 interrupts = <52 53>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 }; 349 350 gpio3: gpio@73f8c000 { 351 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 352 reg = <0x73f8c000 0x4000>; 353 interrupts = <54 55>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 }; 359 360 gpio4: gpio@73f90000 { 361 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 362 reg = <0x73f90000 0x4000>; 363 interrupts = <56 57>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 }; 369 370 kpp: kpp@73f94000 { 371 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; 372 reg = <0x73f94000 0x4000>; 373 interrupts = <60>; 374 clocks = <&clks IMX5_CLK_DUMMY>; 375 status = "disabled"; 376 }; 377 378 wdog1: watchdog@73f98000 { 379 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 380 reg = <0x73f98000 0x4000>; 381 interrupts = <58>; 382 clocks = <&clks IMX5_CLK_DUMMY>; 383 }; 384 385 wdog2: watchdog@73f9c000 { 386 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 387 reg = <0x73f9c000 0x4000>; 388 interrupts = <59>; 389 clocks = <&clks IMX5_CLK_DUMMY>; 390 status = "disabled"; 391 }; 392 393 gpt: timer@73fa0000 { 394 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; 395 reg = <0x73fa0000 0x4000>; 396 interrupts = <39>; 397 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 398 <&clks IMX5_CLK_GPT_HF_GATE>; 399 clock-names = "ipg", "per"; 400 }; 401 402 iomuxc: iomuxc@73fa8000 { 403 compatible = "fsl,imx51-iomuxc"; 404 reg = <0x73fa8000 0x4000>; 405 }; 406 407 pwm1: pwm@73fb4000 { 408 #pwm-cells = <3>; 409 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 410 reg = <0x73fb4000 0x4000>; 411 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 412 <&clks IMX5_CLK_PWM1_HF_GATE>; 413 clock-names = "ipg", "per"; 414 interrupts = <61>; 415 }; 416 417 pwm2: pwm@73fb8000 { 418 #pwm-cells = <3>; 419 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 420 reg = <0x73fb8000 0x4000>; 421 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 422 <&clks IMX5_CLK_PWM2_HF_GATE>; 423 clock-names = "ipg", "per"; 424 interrupts = <94>; 425 }; 426 427 uart1: serial@73fbc000 { 428 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 429 reg = <0x73fbc000 0x4000>; 430 interrupts = <31>; 431 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 432 <&clks IMX5_CLK_UART1_PER_GATE>; 433 clock-names = "ipg", "per"; 434 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 uart2: serial@73fc0000 { 440 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 441 reg = <0x73fc0000 0x4000>; 442 interrupts = <32>; 443 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 444 <&clks IMX5_CLK_UART2_PER_GATE>; 445 clock-names = "ipg", "per"; 446 dmas = <&sdma 16 4 1>, <&sdma 17 4 2>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 src: reset-controller@73fd0000 { 452 compatible = "fsl,imx51-src"; 453 reg = <0x73fd0000 0x4000>; 454 interrupts = <75>; 455 #reset-cells = <1>; 456 }; 457 458 clks: ccm@73fd4000 { 459 compatible = "fsl,imx51-ccm"; 460 reg = <0x73fd4000 0x4000>; 461 interrupts = <0 71 0x04 0 72 0x04>; 462 #clock-cells = <1>; 463 }; 464 }; 465 466 aips2: bus@80000000 { /* AIPS2 */ 467 compatible = "fsl,aips-bus", "simple-bus"; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 reg = <0x80000000 0x10000000>; 471 ranges; 472 473 aipstz2: bridge@83f00000 { 474 compatible = "fsl,imx51-aipstz"; 475 reg = <0x83f00000 0x60>; 476 }; 477 478 iim: efuse@83f98000 { 479 compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon"; 480 reg = <0x83f98000 0x4000>; 481 interrupts = <69>; 482 clocks = <&clks IMX5_CLK_IIM_GATE>; 483 }; 484 485 tigerp: tigerp@83fa0000 { 486 compatible = "fsl,imx51-tigerp"; 487 reg = <0x83fa0000 0x28>; 488 }; 489 490 owire: owire@83fa4000 { 491 compatible = "fsl,imx51-owire", "fsl,imx21-owire"; 492 reg = <0x83fa4000 0x4000>; 493 interrupts = <88>; 494 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 495 status = "disabled"; 496 }; 497 498 ecspi2: spi@83fac000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "fsl,imx51-ecspi"; 502 reg = <0x83fac000 0x4000>; 503 interrupts = <37>; 504 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 505 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 506 clock-names = "ipg", "per"; 507 status = "disabled"; 508 }; 509 510 sdma: dma-controller@83fb0000 { 511 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 512 reg = <0x83fb0000 0x4000>; 513 interrupts = <6>; 514 clocks = <&clks IMX5_CLK_SDMA_GATE>, 515 <&clks IMX5_CLK_AHB>; 516 clock-names = "ipg", "ahb"; 517 #dma-cells = <3>; 518 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 519 }; 520 521 cspi: spi@83fc0000 { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 525 reg = <0x83fc0000 0x4000>; 526 interrupts = <38>; 527 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 528 <&clks IMX5_CLK_CSPI_IPG_GATE>; 529 clock-names = "ipg", "per"; 530 status = "disabled"; 531 }; 532 533 i2c2: i2c@83fc4000 { 534 #address-cells = <1>; 535 #size-cells = <0>; 536 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 537 reg = <0x83fc4000 0x4000>; 538 interrupts = <63>; 539 clocks = <&clks IMX5_CLK_I2C2_GATE>; 540 status = "disabled"; 541 }; 542 543 i2c1: i2c@83fc8000 { 544 #address-cells = <1>; 545 #size-cells = <0>; 546 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 547 reg = <0x83fc8000 0x4000>; 548 interrupts = <62>; 549 clocks = <&clks IMX5_CLK_I2C1_GATE>; 550 status = "disabled"; 551 }; 552 553 ssi1: ssi@83fcc000 { 554 #sound-dai-cells = <0>; 555 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 556 reg = <0x83fcc000 0x4000>; 557 interrupts = <29>; 558 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, 559 <&clks IMX5_CLK_SSI1_ROOT_GATE>; 560 clock-names = "ipg", "baud"; 561 dmas = <&sdma 28 0 0>, 562 <&sdma 29 0 0>; 563 dma-names = "rx", "tx"; 564 fsl,fifo-depth = <15>; 565 status = "disabled"; 566 }; 567 568 audmux: audmux@83fd0000 { 569 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 570 reg = <0x83fd0000 0x4000>; 571 clocks = <&clks IMX5_CLK_DUMMY>; 572 clock-names = "audmux"; 573 status = "disabled"; 574 }; 575 576 m4if: m4if@83fd8000 { 577 compatible = "fsl,imx51-m4if"; 578 reg = <0x83fd8000 0x1000>; 579 }; 580 581 weim: weim@83fda000 { 582 #address-cells = <2>; 583 #size-cells = <1>; 584 compatible = "fsl,imx51-weim"; 585 reg = <0x83fda000 0x1000>; 586 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; 587 ranges = < 588 0 0 0xb0000000 0x08000000 589 1 0 0xb8000000 0x08000000 590 2 0 0xc0000000 0x08000000 591 3 0 0xc8000000 0x04000000 592 4 0 0xcc000000 0x02000000 593 5 0 0xce000000 0x02000000 594 >; 595 status = "disabled"; 596 }; 597 598 nfc: nand@83fdb000 { 599 #address-cells = <1>; 600 #size-cells = <1>; 601 compatible = "fsl,imx51-nand"; 602 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 603 interrupts = <8>; 604 clocks = <&clks IMX5_CLK_NFC_GATE>; 605 status = "disabled"; 606 }; 607 608 pata: pata@83fe0000 { 609 compatible = "fsl,imx51-pata", "fsl,imx27-pata"; 610 reg = <0x83fe0000 0x4000>; 611 interrupts = <70>; 612 clocks = <&clks IMX5_CLK_PATA_GATE>; 613 status = "disabled"; 614 }; 615 616 ssi3: ssi@83fe8000 { 617 #sound-dai-cells = <0>; 618 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 619 reg = <0x83fe8000 0x4000>; 620 interrupts = <96>; 621 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, 622 <&clks IMX5_CLK_SSI3_ROOT_GATE>; 623 clock-names = "ipg", "baud"; 624 dmas = <&sdma 46 0 0>, 625 <&sdma 47 0 0>; 626 dma-names = "rx", "tx"; 627 fsl,fifo-depth = <15>; 628 status = "disabled"; 629 }; 630 631 fec: ethernet@83fec000 { 632 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 633 reg = <0x83fec000 0x4000>; 634 interrupts = <87>; 635 clocks = <&clks IMX5_CLK_FEC_GATE>, 636 <&clks IMX5_CLK_FEC_GATE>, 637 <&clks IMX5_CLK_FEC_GATE>; 638 clock-names = "ipg", "ahb", "ptp"; 639 status = "disabled"; 640 }; 641 642 vpu: vpu@83ff4000 { 643 compatible = "fsl,imx51-vpu", "cnm,codahx4"; 644 reg = <0x83ff4000 0x1000>; 645 interrupts = <9>; 646 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 647 <&clks IMX5_CLK_VPU_GATE>; 648 clock-names = "per", "ahb"; 649 resets = <&src 1>; 650 iram = <&iram>; 651 }; 652 653 sahara: crypto@83ff8000 { 654 compatible = "fsl,imx53-sahara"; 655 reg = <0x83ff8000 0x4000>; 656 interrupts = <19 20>; 657 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, 658 <&clks IMX5_CLK_SAHARA_IPG_GATE>; 659 clock-names = "ipg", "ahb"; 660 }; 661 }; 662 }; 663}; 664