1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 - Columbia University and Linaro Ltd. 4 * Author: Jintack Lim <jintack.lim@linaro.org> 5 */ 6 7 #include <linux/kvm.h> 8 #include <linux/kvm_host.h> 9 10 #include <asm/kvm_emulate.h> 11 #include <asm/kvm_nested.h> 12 #include <asm/sysreg.h> 13 14 #include "sys_regs.h" 15 16 /* Protection against the sysreg repainting madness... */ 17 #define NV_FTR(r, f) ID_AA64##r##_EL1_##f 18 19 /* 20 * Our emulated CPU doesn't support all the possible features. For the 21 * sake of simplicity (and probably mental sanity), wipe out a number 22 * of feature bits we don't intend to support for the time being. 23 * This list should get updated as new features get added to the NV 24 * support, and new extension to the architecture. 25 */ 26 static u64 limit_nv_id_reg(u32 id, u64 val) 27 { 28 u64 tmp; 29 30 switch (id) { 31 case SYS_ID_AA64ISAR0_EL1: 32 /* Support everything but TME, O.S. and Range TLBIs */ 33 val &= ~(NV_FTR(ISAR0, TLB) | 34 NV_FTR(ISAR0, TME)); 35 break; 36 37 case SYS_ID_AA64ISAR1_EL1: 38 /* Support everything but PtrAuth and Spec Invalidation */ 39 val &= ~(GENMASK_ULL(63, 56) | 40 NV_FTR(ISAR1, SPECRES) | 41 NV_FTR(ISAR1, GPI) | 42 NV_FTR(ISAR1, GPA) | 43 NV_FTR(ISAR1, API) | 44 NV_FTR(ISAR1, APA)); 45 break; 46 47 case SYS_ID_AA64PFR0_EL1: 48 /* No AMU, MPAM, S-EL2, RAS or SVE */ 49 val &= ~(GENMASK_ULL(55, 52) | 50 NV_FTR(PFR0, AMU) | 51 NV_FTR(PFR0, MPAM) | 52 NV_FTR(PFR0, SEL2) | 53 NV_FTR(PFR0, RAS) | 54 NV_FTR(PFR0, SVE) | 55 NV_FTR(PFR0, EL3) | 56 NV_FTR(PFR0, EL2) | 57 NV_FTR(PFR0, EL1)); 58 /* 64bit EL1/EL2/EL3 only */ 59 val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001); 60 val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001); 61 val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001); 62 break; 63 64 case SYS_ID_AA64PFR1_EL1: 65 /* Only support SSBS */ 66 val &= NV_FTR(PFR1, SSBS); 67 break; 68 69 case SYS_ID_AA64MMFR0_EL1: 70 /* Hide ECV, ExS, Secure Memory */ 71 val &= ~(NV_FTR(MMFR0, ECV) | 72 NV_FTR(MMFR0, EXS) | 73 NV_FTR(MMFR0, TGRAN4_2) | 74 NV_FTR(MMFR0, TGRAN16_2) | 75 NV_FTR(MMFR0, TGRAN64_2) | 76 NV_FTR(MMFR0, SNSMEM)); 77 78 /* Disallow unsupported S2 page sizes */ 79 switch (PAGE_SIZE) { 80 case SZ_64K: 81 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0001); 82 fallthrough; 83 case SZ_16K: 84 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0001); 85 fallthrough; 86 case SZ_4K: 87 /* Support everything */ 88 break; 89 } 90 /* 91 * Since we can't support a guest S2 page size smaller than 92 * the host's own page size (due to KVM only populating its 93 * own S2 using the kernel's page size), advertise the 94 * limitation using FEAT_GTG. 95 */ 96 switch (PAGE_SIZE) { 97 case SZ_4K: 98 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0010); 99 fallthrough; 100 case SZ_16K: 101 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0010); 102 fallthrough; 103 case SZ_64K: 104 val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN64_2), 0b0010); 105 break; 106 } 107 /* Cap PARange to 48bits */ 108 tmp = FIELD_GET(NV_FTR(MMFR0, PARANGE), val); 109 if (tmp > 0b0101) { 110 val &= ~NV_FTR(MMFR0, PARANGE); 111 val |= FIELD_PREP(NV_FTR(MMFR0, PARANGE), 0b0101); 112 } 113 break; 114 115 case SYS_ID_AA64MMFR1_EL1: 116 val &= (NV_FTR(MMFR1, HCX) | 117 NV_FTR(MMFR1, PAN) | 118 NV_FTR(MMFR1, LO) | 119 NV_FTR(MMFR1, HPDS) | 120 NV_FTR(MMFR1, VH) | 121 NV_FTR(MMFR1, VMIDBits)); 122 break; 123 124 case SYS_ID_AA64MMFR2_EL1: 125 val &= ~(NV_FTR(MMFR2, BBM) | 126 NV_FTR(MMFR2, TTL) | 127 GENMASK_ULL(47, 44) | 128 NV_FTR(MMFR2, ST) | 129 NV_FTR(MMFR2, CCIDX) | 130 NV_FTR(MMFR2, VARange)); 131 132 /* Force TTL support */ 133 val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001); 134 break; 135 136 case SYS_ID_AA64DFR0_EL1: 137 /* Only limited support for PMU, Debug, BPs and WPs */ 138 val &= (NV_FTR(DFR0, PMUVer) | 139 NV_FTR(DFR0, WRPs) | 140 NV_FTR(DFR0, BRPs) | 141 NV_FTR(DFR0, DebugVer)); 142 143 /* Cap Debug to ARMv8.1 */ 144 tmp = FIELD_GET(NV_FTR(DFR0, DebugVer), val); 145 if (tmp > 0b0111) { 146 val &= ~NV_FTR(DFR0, DebugVer); 147 val |= FIELD_PREP(NV_FTR(DFR0, DebugVer), 0b0111); 148 } 149 break; 150 151 default: 152 /* Unknown register, just wipe it clean */ 153 val = 0; 154 break; 155 } 156 157 return val; 158 } 159 int kvm_init_nv_sysregs(struct kvm *kvm) 160 { 161 mutex_lock(&kvm->arch.config_lock); 162 163 for (int i = 0; i < KVM_ARM_ID_REG_NUM; i++) 164 kvm->arch.id_regs[i] = limit_nv_id_reg(IDX_IDREG(i), 165 kvm->arch.id_regs[i]); 166 167 mutex_unlock(&kvm->arch.config_lock); 168 169 return 0; 170 } 171