1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11 12/ { 13 compatible = "rockchip,rk3128"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 arm-pmu { 19 compatible = "arm,cortex-a7-pmu"; 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 enable-method = "rockchip,rk3036-smp"; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 clock-latency = <40000>; 37 clocks = <&cru ARMCLK>; 38 resets = <&cru SRST_CORE0>; 39 operating-points-v2 = <&cpu_opp_table>; 40 #cooling-cells = <2>; /* min followed by max */ 41 }; 42 43 cpu1: cpu@f01 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0xf01>; 47 resets = <&cru SRST_CORE1>; 48 operating-points-v2 = <&cpu_opp_table>; 49 }; 50 51 cpu2: cpu@f02 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf02>; 55 resets = <&cru SRST_CORE2>; 56 operating-points-v2 = <&cpu_opp_table>; 57 }; 58 59 cpu3: cpu@f03 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf03>; 63 resets = <&cru SRST_CORE3>; 64 operating-points-v2 = <&cpu_opp_table>; 65 }; 66 }; 67 68 cpu_opp_table: opp-table-0 { 69 compatible = "operating-points-v2"; 70 opp-shared; 71 72 opp-216000000 { 73 opp-hz = /bits/ 64 <216000000>; 74 opp-microvolt = <950000 950000 1325000>; 75 }; 76 opp-408000000 { 77 opp-hz = /bits/ 64 <408000000>; 78 opp-microvolt = <950000 950000 1325000>; 79 }; 80 opp-600000000 { 81 opp-hz = /bits/ 64 <600000000>; 82 opp-microvolt = <950000 950000 1325000>; 83 }; 84 opp-696000000 { 85 opp-hz = /bits/ 64 <696000000>; 86 opp-microvolt = <975000 975000 1325000>; 87 }; 88 opp-816000000 { 89 opp-hz = /bits/ 64 <816000000>; 90 opp-microvolt = <1075000 1075000 1325000>; 91 opp-suspend; 92 }; 93 opp-1008000000 { 94 opp-hz = /bits/ 64 <1008000000>; 95 opp-microvolt = <1200000 1200000 1325000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <1325000 1325000 1325000>; 100 }; 101 }; 102 103 timer { 104 compatible = "arm,armv7-timer"; 105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 arm,cpu-registers-not-fw-configured; 110 clock-frequency = <24000000>; 111 }; 112 113 xin24m: oscillator { 114 compatible = "fixed-clock"; 115 clock-frequency = <24000000>; 116 clock-output-names = "xin24m"; 117 #clock-cells = <0>; 118 }; 119 120 imem: sram@10080000 { 121 compatible = "mmio-sram"; 122 reg = <0x10080000 0x2000>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0x10080000 0x2000>; 126 127 smp-sram@0 { 128 compatible = "rockchip,rk3066-smp-sram"; 129 reg = <0x00 0x10>; 130 }; 131 }; 132 133 pmu: syscon@100a0000 { 134 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 135 reg = <0x100a0000 0x1000>; 136 }; 137 138 gic: interrupt-controller@10139000 { 139 compatible = "arm,cortex-a7-gic"; 140 reg = <0x10139000 0x1000>, 141 <0x1013a000 0x1000>, 142 <0x1013c000 0x2000>, 143 <0x1013e000 0x2000>; 144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 #address-cells = <0>; 148 }; 149 150 usb_otg: usb@10180000 { 151 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 152 reg = <0x10180000 0x40000>; 153 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&cru HCLK_OTG>; 155 clock-names = "otg"; 156 dr_mode = "otg"; 157 phys = <&usb2phy_otg>; 158 phy-names = "usb2-phy"; 159 status = "disabled"; 160 }; 161 162 usb_host_ehci: usb@101c0000 { 163 compatible = "generic-ehci"; 164 reg = <0x101c0000 0x20000>; 165 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 166 phys = <&usb2phy_host>; 167 phy-names = "usb"; 168 status = "disabled"; 169 }; 170 171 usb_host_ohci: usb@101e0000 { 172 compatible = "generic-ohci"; 173 reg = <0x101e0000 0x20000>; 174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 175 phys = <&usb2phy_host>; 176 phy-names = "usb"; 177 status = "disabled"; 178 }; 179 180 sdmmc: mmc@10214000 { 181 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 182 reg = <0x10214000 0x4000>; 183 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 185 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 186 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 187 dmas = <&pdma 10>; 188 dma-names = "rx-tx"; 189 fifo-depth = <256>; 190 max-frequency = <150000000>; 191 resets = <&cru SRST_SDMMC>; 192 reset-names = "reset"; 193 status = "disabled"; 194 }; 195 196 sdio: mmc@10218000 { 197 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 198 reg = <0x10218000 0x4000>; 199 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 201 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 202 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 203 dmas = <&pdma 11>; 204 dma-names = "rx-tx"; 205 fifo-depth = <256>; 206 max-frequency = <150000000>; 207 resets = <&cru SRST_SDIO>; 208 reset-names = "reset"; 209 status = "disabled"; 210 }; 211 212 emmc: mmc@1021c000 { 213 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 214 reg = <0x1021c000 0x4000>; 215 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 217 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 218 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 219 dmas = <&pdma 12>; 220 dma-names = "rx-tx"; 221 fifo-depth = <256>; 222 max-frequency = <150000000>; 223 resets = <&cru SRST_EMMC>; 224 reset-names = "reset"; 225 status = "disabled"; 226 }; 227 228 nfc: nand-controller@10500000 { 229 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 230 reg = <0x10500000 0x4000>; 231 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 233 clock-names = "ahb", "nfc"; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 236 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 237 status = "disabled"; 238 }; 239 240 cru: clock-controller@20000000 { 241 compatible = "rockchip,rk3128-cru"; 242 reg = <0x20000000 0x1000>; 243 clocks = <&xin24m>; 244 clock-names = "xin24m"; 245 rockchip,grf = <&grf>; 246 #clock-cells = <1>; 247 #reset-cells = <1>; 248 assigned-clocks = <&cru PLL_GPLL>; 249 assigned-clock-rates = <594000000>; 250 }; 251 252 grf: syscon@20008000 { 253 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 254 reg = <0x20008000 0x1000>; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 258 usb2phy: usb2phy@17c { 259 compatible = "rockchip,rk3128-usb2phy"; 260 reg = <0x017c 0x0c>; 261 clocks = <&cru SCLK_OTGPHY0>; 262 clock-names = "phyclk"; 263 clock-output-names = "usb480m_phy"; 264 #clock-cells = <0>; 265 status = "disabled"; 266 267 usb2phy_host: host-port { 268 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-names = "linestate"; 270 #phy-cells = <0>; 271 status = "disabled"; 272 }; 273 274 usb2phy_otg: otg-port { 275 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 278 interrupt-names = "otg-bvalid", "otg-id", 279 "linestate"; 280 #phy-cells = <0>; 281 status = "disabled"; 282 }; 283 }; 284 }; 285 286 timer0: timer@20044000 { 287 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 288 reg = <0x20044000 0x20>; 289 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 291 clock-names = "pclk", "timer"; 292 }; 293 294 timer1: timer@20044020 { 295 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 296 reg = <0x20044020 0x20>; 297 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 299 clock-names = "pclk", "timer"; 300 }; 301 302 timer2: timer@20044040 { 303 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 304 reg = <0x20044040 0x20>; 305 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 307 clock-names = "pclk", "timer"; 308 }; 309 310 timer3: timer@20044060 { 311 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 312 reg = <0x20044060 0x20>; 313 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 315 clock-names = "pclk", "timer"; 316 }; 317 318 timer4: timer@20044080 { 319 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 320 reg = <0x20044080 0x20>; 321 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 323 clock-names = "pclk", "timer"; 324 }; 325 326 timer5: timer@200440a0 { 327 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 328 reg = <0x200440a0 0x20>; 329 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 331 clock-names = "pclk", "timer"; 332 }; 333 334 watchdog: watchdog@2004c000 { 335 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 336 reg = <0x2004c000 0x100>; 337 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cru PCLK_WDT>; 339 status = "disabled"; 340 }; 341 342 pwm0: pwm@20050000 { 343 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 344 reg = <0x20050000 0x10>; 345 clocks = <&cru PCLK_PWM>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pwm0_pin>; 348 #pwm-cells = <3>; 349 status = "disabled"; 350 }; 351 352 pwm1: pwm@20050010 { 353 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 354 reg = <0x20050010 0x10>; 355 clocks = <&cru PCLK_PWM>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pwm1_pin>; 358 #pwm-cells = <3>; 359 status = "disabled"; 360 }; 361 362 pwm2: pwm@20050020 { 363 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 364 reg = <0x20050020 0x10>; 365 clocks = <&cru PCLK_PWM>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pwm2_pin>; 368 #pwm-cells = <3>; 369 status = "disabled"; 370 }; 371 372 pwm3: pwm@20050030 { 373 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 374 reg = <0x20050030 0x10>; 375 clocks = <&cru PCLK_PWM>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pwm3_pin>; 378 #pwm-cells = <3>; 379 status = "disabled"; 380 }; 381 382 i2c1: i2c@20056000 { 383 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 384 reg = <0x20056000 0x1000>; 385 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 386 clock-names = "i2c"; 387 clocks = <&cru PCLK_I2C1>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&i2c1_xfer>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 status = "disabled"; 393 }; 394 395 i2c2: i2c@2005a000 { 396 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 397 reg = <0x2005a000 0x1000>; 398 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 399 clock-names = "i2c"; 400 clocks = <&cru PCLK_I2C2>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&i2c2_xfer>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 status = "disabled"; 406 }; 407 408 i2c3: i2c@2005e000 { 409 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 410 reg = <0x2005e000 0x1000>; 411 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 412 clock-names = "i2c"; 413 clocks = <&cru PCLK_I2C3>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&i2c3_xfer>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 status = "disabled"; 419 }; 420 421 uart0: serial@20060000 { 422 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 423 reg = <0x20060000 0x100>; 424 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 425 clock-frequency = <24000000>; 426 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 427 clock-names = "baudclk", "apb_pclk"; 428 dmas = <&pdma 2>, <&pdma 3>; 429 dma-names = "tx", "rx"; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 432 reg-io-width = <4>; 433 reg-shift = <2>; 434 status = "disabled"; 435 }; 436 437 uart1: serial@20064000 { 438 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 439 reg = <0x20064000 0x100>; 440 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 441 clock-frequency = <24000000>; 442 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 443 clock-names = "baudclk", "apb_pclk"; 444 dmas = <&pdma 4>, <&pdma 5>; 445 dma-names = "tx", "rx"; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&uart1_xfer>; 448 reg-io-width = <4>; 449 reg-shift = <2>; 450 status = "disabled"; 451 }; 452 453 uart2: serial@20068000 { 454 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 455 reg = <0x20068000 0x100>; 456 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 457 clock-frequency = <24000000>; 458 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 459 clock-names = "baudclk", "apb_pclk"; 460 dmas = <&pdma 6>, <&pdma 7>; 461 dma-names = "tx", "rx"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&uart2_xfer>; 464 reg-io-width = <4>; 465 reg-shift = <2>; 466 status = "disabled"; 467 }; 468 469 saradc: saradc@2006c000 { 470 compatible = "rockchip,saradc"; 471 reg = <0x2006c000 0x100>; 472 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 474 clock-names = "saradc", "apb_pclk"; 475 resets = <&cru SRST_SARADC>; 476 reset-names = "saradc-apb"; 477 #io-channel-cells = <1>; 478 status = "disabled"; 479 }; 480 481 i2c0: i2c@20072000 { 482 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 483 reg = <0x20072000 0x1000>; 484 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 485 clock-names = "i2c"; 486 clocks = <&cru PCLK_I2C0>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&i2c0_xfer>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 status = "disabled"; 492 }; 493 494 spi0: spi@20074000 { 495 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 496 reg = <0x20074000 0x1000>; 497 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 499 clock-names = "spiclk", "apb_pclk"; 500 dmas = <&pdma 8>, <&pdma 9>; 501 dma-names = "tx", "rx"; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 status = "disabled"; 507 }; 508 509 pdma: dma-controller@20078000 { 510 compatible = "arm,pl330", "arm,primecell"; 511 reg = <0x20078000 0x4000>; 512 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 514 arm,pl330-broken-no-flushp; 515 arm,pl330-periph-burst; 516 clocks = <&cru ACLK_DMAC>; 517 clock-names = "apb_pclk"; 518 #dma-cells = <1>; 519 }; 520 521 pinctrl: pinctrl { 522 compatible = "rockchip,rk3128-pinctrl"; 523 rockchip,grf = <&grf>; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 ranges; 527 528 gpio0: gpio@2007c000 { 529 compatible = "rockchip,gpio-bank"; 530 reg = <0x2007c000 0x100>; 531 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&cru PCLK_GPIO0>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 }; 538 539 gpio1: gpio@20080000 { 540 compatible = "rockchip,gpio-bank"; 541 reg = <0x20080000 0x100>; 542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cru PCLK_GPIO1>; 544 gpio-controller; 545 #gpio-cells = <2>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 550 gpio2: gpio@20084000 { 551 compatible = "rockchip,gpio-bank"; 552 reg = <0x20084000 0x100>; 553 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&cru PCLK_GPIO2>; 555 gpio-controller; 556 #gpio-cells = <2>; 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 }; 560 561 gpio3: gpio@20088000 { 562 compatible = "rockchip,gpio-bank"; 563 reg = <0x20088000 0x100>; 564 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cru PCLK_GPIO3>; 566 gpio-controller; 567 #gpio-cells = <2>; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 }; 571 572 pcfg_pull_default: pcfg-pull-default { 573 bias-pull-pin-default; 574 }; 575 576 pcfg_pull_none: pcfg-pull-none { 577 bias-disable; 578 }; 579 580 emmc { 581 emmc_clk: emmc-clk { 582 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 583 }; 584 585 emmc_cmd: emmc-cmd { 586 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 587 }; 588 589 emmc_cmd1: emmc-cmd1 { 590 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 591 }; 592 593 emmc_pwr: emmc-pwr { 594 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 595 }; 596 597 emmc_bus1: emmc-bus1 { 598 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 599 }; 600 601 emmc_bus4: emmc-bus4 { 602 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 603 <1 RK_PD1 2 &pcfg_pull_default>, 604 <1 RK_PD2 2 &pcfg_pull_default>, 605 <1 RK_PD3 2 &pcfg_pull_default>; 606 }; 607 608 emmc_bus8: emmc-bus8 { 609 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 610 <1 RK_PD1 2 &pcfg_pull_default>, 611 <1 RK_PD2 2 &pcfg_pull_default>, 612 <1 RK_PD3 2 &pcfg_pull_default>, 613 <1 RK_PD4 2 &pcfg_pull_default>, 614 <1 RK_PD5 2 &pcfg_pull_default>, 615 <1 RK_PD6 2 &pcfg_pull_default>, 616 <1 RK_PD7 2 &pcfg_pull_default>; 617 }; 618 }; 619 620 gmac { 621 rgmii_pins: rgmii-pins { 622 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 623 <2 RK_PB1 3 &pcfg_pull_default>, 624 <2 RK_PB3 3 &pcfg_pull_default>, 625 <2 RK_PB4 3 &pcfg_pull_default>, 626 <2 RK_PB5 3 &pcfg_pull_default>, 627 <2 RK_PB6 3 &pcfg_pull_default>, 628 <2 RK_PC0 3 &pcfg_pull_default>, 629 <2 RK_PC1 3 &pcfg_pull_default>, 630 <2 RK_PC2 3 &pcfg_pull_default>, 631 <2 RK_PC3 3 &pcfg_pull_default>, 632 <2 RK_PD1 3 &pcfg_pull_default>, 633 <2 RK_PC4 4 &pcfg_pull_default>, 634 <2 RK_PC5 4 &pcfg_pull_default>, 635 <2 RK_PC6 4 &pcfg_pull_default>, 636 <2 RK_PC7 4 &pcfg_pull_default>; 637 }; 638 639 rmii_pins: rmii-pins { 640 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 641 <2 RK_PB4 3 &pcfg_pull_default>, 642 <2 RK_PB5 3 &pcfg_pull_default>, 643 <2 RK_PB6 3 &pcfg_pull_default>, 644 <2 RK_PB7 3 &pcfg_pull_default>, 645 <2 RK_PC0 3 &pcfg_pull_default>, 646 <2 RK_PC1 3 &pcfg_pull_default>, 647 <2 RK_PC2 3 &pcfg_pull_default>, 648 <2 RK_PC3 3 &pcfg_pull_default>, 649 <2 RK_PD1 3 &pcfg_pull_default>; 650 }; 651 }; 652 653 hdmi { 654 hdmii2c_xfer: hdmii2c-xfer { 655 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 656 <0 RK_PA7 2 &pcfg_pull_none>; 657 }; 658 659 hdmi_hpd: hdmi-hpd { 660 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 661 }; 662 663 hdmi_cec: hdmi-cec { 664 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 665 }; 666 }; 667 668 i2c0 { 669 i2c0_xfer: i2c0-xfer { 670 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 671 <0 RK_PA1 1 &pcfg_pull_none>; 672 }; 673 }; 674 675 i2c1 { 676 i2c1_xfer: i2c1-xfer { 677 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 678 <0 RK_PA3 1 &pcfg_pull_none>; 679 }; 680 }; 681 682 i2c2 { 683 i2c2_xfer: i2c2-xfer { 684 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 685 <2 RK_PC5 3 &pcfg_pull_none>; 686 }; 687 }; 688 689 i2c3 { 690 i2c3_xfer: i2c3-xfer { 691 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 692 <0 RK_PA7 1 &pcfg_pull_none>; 693 }; 694 }; 695 696 i2s { 697 i2s_bus: i2s-bus { 698 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 699 <0 RK_PB1 1 &pcfg_pull_none>, 700 <0 RK_PB3 1 &pcfg_pull_none>, 701 <0 RK_PB4 1 &pcfg_pull_none>, 702 <0 RK_PB5 1 &pcfg_pull_none>, 703 <0 RK_PB6 1 &pcfg_pull_none>; 704 }; 705 706 i2s1_bus: i2s1-bus { 707 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 708 <1 RK_PA1 1 &pcfg_pull_none>, 709 <1 RK_PA2 1 &pcfg_pull_none>, 710 <1 RK_PA3 1 &pcfg_pull_none>, 711 <1 RK_PA4 1 &pcfg_pull_none>, 712 <1 RK_PA5 1 &pcfg_pull_none>; 713 }; 714 }; 715 716 lcdc { 717 lcdc_dclk: lcdc-dclk { 718 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 719 }; 720 721 lcdc_den: lcdc-den { 722 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 723 }; 724 725 lcdc_hsync: lcdc-hsync { 726 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 727 }; 728 729 lcdc_vsync: lcdc-vsync { 730 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 731 }; 732 733 lcdc_rgb24: lcdc-rgb24 { 734 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 735 <2 RK_PB5 1 &pcfg_pull_none>, 736 <2 RK_PB6 1 &pcfg_pull_none>, 737 <2 RK_PB7 1 &pcfg_pull_none>, 738 <2 RK_PC0 1 &pcfg_pull_none>, 739 <2 RK_PC1 1 &pcfg_pull_none>, 740 <2 RK_PC2 1 &pcfg_pull_none>, 741 <2 RK_PC3 1 &pcfg_pull_none>, 742 <2 RK_PC4 1 &pcfg_pull_none>, 743 <2 RK_PC5 1 &pcfg_pull_none>, 744 <2 RK_PC6 1 &pcfg_pull_none>, 745 <2 RK_PC7 1 &pcfg_pull_none>, 746 <2 RK_PD0 1 &pcfg_pull_none>, 747 <2 RK_PD1 1 &pcfg_pull_none>; 748 }; 749 }; 750 751 nfc { 752 flash_ale: flash-ale { 753 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 754 }; 755 756 flash_cle: flash-cle { 757 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 758 }; 759 760 flash_wrn: flash-wrn { 761 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 762 }; 763 764 flash_rdn: flash-rdn { 765 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 766 }; 767 768 flash_rdy: flash-rdy { 769 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 770 }; 771 772 flash_cs0: flash-cs0 { 773 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 774 }; 775 776 flash_dqs: flash-dqs { 777 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 778 }; 779 780 flash_bus8: flash-bus8 { 781 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 782 <1 RK_PD1 1 &pcfg_pull_none>, 783 <1 RK_PD2 1 &pcfg_pull_none>, 784 <1 RK_PD3 1 &pcfg_pull_none>, 785 <1 RK_PD4 1 &pcfg_pull_none>, 786 <1 RK_PD5 1 &pcfg_pull_none>, 787 <1 RK_PD6 1 &pcfg_pull_none>, 788 <1 RK_PD7 1 &pcfg_pull_none>; 789 }; 790 }; 791 792 pwm0 { 793 pwm0_pin: pwm0-pin { 794 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 795 }; 796 }; 797 798 pwm1 { 799 pwm1_pin: pwm1-pin { 800 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 801 }; 802 }; 803 804 pwm2 { 805 pwm2_pin: pwm2-pin { 806 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 807 }; 808 }; 809 810 pwm3 { 811 pwm3_pin: pwm3-pin { 812 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 813 }; 814 }; 815 816 sdio { 817 sdio_clk: sdio-clk { 818 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 819 }; 820 821 sdio_cmd: sdio-cmd { 822 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 823 }; 824 825 sdio_pwren: sdio-pwren { 826 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 827 }; 828 829 sdio_bus4: sdio-bus4 { 830 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 831 <1 RK_PA2 2 &pcfg_pull_default>, 832 <1 RK_PA4 2 &pcfg_pull_default>, 833 <1 RK_PA5 2 &pcfg_pull_default>; 834 }; 835 }; 836 837 sdmmc { 838 sdmmc_clk: sdmmc-clk { 839 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 840 }; 841 842 sdmmc_cmd: sdmmc-cmd { 843 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 844 }; 845 846 sdmmc_wp: sdmmc-wp { 847 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 848 }; 849 850 sdmmc_pwren: sdmmc-pwren { 851 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 852 }; 853 854 sdmmc_bus4: sdmmc-bus4 { 855 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 856 <1 RK_PC3 1 &pcfg_pull_default>, 857 <1 RK_PC4 1 &pcfg_pull_default>, 858 <1 RK_PC5 1 &pcfg_pull_default>; 859 }; 860 }; 861 862 spdif { 863 spdif_tx: spdif-tx { 864 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 865 }; 866 }; 867 868 spi0 { 869 spi0_clk: spi0-clk { 870 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 871 }; 872 873 spi0_cs0: spi0-cs0 { 874 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 875 }; 876 877 spi0_tx: spi0-tx { 878 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 879 }; 880 881 spi0_rx: spi0-rx { 882 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 883 }; 884 885 spi0_cs1: spi0-cs1 { 886 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 887 }; 888 889 spi1_clk: spi1-clk { 890 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 891 }; 892 893 spi1_cs0: spi1-cs0 { 894 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 895 }; 896 897 spi1_tx: spi1-tx { 898 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 899 }; 900 901 spi1_rx: spi1-rx { 902 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 903 }; 904 905 spi1_cs1: spi1-cs1 { 906 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 907 }; 908 909 spi2_clk: spi2-clk { 910 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 911 }; 912 913 spi2_cs0: spi2-cs0 { 914 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 915 }; 916 917 spi2_tx: spi2-tx { 918 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 919 }; 920 921 spi2_rx: spi2-rx { 922 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 923 }; 924 }; 925 926 uart0 { 927 uart0_xfer: uart0-xfer { 928 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 929 <2 RK_PD3 2 &pcfg_pull_none>; 930 }; 931 932 uart0_cts: uart0-cts { 933 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 934 }; 935 936 uart0_rts: uart0-rts { 937 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 938 }; 939 }; 940 941 uart1 { 942 uart1_xfer: uart1-xfer { 943 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 944 <1 RK_PB2 2 &pcfg_pull_default>; 945 }; 946 947 uart1_cts: uart1-cts { 948 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 949 }; 950 951 uart1_rts: uart1-rts { 952 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 953 }; 954 }; 955 956 uart2 { 957 uart2_xfer: uart2-xfer { 958 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 959 <1 RK_PC3 2 &pcfg_pull_none>; 960 }; 961 962 uart2_cts: uart2-cts { 963 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 964 }; 965 966 uart2_rts: uart2-rts { 967 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 968 }; 969 }; 970 }; 971}; 972