1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 #include <linux/static_call.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/hardirq.h> 16 17 #define ARCH_APICTIMER_STOPS_ON_C3 1 18 19 /* 20 * Debugging macros 21 */ 22 #define APIC_QUIET 0 23 #define APIC_VERBOSE 1 24 #define APIC_DEBUG 2 25 26 /* Macros for apic_extnmi which controls external NMI masking */ 27 #define APIC_EXTNMI_BSP 0 /* Default */ 28 #define APIC_EXTNMI_ALL 1 29 #define APIC_EXTNMI_NONE 2 30 31 /* 32 * Define the default level of output to be very little 33 * This can be turned up by using apic=verbose for more 34 * information and apic=debug for _lots_ of information. 35 * apic_verbosity is defined in apic.c 36 */ 37 #define apic_printk(v, s, a...) do { \ 38 if ((v) <= apic_verbosity) \ 39 printk(s, ##a); \ 40 } while (0) 41 42 43 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 44 extern void x86_32_probe_apic(void); 45 #else 46 static inline void x86_32_probe_apic(void) { } 47 #endif 48 49 #ifdef CONFIG_X86_LOCAL_APIC 50 51 extern int apic_verbosity; 52 extern int local_apic_timer_c2_ok; 53 54 extern bool apic_is_disabled; 55 extern unsigned int lapic_timer_period; 56 57 extern u32 cpuid_to_apicid[]; 58 59 extern enum apic_intr_mode_id apic_intr_mode; 60 enum apic_intr_mode_id { 61 APIC_PIC, 62 APIC_VIRTUAL_WIRE, 63 APIC_VIRTUAL_WIRE_NO_CONFIG, 64 APIC_SYMMETRIC_IO, 65 APIC_SYMMETRIC_IO_NO_ROUTING 66 }; 67 68 /* 69 * With 82489DX we can't rely on apic feature bit 70 * retrieved via cpuid but still have to deal with 71 * such an apic chip so we assume that SMP configuration 72 * is found from MP table (64bit case uses ACPI mostly 73 * which set smp presence flag as well so we are safe 74 * to use this helper too). 75 */ 76 static inline bool apic_from_smp_config(void) 77 { 78 return smp_found_config && !apic_is_disabled; 79 } 80 81 /* 82 * Basic functions accessing APICs. 83 */ 84 #ifdef CONFIG_PARAVIRT 85 #include <asm/paravirt.h> 86 #endif 87 88 static inline void native_apic_mem_write(u32 reg, u32 v) 89 { 90 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 91 92 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, 93 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 94 ASM_OUTPUT2("0" (v), "m" (*addr))); 95 } 96 97 static inline u32 native_apic_mem_read(u32 reg) 98 { 99 return *((volatile u32 *)(APIC_BASE + reg)); 100 } 101 102 static inline void native_apic_mem_eoi(void) 103 { 104 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); 105 } 106 107 extern void native_apic_icr_write(u32 low, u32 id); 108 extern u64 native_apic_icr_read(void); 109 110 static inline bool apic_is_x2apic_enabled(void) 111 { 112 u64 msr; 113 114 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 115 return false; 116 return msr & X2APIC_ENABLE; 117 } 118 119 extern void enable_IR_x2apic(void); 120 121 extern int get_physical_broadcast(void); 122 123 extern int lapic_get_maxlvt(void); 124 extern void clear_local_APIC(void); 125 extern void disconnect_bsp_APIC(int virt_wire_setup); 126 extern void disable_local_APIC(void); 127 extern void apic_soft_disable(void); 128 extern void lapic_shutdown(void); 129 extern void sync_Arb_IDs(void); 130 extern void init_bsp_APIC(void); 131 extern void apic_intr_mode_select(void); 132 extern void apic_intr_mode_init(void); 133 extern void init_apic_mappings(void); 134 void register_lapic_address(unsigned long address); 135 extern void setup_boot_APIC_clock(void); 136 extern void setup_secondary_APIC_clock(void); 137 extern void lapic_update_tsc_freq(void); 138 139 #ifdef CONFIG_X86_64 140 static inline bool apic_force_enable(unsigned long addr) 141 { 142 return false; 143 } 144 #else 145 extern bool apic_force_enable(unsigned long addr); 146 #endif 147 148 extern void apic_ap_setup(void); 149 150 /* 151 * On 32bit this is mach-xxx local 152 */ 153 #ifdef CONFIG_X86_64 154 extern int apic_is_clustered_box(void); 155 #else 156 static inline int apic_is_clustered_box(void) 157 { 158 return 0; 159 } 160 #endif 161 162 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 163 extern void lapic_assign_system_vectors(void); 164 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 165 extern void lapic_update_legacy_vectors(void); 166 extern void lapic_online(void); 167 extern void lapic_offline(void); 168 extern bool apic_needs_pit(void); 169 170 extern void apic_send_IPI_allbutself(unsigned int vector); 171 172 #else /* !CONFIG_X86_LOCAL_APIC */ 173 static inline void lapic_shutdown(void) { } 174 #define local_apic_timer_c2_ok 1 175 static inline void init_apic_mappings(void) { } 176 static inline void disable_local_APIC(void) { } 177 # define setup_boot_APIC_clock x86_init_noop 178 # define setup_secondary_APIC_clock x86_init_noop 179 static inline void lapic_update_tsc_freq(void) { } 180 static inline void init_bsp_APIC(void) { } 181 static inline void apic_intr_mode_select(void) { } 182 static inline void apic_intr_mode_init(void) { } 183 static inline void lapic_assign_system_vectors(void) { } 184 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 185 static inline bool apic_needs_pit(void) { return true; } 186 #endif /* !CONFIG_X86_LOCAL_APIC */ 187 188 #ifdef CONFIG_X86_X2APIC 189 static inline void native_apic_msr_write(u32 reg, u32 v) 190 { 191 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 192 reg == APIC_LVR) 193 return; 194 195 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 196 } 197 198 static inline void native_apic_msr_eoi(void) 199 { 200 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 201 } 202 203 static inline u32 native_apic_msr_read(u32 reg) 204 { 205 u64 msr; 206 207 if (reg == APIC_DFR) 208 return -1; 209 210 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 211 return (u32)msr; 212 } 213 214 static inline void native_x2apic_icr_write(u32 low, u32 id) 215 { 216 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 217 } 218 219 static inline u64 native_x2apic_icr_read(void) 220 { 221 unsigned long val; 222 223 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 224 return val; 225 } 226 227 extern int x2apic_mode; 228 extern int x2apic_phys; 229 extern void __init x2apic_set_max_apicid(u32 apicid); 230 extern void x2apic_setup(void); 231 static inline int x2apic_enabled(void) 232 { 233 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 234 } 235 236 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 237 #else /* !CONFIG_X86_X2APIC */ 238 static inline void x2apic_setup(void) { } 239 static inline int x2apic_enabled(void) { return 0; } 240 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 241 #define x2apic_mode (0) 242 #define x2apic_supported() (0) 243 #endif /* !CONFIG_X86_X2APIC */ 244 extern void __init check_x2apic(void); 245 246 struct irq_data; 247 248 /* 249 * Copyright 2004 James Cleverdon, IBM. 250 * 251 * Generic APIC sub-arch data struct. 252 * 253 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 254 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 255 * James Cleverdon. 256 */ 257 struct apic { 258 /* Hotpath functions first */ 259 void (*eoi)(void); 260 void (*native_eoi)(void); 261 void (*write)(u32 reg, u32 v); 262 u32 (*read)(u32 reg); 263 264 /* IPI related functions */ 265 void (*wait_icr_idle)(void); 266 u32 (*safe_wait_icr_idle)(void); 267 268 void (*send_IPI)(int cpu, int vector); 269 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 270 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 271 void (*send_IPI_allbutself)(int vector); 272 void (*send_IPI_all)(int vector); 273 void (*send_IPI_self)(int vector); 274 275 enum apic_delivery_modes delivery_mode; 276 277 u32 disable_esr : 1, 278 dest_mode_logical : 1, 279 x2apic_set_max_apicid : 1, 280 nmi_to_offline_cpu : 1; 281 282 u32 (*calc_dest_apicid)(unsigned int cpu); 283 284 /* ICR related functions */ 285 u64 (*icr_read)(void); 286 void (*icr_write)(u32 low, u32 high); 287 288 /* The limit of the APIC ID space. */ 289 u32 max_apic_id; 290 291 /* Probe, setup and smpboot functions */ 292 int (*probe)(void); 293 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 294 bool (*apic_id_registered)(void); 295 296 bool (*check_apicid_used)(physid_mask_t *map, u32 apicid); 297 void (*init_apic_ldr)(void); 298 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 299 u32 (*cpu_present_to_apicid)(int mps_cpu); 300 u32 (*phys_pkg_id)(u32 cpuid_apic, int index_msb); 301 302 u32 (*get_apic_id)(u32 id); 303 u32 (*set_apic_id)(u32 apicid); 304 305 /* wakeup_secondary_cpu */ 306 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); 307 /* wakeup secondary CPU using 64-bit wakeup point */ 308 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); 309 310 char *name; 311 }; 312 313 struct apic_override { 314 void (*eoi)(void); 315 void (*native_eoi)(void); 316 void (*write)(u32 reg, u32 v); 317 u32 (*read)(u32 reg); 318 void (*send_IPI)(int cpu, int vector); 319 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 320 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 321 void (*send_IPI_allbutself)(int vector); 322 void (*send_IPI_all)(int vector); 323 void (*send_IPI_self)(int vector); 324 u64 (*icr_read)(void); 325 void (*icr_write)(u32 low, u32 high); 326 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); 327 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); 328 }; 329 330 /* 331 * Pointer to the local APIC driver in use on this system (there's 332 * always just one such driver in use - the kernel decides via an 333 * early probing process which one it picks - and then sticks to it): 334 */ 335 extern struct apic *apic; 336 337 /* 338 * APIC drivers are probed based on how they are listed in the .apicdrivers 339 * section. So the order is important and enforced by the ordering 340 * of different apic driver files in the Makefile. 341 * 342 * For the files having two apic drivers, we use apic_drivers() 343 * to enforce the order with in them. 344 */ 345 #define apic_driver(sym) \ 346 static const struct apic *__apicdrivers_##sym __used \ 347 __aligned(sizeof(struct apic *)) \ 348 __section(".apicdrivers") = { &sym } 349 350 #define apic_drivers(sym1, sym2) \ 351 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 352 __aligned(sizeof(struct apic *)) \ 353 __section(".apicdrivers") = { &sym1, &sym2 } 354 355 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 356 357 /* 358 * APIC functionality to boot other CPUs - only used on SMP: 359 */ 360 #ifdef CONFIG_SMP 361 extern int lapic_can_unplug_cpu(void); 362 #endif 363 364 #ifdef CONFIG_X86_LOCAL_APIC 365 extern struct apic_override __x86_apic_override; 366 367 void __init apic_setup_apic_calls(void); 368 void __init apic_install_driver(struct apic *driver); 369 370 #define apic_update_callback(_callback, _fn) { \ 371 __x86_apic_override._callback = _fn; \ 372 apic->_callback = _fn; \ 373 static_call_update(apic_call_##_callback, _fn); \ 374 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ 375 } 376 377 #define DECLARE_APIC_CALL(__cb) \ 378 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) 379 380 DECLARE_APIC_CALL(eoi); 381 DECLARE_APIC_CALL(native_eoi); 382 DECLARE_APIC_CALL(icr_read); 383 DECLARE_APIC_CALL(icr_write); 384 DECLARE_APIC_CALL(read); 385 DECLARE_APIC_CALL(send_IPI); 386 DECLARE_APIC_CALL(send_IPI_mask); 387 DECLARE_APIC_CALL(send_IPI_mask_allbutself); 388 DECLARE_APIC_CALL(send_IPI_allbutself); 389 DECLARE_APIC_CALL(send_IPI_all); 390 DECLARE_APIC_CALL(send_IPI_self); 391 DECLARE_APIC_CALL(wait_icr_idle); 392 DECLARE_APIC_CALL(wakeup_secondary_cpu); 393 DECLARE_APIC_CALL(wakeup_secondary_cpu_64); 394 DECLARE_APIC_CALL(write); 395 396 static __always_inline u32 apic_read(u32 reg) 397 { 398 return static_call(apic_call_read)(reg); 399 } 400 401 static __always_inline void apic_write(u32 reg, u32 val) 402 { 403 static_call(apic_call_write)(reg, val); 404 } 405 406 static __always_inline void apic_eoi(void) 407 { 408 static_call(apic_call_eoi)(); 409 } 410 411 static __always_inline void apic_native_eoi(void) 412 { 413 static_call(apic_call_native_eoi)(); 414 } 415 416 static __always_inline u64 apic_icr_read(void) 417 { 418 return static_call(apic_call_icr_read)(); 419 } 420 421 static __always_inline void apic_icr_write(u32 low, u32 high) 422 { 423 static_call(apic_call_icr_write)(low, high); 424 } 425 426 static __always_inline void __apic_send_IPI(int cpu, int vector) 427 { 428 static_call(apic_call_send_IPI)(cpu, vector); 429 } 430 431 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) 432 { 433 static_call_mod(apic_call_send_IPI_mask)(mask, vector); 434 } 435 436 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 437 { 438 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); 439 } 440 441 static __always_inline void __apic_send_IPI_allbutself(int vector) 442 { 443 static_call(apic_call_send_IPI_allbutself)(vector); 444 } 445 446 static __always_inline void __apic_send_IPI_all(int vector) 447 { 448 static_call(apic_call_send_IPI_all)(vector); 449 } 450 451 static __always_inline void __apic_send_IPI_self(int vector) 452 { 453 static_call_mod(apic_call_send_IPI_self)(vector); 454 } 455 456 static __always_inline void apic_wait_icr_idle(void) 457 { 458 static_call_cond(apic_call_wait_icr_idle)(); 459 } 460 461 static __always_inline u32 safe_apic_wait_icr_idle(void) 462 { 463 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; 464 } 465 466 static __always_inline bool apic_id_valid(u32 apic_id) 467 { 468 return apic_id <= apic->max_apic_id; 469 } 470 471 #else /* CONFIG_X86_LOCAL_APIC */ 472 473 static inline u32 apic_read(u32 reg) { return 0; } 474 static inline void apic_write(u32 reg, u32 val) { } 475 static inline void apic_eoi(void) { } 476 static inline u64 apic_icr_read(void) { return 0; } 477 static inline void apic_icr_write(u32 low, u32 high) { } 478 static inline void apic_wait_icr_idle(void) { } 479 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 480 static inline void apic_set_eoi_cb(void (*eoi)(void)) {} 481 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } 482 static inline void apic_setup_apic_calls(void) { } 483 484 #define apic_update_callback(_callback, _fn) do { } while (0) 485 486 #endif /* CONFIG_X86_LOCAL_APIC */ 487 488 extern void apic_ack_irq(struct irq_data *data); 489 490 static inline bool lapic_vector_set_in_irr(unsigned int vector) 491 { 492 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 493 494 return !!(irr & (1U << (vector % 32))); 495 } 496 497 /* 498 * Warm reset vector position: 499 */ 500 #define TRAMPOLINE_PHYS_LOW 0x467 501 #define TRAMPOLINE_PHYS_HIGH 0x469 502 503 extern void generic_bigsmp_probe(void); 504 505 #ifdef CONFIG_X86_LOCAL_APIC 506 507 #include <asm/smp.h> 508 509 extern struct apic apic_noop; 510 511 static inline u32 read_apic_id(void) 512 { 513 u32 reg = apic_read(APIC_ID); 514 515 return apic->get_apic_id(reg); 516 } 517 518 #ifdef CONFIG_X86_64 519 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 520 extern int default_acpi_madt_oem_check(char *, char *); 521 extern void x86_64_probe_apic(void); 522 #else 523 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 524 static inline void x86_64_probe_apic(void) { } 525 #endif 526 527 extern int default_apic_id_valid(u32 apicid); 528 529 extern u32 apic_default_calc_apicid(unsigned int cpu); 530 extern u32 apic_flat_calc_apicid(unsigned int cpu); 531 532 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); 533 extern u32 default_cpu_present_to_apicid(int mps_cpu); 534 535 void apic_send_nmi_to_offline_cpu(unsigned int cpu); 536 537 #else /* CONFIG_X86_LOCAL_APIC */ 538 539 static inline u32 read_apic_id(void) { return 0; } 540 541 #endif /* !CONFIG_X86_LOCAL_APIC */ 542 543 #ifdef CONFIG_SMP 544 void apic_smt_update(void); 545 #else 546 static inline void apic_smt_update(void) { } 547 #endif 548 549 struct msi_msg; 550 struct irq_cfg; 551 552 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 553 bool dmar); 554 555 extern void ioapic_zap_locks(void); 556 557 #endif /* _ASM_X86_APIC_H */ 558