1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995 Waldorf GmbH 7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 10 * Author: Maciej W. Rozycki <macro@mips.com> 11 */ 12 #ifndef _ASM_IO_H 13 #define _ASM_IO_H 14 15 #include <linux/compiler.h> 16 #include <linux/types.h> 17 #include <linux/irqflags.h> 18 19 #include <asm/addrspace.h> 20 #include <asm/barrier.h> 21 #include <asm/bug.h> 22 #include <asm/byteorder.h> 23 #include <asm/cpu.h> 24 #include <asm/cpu-features.h> 25 #include <asm/page.h> 26 #include <asm/pgtable-bits.h> 27 #include <asm/string.h> 28 #include <mangle-port.h> 29 30 /* 31 * Raw operations are never swapped in software. OTOH values that raw 32 * operations are working on may or may not have been swapped by the bus 33 * hardware. An example use would be for flash memory that's used for 34 * execute in place. 35 */ 36 # define __raw_ioswabb(a, x) (x) 37 # define __raw_ioswabw(a, x) (x) 38 # define __raw_ioswabl(a, x) (x) 39 # define __raw_ioswabq(a, x) (x) 40 # define ____raw_ioswabq(a, x) (x) 41 42 # define _ioswabb ioswabb 43 # define _ioswabw ioswabw 44 # define _ioswabl ioswabl 45 # define _ioswabq ioswabq 46 47 # define __relaxed_ioswabb ioswabb 48 # define __relaxed_ioswabw ioswabw 49 # define __relaxed_ioswabl ioswabl 50 # define __relaxed_ioswabq ioswabq 51 52 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 53 54 /* 55 * On MIPS I/O ports are memory mapped, so we access them using normal 56 * load/store instructions. mips_io_port_base is the virtual address to 57 * which all ports are being mapped. For sake of efficiency some code 58 * assumes that this is an address that can be loaded with a single lui 59 * instruction, so the lower 16 bits must be zero. Should be true on 60 * any sane architecture; generic code does not use this assumption. 61 */ 62 extern unsigned long mips_io_port_base; 63 64 static inline void set_io_port_base(unsigned long base) 65 { 66 mips_io_port_base = base; 67 } 68 69 /* 70 * Provide the necessary definitions for generic iomap. We make use of 71 * mips_io_port_base for iomap(), but we don't reserve any low addresses for 72 * use with I/O ports. 73 */ 74 75 #define HAVE_ARCH_PIO_SIZE 76 #define PIO_OFFSET mips_io_port_base 77 #define PIO_MASK IO_SPACE_LIMIT 78 #define PIO_RESERVED 0x0UL 79 80 /* 81 * Enforce in-order execution of data I/O. In the MIPS architecture 82 * these are equivalent to corresponding platform-specific memory 83 * barriers defined in <asm/barrier.h>. API pinched from PowerPC, 84 * with sync additionally defined. 85 */ 86 #define iobarrier_rw() mb() 87 #define iobarrier_r() rmb() 88 #define iobarrier_w() wmb() 89 #define iobarrier_sync() iob() 90 91 /* 92 * virt_to_phys - map virtual addresses to physical 93 * @address: address to remap 94 * 95 * The returned physical address is the physical (CPU) mapping for 96 * the memory address given. It is only valid to use this function on 97 * addresses directly mapped or allocated via kmalloc. 98 * 99 * This function does not give bus mappings for DMA transfers. In 100 * almost all conceivable cases a device driver should not be using 101 * this function 102 */ 103 static inline unsigned long __virt_to_phys_nodebug(volatile const void *address) 104 { 105 return __pa(address); 106 } 107 108 #ifdef CONFIG_DEBUG_VIRTUAL 109 extern phys_addr_t __virt_to_phys(volatile const void *x); 110 #else 111 #define __virt_to_phys(x) __virt_to_phys_nodebug(x) 112 #endif 113 114 #define virt_to_phys virt_to_phys 115 static inline phys_addr_t virt_to_phys(const volatile void *x) 116 { 117 return __virt_to_phys(x); 118 } 119 120 /* 121 * ISA I/O bus memory addresses are 1:1 with the physical address. 122 */ 123 static inline unsigned long isa_virt_to_bus(volatile void *address) 124 { 125 return virt_to_phys(address); 126 } 127 128 /* 129 * Change "struct page" to physical address. 130 */ 131 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 132 133 void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, 134 unsigned long prot_val); 135 void iounmap(const volatile void __iomem *addr); 136 137 /* 138 * ioremap - map bus memory into CPU space 139 * @offset: bus address of the memory 140 * @size: size of the resource to map 141 * 142 * ioremap performs a platform specific sequence of operations to 143 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 144 * writew/writel functions and the other mmio helpers. The returned 145 * address is not guaranteed to be usable directly as a virtual 146 * address. 147 */ 148 #define ioremap(offset, size) \ 149 ioremap_prot((offset), (size), _CACHE_UNCACHED) 150 151 /* 152 * ioremap_cache - map bus memory into CPU space 153 * @offset: bus address of the memory 154 * @size: size of the resource to map 155 * 156 * ioremap_cache performs a platform specific sequence of operations to 157 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 158 * writew/writel functions and the other mmio helpers. The returned 159 * address is not guaranteed to be usable directly as a virtual 160 * address. 161 * 162 * This version of ioremap ensures that the memory is marked cacheable by 163 * the CPU. Also enables full write-combining. Useful for some 164 * memory-like regions on I/O busses. 165 */ 166 #define ioremap_cache(offset, size) \ 167 ioremap_prot((offset), (size), _page_cachable_default) 168 169 /* 170 * ioremap_wc - map bus memory into CPU space 171 * @offset: bus address of the memory 172 * @size: size of the resource to map 173 * 174 * ioremap_wc performs a platform specific sequence of operations to 175 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 176 * writew/writel functions and the other mmio helpers. The returned 177 * address is not guaranteed to be usable directly as a virtual 178 * address. 179 * 180 * This version of ioremap ensures that the memory is marked uncacheable 181 * but accelerated by means of write-combining feature. It is specifically 182 * useful for PCIe prefetchable windows, which may vastly improve a 183 * communications performance. If it was determined on boot stage, what 184 * CPU CCA doesn't support UCA, the method shall fall-back to the 185 * _CACHE_UNCACHED option (see cpu_probe() method). 186 */ 187 #define ioremap_wc(offset, size) \ 188 ioremap_prot((offset), (size), boot_cpu_data.writecombine) 189 190 #if defined(CONFIG_CPU_CAVIUM_OCTEON) 191 #define war_io_reorder_wmb() wmb() 192 #else 193 #define war_io_reorder_wmb() barrier() 194 #endif 195 196 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \ 197 \ 198 static inline void pfx##write##bwlq(type val, \ 199 volatile void __iomem *mem) \ 200 { \ 201 volatile type *__mem; \ 202 type __val; \ 203 \ 204 if (barrier) \ 205 iobarrier_rw(); \ 206 else \ 207 war_io_reorder_wmb(); \ 208 \ 209 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 210 \ 211 __val = pfx##ioswab##bwlq(__mem, val); \ 212 \ 213 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 214 *__mem = __val; \ 215 else if (cpu_has_64bits) { \ 216 unsigned long __flags; \ 217 type __tmp; \ 218 \ 219 if (irq) \ 220 local_irq_save(__flags); \ 221 __asm__ __volatile__( \ 222 ".set push" "\t\t# __writeq""\n\t" \ 223 ".set arch=r4000" "\n\t" \ 224 "dsll32 %L0, %L0, 0" "\n\t" \ 225 "dsrl32 %L0, %L0, 0" "\n\t" \ 226 "dsll32 %M0, %M0, 0" "\n\t" \ 227 "or %L0, %L0, %M0" "\n\t" \ 228 "sd %L0, %2" "\n\t" \ 229 ".set pop" "\n" \ 230 : "=r" (__tmp) \ 231 : "0" (__val), "m" (*__mem)); \ 232 if (irq) \ 233 local_irq_restore(__flags); \ 234 } else \ 235 BUG(); \ 236 } \ 237 \ 238 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 239 { \ 240 volatile type *__mem; \ 241 type __val; \ 242 \ 243 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 244 \ 245 if (barrier) \ 246 iobarrier_rw(); \ 247 \ 248 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 249 __val = *__mem; \ 250 else if (cpu_has_64bits) { \ 251 unsigned long __flags; \ 252 \ 253 if (irq) \ 254 local_irq_save(__flags); \ 255 __asm__ __volatile__( \ 256 ".set push" "\t\t# __readq" "\n\t" \ 257 ".set arch=r4000" "\n\t" \ 258 "ld %L0, %1" "\n\t" \ 259 "dsra32 %M0, %L0, 0" "\n\t" \ 260 "sll %L0, %L0, 0" "\n\t" \ 261 ".set pop" "\n" \ 262 : "=r" (__val) \ 263 : "m" (*__mem)); \ 264 if (irq) \ 265 local_irq_restore(__flags); \ 266 } else { \ 267 __val = 0; \ 268 BUG(); \ 269 } \ 270 \ 271 /* prevent prefetching of coherent DMA data prematurely */ \ 272 if (!relax) \ 273 rmb(); \ 274 return pfx##ioswab##bwlq(__mem, __val); \ 275 } 276 277 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax) \ 278 \ 279 static inline void pfx##out##bwlq(type val, unsigned long port) \ 280 { \ 281 volatile type *__addr; \ 282 type __val; \ 283 \ 284 if (barrier) \ 285 iobarrier_rw(); \ 286 else \ 287 war_io_reorder_wmb(); \ 288 \ 289 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 290 \ 291 __val = pfx##ioswab##bwlq(__addr, val); \ 292 \ 293 /* Really, we want this to be atomic */ \ 294 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 295 \ 296 *__addr = __val; \ 297 } \ 298 \ 299 static inline type pfx##in##bwlq(unsigned long port) \ 300 { \ 301 volatile type *__addr; \ 302 type __val; \ 303 \ 304 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 305 \ 306 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 307 \ 308 if (barrier) \ 309 iobarrier_rw(); \ 310 \ 311 __val = *__addr; \ 312 \ 313 /* prevent prefetching of coherent DMA data prematurely */ \ 314 if (!relax) \ 315 rmb(); \ 316 return pfx##ioswab##bwlq(__addr, __val); \ 317 } 318 319 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \ 320 \ 321 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1) 322 323 #define BUILDIO_MEM(bwlq, type) \ 324 \ 325 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \ 326 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \ 327 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \ 328 __BUILD_MEMORY_PFX(, bwlq, type, 0) 329 330 BUILDIO_MEM(b, u8) 331 BUILDIO_MEM(w, u16) 332 BUILDIO_MEM(l, u32) 333 #ifdef CONFIG_64BIT 334 BUILDIO_MEM(q, u64) 335 #else 336 __BUILD_MEMORY_PFX(__raw_, q, u64, 0) 337 __BUILD_MEMORY_PFX(__mem_, q, u64, 0) 338 #endif 339 340 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 341 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0) 342 343 #define BUILDIO_IOPORT(bwlq, type) \ 344 __BUILD_IOPORT_PFX(_, bwlq, type) \ 345 __BUILD_IOPORT_PFX(__mem_, bwlq, type) 346 347 BUILDIO_IOPORT(b, u8) 348 BUILDIO_IOPORT(w, u16) 349 BUILDIO_IOPORT(l, u32) 350 #ifdef CONFIG_64BIT 351 BUILDIO_IOPORT(q, u64) 352 #endif 353 354 #define __BUILDIO(bwlq, type) \ 355 \ 356 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0) 357 358 __BUILDIO(q, u64) 359 360 #define readb_relaxed __relaxed_readb 361 #define readw_relaxed __relaxed_readw 362 #define readl_relaxed __relaxed_readl 363 #ifdef CONFIG_64BIT 364 #define readq_relaxed __relaxed_readq 365 #endif 366 367 #define writeb_relaxed __relaxed_writeb 368 #define writew_relaxed __relaxed_writew 369 #define writel_relaxed __relaxed_writel 370 #ifdef CONFIG_64BIT 371 #define writeq_relaxed __relaxed_writeq 372 #endif 373 374 #define readb_be(addr) \ 375 __raw_readb((__force unsigned *)(addr)) 376 #define readw_be(addr) \ 377 be16_to_cpu(__raw_readw((__force unsigned *)(addr))) 378 #define readl_be(addr) \ 379 be32_to_cpu(__raw_readl((__force unsigned *)(addr))) 380 #define readq_be(addr) \ 381 be64_to_cpu(__raw_readq((__force unsigned *)(addr))) 382 383 #define writeb_be(val, addr) \ 384 __raw_writeb((val), (__force unsigned *)(addr)) 385 #define writew_be(val, addr) \ 386 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) 387 #define writel_be(val, addr) \ 388 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) 389 #define writeq_be(val, addr) \ 390 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) 391 392 #define __BUILD_MEMORY_STRING(bwlq, type) \ 393 \ 394 static inline void writes##bwlq(volatile void __iomem *mem, \ 395 const void *addr, unsigned int count) \ 396 { \ 397 const volatile type *__addr = addr; \ 398 \ 399 while (count--) { \ 400 __mem_write##bwlq(*__addr, mem); \ 401 __addr++; \ 402 } \ 403 } \ 404 \ 405 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 406 unsigned int count) \ 407 { \ 408 volatile type *__addr = addr; \ 409 \ 410 while (count--) { \ 411 *__addr = __mem_read##bwlq(mem); \ 412 __addr++; \ 413 } \ 414 } 415 416 #define __BUILD_IOPORT_STRING(bwlq, type) \ 417 \ 418 static inline void outs##bwlq(unsigned long port, const void *addr, \ 419 unsigned int count) \ 420 { \ 421 const volatile type *__addr = addr; \ 422 \ 423 while (count--) { \ 424 __mem_out##bwlq(*__addr, port); \ 425 __addr++; \ 426 } \ 427 } \ 428 \ 429 static inline void ins##bwlq(unsigned long port, void *addr, \ 430 unsigned int count) \ 431 { \ 432 volatile type *__addr = addr; \ 433 \ 434 while (count--) { \ 435 *__addr = __mem_in##bwlq(port); \ 436 __addr++; \ 437 } \ 438 } 439 440 #define BUILDSTRING(bwlq, type) \ 441 \ 442 __BUILD_MEMORY_STRING(bwlq, type) \ 443 __BUILD_IOPORT_STRING(bwlq, type) 444 445 BUILDSTRING(b, u8) 446 BUILDSTRING(w, u16) 447 BUILDSTRING(l, u32) 448 #ifdef CONFIG_64BIT 449 BUILDSTRING(q, u64) 450 #endif 451 452 453 /* 454 * The caches on some architectures aren't dma-coherent and have need to 455 * handle this in software. There are three types of operations that 456 * can be applied to dma buffers. 457 * 458 * - dma_cache_wback_inv(start, size) makes caches and coherent by 459 * writing the content of the caches back to memory, if necessary. 460 * The function also invalidates the affected part of the caches as 461 * necessary before DMA transfers from outside to memory. 462 * - dma_cache_wback(start, size) makes caches and coherent by 463 * writing the content of the caches back to memory, if necessary. 464 * The function also invalidates the affected part of the caches as 465 * necessary before DMA transfers from outside to memory. 466 * - dma_cache_inv(start, size) invalidates the affected parts of the 467 * caches. Dirty lines of the caches may be written back or simply 468 * be discarded. This operation is necessary before dma operations 469 * to the memory. 470 * 471 * This API used to be exported; it now is for arch code internal use only. 472 */ 473 #ifdef CONFIG_DMA_NONCOHERENT 474 475 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); 476 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); 477 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); 478 479 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) 480 #define dma_cache_wback(start, size) _dma_cache_wback(start, size) 481 #define dma_cache_inv(start, size) _dma_cache_inv(start, size) 482 483 #else /* Sane hardware */ 484 485 #define dma_cache_wback_inv(start,size) \ 486 do { (void) (start); (void) (size); } while (0) 487 #define dma_cache_wback(start,size) \ 488 do { (void) (start); (void) (size); } while (0) 489 #define dma_cache_inv(start,size) \ 490 do { (void) (start); (void) (size); } while (0) 491 492 #endif /* CONFIG_DMA_NONCOHERENT */ 493 494 /* 495 * Read a 32-bit register that requires a 64-bit read cycle on the bus. 496 * Avoid interrupt mucking, just adjust the address for 4-byte access. 497 * Assume the addresses are 8-byte aligned. 498 */ 499 #ifdef __MIPSEB__ 500 #define __CSR_32_ADJUST 4 501 #else 502 #define __CSR_32_ADJUST 0 503 #endif 504 505 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 506 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 507 508 #define __raw_readb __raw_readb 509 #define __raw_readw __raw_readw 510 #define __raw_readl __raw_readl 511 #ifdef CONFIG_64BIT 512 #define __raw_readq __raw_readq 513 #endif 514 #define __raw_writeb __raw_writeb 515 #define __raw_writew __raw_writew 516 #define __raw_writel __raw_writel 517 #ifdef CONFIG_64BIT 518 #define __raw_writeq __raw_writeq 519 #endif 520 521 #define readb readb 522 #define readw readw 523 #define readl readl 524 #ifdef CONFIG_64BIT 525 #define readq readq 526 #endif 527 #define writeb writeb 528 #define writew writew 529 #define writel writel 530 #ifdef CONFIG_64BIT 531 #define writeq writeq 532 #endif 533 534 #define readsb readsb 535 #define readsw readsw 536 #define readsl readsl 537 #ifdef CONFIG_64BIT 538 #define readsq readsq 539 #endif 540 #define writesb writesb 541 #define writesw writesw 542 #define writesl writesl 543 #ifdef CONFIG_64BIT 544 #define writesq writesq 545 #endif 546 547 #define _inb _inb 548 #define _inw _inw 549 #define _inl _inl 550 #define insb insb 551 #define insw insw 552 #define insl insl 553 554 #define _outb _outb 555 #define _outw _outw 556 #define _outl _outl 557 #define outsb outsb 558 #define outsw outsw 559 #define outsl outsl 560 561 void __ioread64_copy(void *to, const void __iomem *from, size_t count); 562 563 #include <asm-generic/io.h> 564 565 static inline void *isa_bus_to_virt(unsigned long address) 566 { 567 return phys_to_virt(address); 568 } 569 570 #endif /* _ASM_IO_H */ 571