1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <drm/ttm/ttm_tt.h> 32 #include <linux/module.h> 33 #include <linux/dma-buf.h> 34 #include "amdgpu_xgmi.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_ras.h" 37 #include "amdgpu_umc.h" 38 #include "amdgpu_reset.h" 39 40 /* Total memory size in system memory and all GPU VRAM. Used to 41 * estimate worst case amount of memory to reserve for page tables 42 */ 43 uint64_t amdgpu_amdkfd_total_mem_size; 44 45 static bool kfd_initialized; 46 47 int amdgpu_amdkfd_init(void) 48 { 49 struct sysinfo si; 50 int ret; 51 52 si_meminfo(&si); 53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 54 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 55 56 ret = kgd2kfd_init(); 57 kfd_initialized = !ret; 58 59 return ret; 60 } 61 62 void amdgpu_amdkfd_fini(void) 63 { 64 if (kfd_initialized) { 65 kgd2kfd_exit(); 66 kfd_initialized = false; 67 } 68 } 69 70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 71 { 72 bool vf = amdgpu_sriov_vf(adev); 73 74 if (!kfd_initialized) 75 return; 76 77 adev->kfd.dev = kgd2kfd_probe(adev, vf); 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_kernel_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->enable_mes) { 103 /* 104 * With MES enabled, we only need to initialize 105 * the base address. The size and offset are 106 * not initialized as AMDGPU manages the whole 107 * doorbell space. 108 */ 109 *aperture_base = adev->doorbell.base; 110 *aperture_size = 0; 111 *start_offset = 0; 112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 113 sizeof(u32)) { 114 *aperture_base = adev->doorbell.base; 115 *aperture_size = adev->doorbell.size; 116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 117 } else { 118 *aperture_base = 0; 119 *aperture_size = 0; 120 *start_offset = 0; 121 } 122 } 123 124 125 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 126 { 127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 128 kfd.reset_work); 129 130 struct amdgpu_reset_context reset_context; 131 132 memset(&reset_context, 0, sizeof(reset_context)); 133 134 reset_context.method = AMD_RESET_METHOD_NONE; 135 reset_context.reset_req_dev = adev; 136 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 137 138 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 139 } 140 141 static const struct drm_client_funcs kfd_client_funcs = { 142 .unregister = drm_client_release, 143 }; 144 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 145 { 146 int i; 147 int last_valid_bit; 148 int ret; 149 150 amdgpu_amdkfd_gpuvm_init_mem_limits(); 151 152 if (adev->kfd.dev) { 153 struct kgd2kfd_shared_resources gpu_resources = { 154 .compute_vmid_bitmap = 155 ((1 << AMDGPU_NUM_VMID) - 1) - 156 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 157 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 158 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 159 .gpuvm_size = min(adev->vm_manager.max_pfn 160 << AMDGPU_GPU_PAGE_SHIFT, 161 AMDGPU_GMC_HOLE_START), 162 .drm_render_minor = adev_to_drm(adev)->render->index, 163 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 164 .enable_mes = adev->enable_mes, 165 }; 166 167 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", &kfd_client_funcs); 168 if (ret) { 169 dev_err(adev->dev, "Failed to init DRM client: %d\n", ret); 170 return; 171 } 172 173 /* this is going to have a few of the MSBs set that we need to 174 * clear 175 */ 176 bitmap_complement(gpu_resources.cp_queue_bitmap, 177 adev->gfx.mec_bitmap[0].queue_bitmap, 178 AMDGPU_MAX_QUEUES); 179 180 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 181 * nbits is not compile time constant 182 */ 183 last_valid_bit = 1 /* only first MEC can have compute queues */ 184 * adev->gfx.mec.num_pipe_per_mec 185 * adev->gfx.mec.num_queue_per_pipe; 186 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i) 187 clear_bit(i, gpu_resources.cp_queue_bitmap); 188 189 amdgpu_doorbell_get_kfd_info(adev, 190 &gpu_resources.doorbell_physical_address, 191 &gpu_resources.doorbell_aperture_size, 192 &gpu_resources.doorbell_start_offset); 193 194 /* Since SOC15, BIF starts to statically use the 195 * lower 12 bits of doorbell addresses for routing 196 * based on settings in registers like 197 * SDMA0_DOORBELL_RANGE etc.. 198 * In order to route a doorbell to CP engine, the lower 199 * 12 bits of its address has to be outside the range 200 * set for SDMA, VCN, and IH blocks. 201 */ 202 if (adev->asic_type >= CHIP_VEGA10) { 203 gpu_resources.non_cp_doorbells_start = 204 adev->doorbell_index.first_non_cp; 205 gpu_resources.non_cp_doorbells_end = 206 adev->doorbell_index.last_non_cp; 207 } 208 209 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 210 &gpu_resources); 211 if (adev->kfd.init_complete) 212 drm_client_register(&adev->kfd.client); 213 else 214 drm_client_release(&adev->kfd.client); 215 216 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 217 218 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 219 } 220 } 221 222 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 223 { 224 if (adev->kfd.dev) { 225 kgd2kfd_device_exit(adev->kfd.dev); 226 adev->kfd.dev = NULL; 227 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 228 } 229 } 230 231 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 232 const void *ih_ring_entry) 233 { 234 if (adev->kfd.dev) 235 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 236 } 237 238 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 239 { 240 if (adev->kfd.dev) 241 kgd2kfd_suspend(adev->kfd.dev, run_pm); 242 } 243 244 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 245 { 246 int r = 0; 247 248 if (adev->kfd.dev) 249 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 250 251 return r; 252 } 253 254 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 255 { 256 int r = 0; 257 258 if (adev->kfd.dev) 259 r = kgd2kfd_pre_reset(adev->kfd.dev); 260 261 return r; 262 } 263 264 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 265 { 266 int r = 0; 267 268 if (adev->kfd.dev) 269 r = kgd2kfd_post_reset(adev->kfd.dev); 270 271 return r; 272 } 273 274 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 275 { 276 if (amdgpu_device_should_recover_gpu(adev)) 277 amdgpu_reset_domain_schedule(adev->reset_domain, 278 &adev->kfd.reset_work); 279 } 280 281 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 282 void **mem_obj, uint64_t *gpu_addr, 283 void **cpu_ptr, bool cp_mqd_gfx9) 284 { 285 struct amdgpu_bo *bo = NULL; 286 struct amdgpu_bo_param bp; 287 int r; 288 void *cpu_ptr_tmp = NULL; 289 290 memset(&bp, 0, sizeof(bp)); 291 bp.size = size; 292 bp.byte_align = PAGE_SIZE; 293 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 294 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 295 bp.type = ttm_bo_type_kernel; 296 bp.resv = NULL; 297 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 298 299 if (cp_mqd_gfx9) 300 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 301 302 r = amdgpu_bo_create(adev, &bp, &bo); 303 if (r) { 304 dev_err(adev->dev, 305 "failed to allocate BO for amdkfd (%d)\n", r); 306 return r; 307 } 308 309 /* map the buffer */ 310 r = amdgpu_bo_reserve(bo, true); 311 if (r) { 312 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 313 goto allocate_mem_reserve_bo_failed; 314 } 315 316 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 317 if (r) { 318 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 319 goto allocate_mem_pin_bo_failed; 320 } 321 322 r = amdgpu_ttm_alloc_gart(&bo->tbo); 323 if (r) { 324 dev_err(adev->dev, "%p bind failed\n", bo); 325 goto allocate_mem_kmap_bo_failed; 326 } 327 328 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 329 if (r) { 330 dev_err(adev->dev, 331 "(%d) failed to map bo to kernel for amdkfd\n", r); 332 goto allocate_mem_kmap_bo_failed; 333 } 334 335 *mem_obj = bo; 336 *gpu_addr = amdgpu_bo_gpu_offset(bo); 337 *cpu_ptr = cpu_ptr_tmp; 338 339 amdgpu_bo_unreserve(bo); 340 341 return 0; 342 343 allocate_mem_kmap_bo_failed: 344 amdgpu_bo_unpin(bo); 345 allocate_mem_pin_bo_failed: 346 amdgpu_bo_unreserve(bo); 347 allocate_mem_reserve_bo_failed: 348 amdgpu_bo_unref(&bo); 349 350 return r; 351 } 352 353 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj) 354 { 355 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 356 357 amdgpu_bo_reserve(bo, true); 358 amdgpu_bo_kunmap(bo); 359 amdgpu_bo_unpin(bo); 360 amdgpu_bo_unreserve(bo); 361 amdgpu_bo_unref(&(bo)); 362 } 363 364 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 365 void **mem_obj) 366 { 367 struct amdgpu_bo *bo = NULL; 368 struct amdgpu_bo_user *ubo; 369 struct amdgpu_bo_param bp; 370 int r; 371 372 memset(&bp, 0, sizeof(bp)); 373 bp.size = size; 374 bp.byte_align = 1; 375 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 376 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 377 bp.type = ttm_bo_type_device; 378 bp.resv = NULL; 379 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 380 381 r = amdgpu_bo_create_user(adev, &bp, &ubo); 382 if (r) { 383 dev_err(adev->dev, 384 "failed to allocate gws BO for amdkfd (%d)\n", r); 385 return r; 386 } 387 388 bo = &ubo->bo; 389 *mem_obj = bo; 390 return 0; 391 } 392 393 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 394 { 395 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 396 397 amdgpu_bo_unref(&bo); 398 } 399 400 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 401 enum kgd_engine_type type) 402 { 403 switch (type) { 404 case KGD_ENGINE_PFP: 405 return adev->gfx.pfp_fw_version; 406 407 case KGD_ENGINE_ME: 408 return adev->gfx.me_fw_version; 409 410 case KGD_ENGINE_CE: 411 return adev->gfx.ce_fw_version; 412 413 case KGD_ENGINE_MEC1: 414 return adev->gfx.mec_fw_version; 415 416 case KGD_ENGINE_MEC2: 417 return adev->gfx.mec2_fw_version; 418 419 case KGD_ENGINE_RLC: 420 return adev->gfx.rlc_fw_version; 421 422 case KGD_ENGINE_SDMA1: 423 return adev->sdma.instance[0].fw_version; 424 425 case KGD_ENGINE_SDMA2: 426 return adev->sdma.instance[1].fw_version; 427 428 default: 429 return 0; 430 } 431 432 return 0; 433 } 434 435 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 436 struct kfd_local_mem_info *mem_info, 437 struct amdgpu_xcp *xcp) 438 { 439 memset(mem_info, 0, sizeof(*mem_info)); 440 441 if (xcp) { 442 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 443 mem_info->local_mem_size_public = 444 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 445 else 446 mem_info->local_mem_size_private = 447 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 448 } else { 449 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 450 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 451 adev->gmc.visible_vram_size; 452 } 453 mem_info->vram_width = adev->gmc.vram_width; 454 455 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 456 &adev->gmc.aper_base, 457 mem_info->local_mem_size_public, 458 mem_info->local_mem_size_private); 459 460 if (adev->pm.dpm_enabled) { 461 if (amdgpu_emu_mode == 1) 462 mem_info->mem_clk_max = 0; 463 else 464 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 465 } else 466 mem_info->mem_clk_max = 100; 467 } 468 469 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 470 { 471 if (adev->gfx.funcs->get_gpu_clock_counter) 472 return adev->gfx.funcs->get_gpu_clock_counter(adev); 473 return 0; 474 } 475 476 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 477 { 478 /* the sclk is in quantas of 10kHz */ 479 if (adev->pm.dpm_enabled) 480 return amdgpu_dpm_get_sclk(adev, false) / 100; 481 else 482 return 100; 483 } 484 485 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 486 struct amdgpu_device **dmabuf_adev, 487 uint64_t *bo_size, void *metadata_buffer, 488 size_t buffer_size, uint32_t *metadata_size, 489 uint32_t *flags, int8_t *xcp_id) 490 { 491 struct dma_buf *dma_buf; 492 struct drm_gem_object *obj; 493 struct amdgpu_bo *bo; 494 uint64_t metadata_flags; 495 int r = -EINVAL; 496 497 dma_buf = dma_buf_get(dma_buf_fd); 498 if (IS_ERR(dma_buf)) 499 return PTR_ERR(dma_buf); 500 501 if (dma_buf->ops != &amdgpu_dmabuf_ops) 502 /* Can't handle non-graphics buffers */ 503 goto out_put; 504 505 obj = dma_buf->priv; 506 if (obj->dev->driver != adev_to_drm(adev)->driver) 507 /* Can't handle buffers from different drivers */ 508 goto out_put; 509 510 adev = drm_to_adev(obj->dev); 511 bo = gem_to_amdgpu_bo(obj); 512 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 513 AMDGPU_GEM_DOMAIN_GTT))) 514 /* Only VRAM and GTT BOs are supported */ 515 goto out_put; 516 517 r = 0; 518 if (dmabuf_adev) 519 *dmabuf_adev = adev; 520 if (bo_size) 521 *bo_size = amdgpu_bo_size(bo); 522 if (metadata_buffer) 523 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 524 metadata_size, &metadata_flags); 525 if (flags) { 526 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 527 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 528 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 529 530 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 531 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 532 } 533 if (xcp_id) 534 *xcp_id = bo->xcp_id; 535 536 out_put: 537 dma_buf_put(dma_buf); 538 return r; 539 } 540 541 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 542 struct amdgpu_device *src) 543 { 544 struct amdgpu_device *peer_adev = src; 545 struct amdgpu_device *adev = dst; 546 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 547 548 if (ret < 0) { 549 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 550 adev->gmc.xgmi.physical_node_id, 551 peer_adev->gmc.xgmi.physical_node_id, ret); 552 ret = 0; 553 } 554 return (uint8_t)ret; 555 } 556 557 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 558 struct amdgpu_device *src, 559 bool is_min) 560 { 561 struct amdgpu_device *adev = dst, *peer_adev; 562 int num_links; 563 564 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)) 565 return 0; 566 567 if (src) 568 peer_adev = src; 569 570 /* num links returns 0 for indirect peers since indirect route is unknown. */ 571 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 572 if (num_links < 0) { 573 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 574 adev->gmc.xgmi.physical_node_id, 575 peer_adev->gmc.xgmi.physical_node_id, num_links); 576 num_links = 0; 577 } 578 579 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 580 return (num_links * 16 * 25000)/BITS_PER_BYTE; 581 } 582 583 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 584 { 585 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 586 fls(adev->pm.pcie_mlw_mask)) - 1; 587 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 588 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 589 fls(adev->pm.pcie_gen_mask & 590 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 591 uint32_t num_lanes_mask = 1 << num_lanes_shift; 592 uint32_t gen_speed_mask = 1 << gen_speed_shift; 593 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 594 595 switch (num_lanes_mask) { 596 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 597 num_lanes_factor = 1; 598 break; 599 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 600 num_lanes_factor = 2; 601 break; 602 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 603 num_lanes_factor = 4; 604 break; 605 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 606 num_lanes_factor = 8; 607 break; 608 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 609 num_lanes_factor = 12; 610 break; 611 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 612 num_lanes_factor = 16; 613 break; 614 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 615 num_lanes_factor = 32; 616 break; 617 } 618 619 switch (gen_speed_mask) { 620 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 621 gen_speed_mbits_factor = 2500; 622 break; 623 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 624 gen_speed_mbits_factor = 5000; 625 break; 626 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 627 gen_speed_mbits_factor = 8000; 628 break; 629 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 630 gen_speed_mbits_factor = 16000; 631 break; 632 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 633 gen_speed_mbits_factor = 32000; 634 break; 635 } 636 637 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 638 } 639 640 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 641 enum kgd_engine_type engine, 642 uint32_t vmid, uint64_t gpu_addr, 643 uint32_t *ib_cmd, uint32_t ib_len) 644 { 645 struct amdgpu_job *job; 646 struct amdgpu_ib *ib; 647 struct amdgpu_ring *ring; 648 struct dma_fence *f = NULL; 649 int ret; 650 651 switch (engine) { 652 case KGD_ENGINE_MEC1: 653 ring = &adev->gfx.compute_ring[0]; 654 break; 655 case KGD_ENGINE_SDMA1: 656 ring = &adev->sdma.instance[0].ring; 657 break; 658 case KGD_ENGINE_SDMA2: 659 ring = &adev->sdma.instance[1].ring; 660 break; 661 default: 662 pr_err("Invalid engine in IB submission: %d\n", engine); 663 ret = -EINVAL; 664 goto err; 665 } 666 667 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job); 668 if (ret) 669 goto err; 670 671 ib = &job->ibs[0]; 672 memset(ib, 0, sizeof(struct amdgpu_ib)); 673 674 ib->gpu_addr = gpu_addr; 675 ib->ptr = ib_cmd; 676 ib->length_dw = ib_len; 677 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 678 job->vmid = vmid; 679 job->num_ibs = 1; 680 681 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 682 683 if (ret) { 684 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 685 goto err_ib_sched; 686 } 687 688 /* Drop the initial kref_init count (see drm_sched_main as example) */ 689 dma_fence_put(f); 690 ret = dma_fence_wait(f, false); 691 692 err_ib_sched: 693 amdgpu_job_free(job); 694 err: 695 return ret; 696 } 697 698 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 699 { 700 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE; 701 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && 702 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) { 703 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 704 amdgpu_gfx_off_ctrl(adev, idle); 705 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && 706 (adev->flags & AMD_IS_APU)) { 707 /* Disable GFXOFF and PG. Temporary workaround 708 * to fix some compute applications issue on GFX9. 709 */ 710 adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state); 711 } 712 amdgpu_dpm_switch_power_profile(adev, 713 PP_SMC_POWER_PROFILE_COMPUTE, 714 !idle); 715 } 716 717 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 718 { 719 if (adev->kfd.dev) 720 return vmid >= adev->vm_manager.first_kfd_vmid; 721 722 return false; 723 } 724 725 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 726 { 727 return adev->have_atomics_support; 728 } 729 730 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 731 { 732 amdgpu_device_flush_hdp(adev, NULL); 733 } 734 735 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) 736 { 737 amdgpu_umc_poison_handler(adev, reset); 738 } 739 740 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 741 uint32_t *payload) 742 { 743 int ret; 744 745 /* Device or IH ring is not ready so bail. */ 746 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 747 if (ret) 748 return ret; 749 750 /* Send payload to fence KFD interrupts */ 751 amdgpu_amdkfd_interrupt(adev, payload); 752 753 return 0; 754 } 755 756 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev) 757 { 758 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status) 759 return adev->gfx.ras->query_utcl2_poison_status(adev); 760 else 761 return false; 762 } 763 764 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 765 { 766 return kgd2kfd_check_and_lock_kfd(); 767 } 768 769 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 770 { 771 kgd2kfd_unlock_kfd(); 772 } 773 774 775 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 776 { 777 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 778 u64 tmp; 779 780 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 781 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { 782 /* In NPS1 mode, we should restrict the vram reporting 783 * tied to the ttm_pages_limit which is 1/2 of the system 784 * memory. For other partition modes, the HBM is uniformly 785 * divided already per numa node reported. If user wants to 786 * go beyond the default ttm limit and maximize the ROCm 787 * allocations, they can go up to max ttm and sysmem limits. 788 */ 789 790 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes(); 791 } else { 792 tmp = adev->gmc.mem_partitions[mem_id].size; 793 } 794 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 795 return ALIGN_DOWN(tmp, PAGE_SIZE); 796 } else { 797 return adev->gmc.real_vram_size; 798 } 799 } 800 801 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 802 u32 inst) 803 { 804 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 805 struct amdgpu_ring *kiq_ring = &kiq->ring; 806 struct amdgpu_ring_funcs *ring_funcs; 807 struct amdgpu_ring *ring; 808 int r = 0; 809 810 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 811 return -EINVAL; 812 813 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL); 814 if (!ring_funcs) 815 return -ENOMEM; 816 817 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 818 if (!ring) { 819 r = -ENOMEM; 820 goto free_ring_funcs; 821 } 822 823 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 824 ring->doorbell_index = doorbell_off; 825 ring->funcs = ring_funcs; 826 827 spin_lock(&kiq->ring_lock); 828 829 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 830 spin_unlock(&kiq->ring_lock); 831 r = -ENOMEM; 832 goto free_ring; 833 } 834 835 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 836 837 if (kiq_ring->sched.ready && !adev->job_hang) 838 r = amdgpu_ring_test_helper(kiq_ring); 839 840 spin_unlock(&kiq->ring_lock); 841 842 free_ring: 843 kfree(ring); 844 845 free_ring_funcs: 846 kfree(ring_funcs); 847 848 return r; 849 } 850