1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifer being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 62 * match only a single modifier. A modifier must not be a subset of layouts of 63 * another modifier. For instance, it's incorrect to encode pitch alignment in 64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 65 * aligned modifier. That said, modifiers can have implicit minimal 66 * requirements. 67 * 68 * For modifiers where the combination of fourcc code and modifier can alias, 69 * a canonical pair needs to be defined and used by all drivers. Preferred 70 * combinations are also encouraged where all combinations might lead to 71 * confusion and unnecessarily reduced interoperability. An example for the 72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 73 * 74 * There are two kinds of modifier users: 75 * 76 * - Kernel and user-space drivers: for drivers it's important that modifiers 77 * don't alias, otherwise two drivers might support the same format but use 78 * different aliases, preventing them from sharing buffers in an efficient 79 * format. 80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 81 * see modifiers as opaque tokens they can check for equality and intersect. 82 * These users musn't need to know to reason about the modifier value 83 * (i.e. they are not expected to extract information out of the modifier). 84 * 85 * Vendors should document their modifier usage in as much detail as 86 * possible, to ensure maximum compatibility across devices, drivers and 87 * applications. 88 * 89 * The authoritative list of format modifier codes is found in 90 * `include/uapi/drm/drm_fourcc.h` 91 */ 92 93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 94 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 95 96 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 97 98 /* Reserve 0 for the invalid format specifier */ 99 #define DRM_FORMAT_INVALID 0 100 101 /* color index */ 102 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ 103 #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ 104 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ 105 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 106 107 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */ 108 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ 109 110 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */ 111 #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */ 112 113 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */ 114 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ 115 116 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */ 117 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ 118 119 /* 1 bpp Red (direct relationship between channel value and brightness) */ 120 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ 121 122 /* 2 bpp Red (direct relationship between channel value and brightness) */ 123 #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */ 124 125 /* 4 bpp Red (direct relationship between channel value and brightness) */ 126 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ 127 128 /* 8 bpp Red (direct relationship between channel value and brightness) */ 129 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 130 131 /* 10 bpp Red (direct relationship between channel value and brightness) */ 132 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 133 134 /* 12 bpp Red (direct relationship between channel value and brightness) */ 135 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 136 137 /* 16 bpp Red (direct relationship between channel value and brightness) */ 138 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 139 140 /* 16 bpp RG */ 141 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 142 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 143 144 /* 32 bpp RG */ 145 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 146 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 147 148 /* 8 bpp RGB */ 149 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 150 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 151 152 /* 16 bpp RGB */ 153 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 154 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 155 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 156 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 157 158 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 159 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 160 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 161 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 162 163 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 164 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 165 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 166 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 167 168 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 169 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 170 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 171 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 172 173 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 174 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 175 176 /* 24 bpp RGB */ 177 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 178 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 179 180 /* 32 bpp RGB */ 181 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 182 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 183 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 184 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 185 186 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 187 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 188 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 189 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 190 191 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 192 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 193 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 194 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 195 196 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 197 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 198 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 199 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 200 201 /* 64 bpp RGB */ 202 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 203 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 204 205 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 206 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 207 208 /* 209 * Floating point 64bpp RGB 210 * IEEE 754-2008 binary16 half-precision float 211 * [15:0] sign:exponent:mantissa 1:5:10 212 */ 213 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 214 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 215 216 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 217 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 218 219 /* 220 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 221 * of unused padding per component: 222 */ 223 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 224 225 /* packed YCbCr */ 226 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 227 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 228 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 229 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 230 231 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 232 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ 233 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 234 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ 235 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 236 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 237 238 /* 239 * packed Y2xx indicate for each component, xx valid data occupy msb 240 * 16-xx padding occupy lsb 241 */ 242 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 243 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 244 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 245 246 /* 247 * packed Y4xx indicate for each component, xx valid data occupy msb 248 * 16-xx padding occupy lsb except Y410 249 */ 250 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 251 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 252 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 253 254 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 255 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 256 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 257 258 /* 259 * packed YCbCr420 2x2 tiled formats 260 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 261 */ 262 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 263 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 264 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 265 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 266 267 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 268 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 269 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 270 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 271 272 /* 273 * 1-plane YUV 4:2:0 274 * In these formats, the component ordering is specified (Y, followed by U 275 * then V), but the exact Linear layout is undefined. 276 * These formats can only be used with a non-Linear modifier. 277 */ 278 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 279 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 280 281 /* 282 * 2 plane RGB + A 283 * index 0 = RGB plane, same format as the corresponding non _A8 format has 284 * index 1 = A plane, [7:0] A 285 */ 286 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 287 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 288 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 289 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 290 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 291 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 292 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 293 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 294 295 /* 296 * 2 plane YCbCr 297 * index 0 = Y plane, [7:0] Y 298 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 299 * or 300 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 301 */ 302 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 303 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 304 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 305 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 306 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 307 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 308 /* 309 * 2 plane YCbCr 310 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 311 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 312 */ 313 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 314 315 /* 316 * 2 plane YCbCr MSB aligned 317 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 318 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 319 */ 320 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 321 322 /* 323 * 2 plane YCbCr MSB aligned 324 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 325 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 326 */ 327 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 328 329 /* 330 * 2 plane YCbCr MSB aligned 331 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 332 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 333 */ 334 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 335 336 /* 337 * 2 plane YCbCr MSB aligned 338 * index 0 = Y plane, [15:0] Y little endian 339 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 340 */ 341 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 342 343 /* 2 plane YCbCr420. 344 * 3 10 bit components and 2 padding bits packed into 4 bytes. 345 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian 346 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian 347 */ 348 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ 349 350 /* 3 plane non-subsampled (444) YCbCr 351 * 16 bits per component, but only 10 bits are used and 6 bits are padded 352 * index 0: Y plane, [15:0] Y:x [10:6] little endian 353 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 354 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 355 */ 356 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 357 358 /* 3 plane non-subsampled (444) YCrCb 359 * 16 bits per component, but only 10 bits are used and 6 bits are padded 360 * index 0: Y plane, [15:0] Y:x [10:6] little endian 361 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 362 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 363 */ 364 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 365 366 /* 367 * 3 plane YCbCr 368 * index 0: Y plane, [7:0] Y 369 * index 1: Cb plane, [7:0] Cb 370 * index 2: Cr plane, [7:0] Cr 371 * or 372 * index 1: Cr plane, [7:0] Cr 373 * index 2: Cb plane, [7:0] Cb 374 */ 375 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 376 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 377 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 378 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 379 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 380 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 381 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 382 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 383 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 384 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 385 386 387 /* 388 * Format Modifiers: 389 * 390 * Format modifiers describe, typically, a re-ordering or modification 391 * of the data in a plane of an FB. This can be used to express tiled/ 392 * swizzled formats, or compression, or a combination of the two. 393 * 394 * The upper 8 bits of the format modifier are a vendor-id as assigned 395 * below. The lower 56 bits are assigned as vendor sees fit. 396 */ 397 398 /* Vendor Ids: */ 399 #define DRM_FORMAT_MOD_VENDOR_NONE 0 400 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 401 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 402 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 403 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 404 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 405 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 406 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 407 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 408 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 409 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 410 411 /* add more to the end as needed */ 412 413 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 414 415 #define fourcc_mod_get_vendor(modifier) \ 416 (((modifier) >> 56) & 0xff) 417 418 #define fourcc_mod_is_vendor(modifier, vendor) \ 419 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 420 421 #define fourcc_mod_code(vendor, val) \ 422 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 423 424 /* 425 * Format Modifier tokens: 426 * 427 * When adding a new token please document the layout with a code comment, 428 * similar to the fourcc codes above. drm_fourcc.h is considered the 429 * authoritative source for all of these. 430 * 431 * Generic modifier names: 432 * 433 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 434 * for layouts which are common across multiple vendors. To preserve 435 * compatibility, in cases where a vendor-specific definition already exists and 436 * a generic name for it is desired, the common name is a purely symbolic alias 437 * and must use the same numerical value as the original definition. 438 * 439 * Note that generic names should only be used for modifiers which describe 440 * generic layouts (such as pixel re-ordering), which may have 441 * independently-developed support across multiple vendors. 442 * 443 * In future cases where a generic layout is identified before merging with a 444 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 445 * 'NONE' could be considered. This should only be for obvious, exceptional 446 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 447 * apply to a single vendor. 448 * 449 * Generic names should not be used for cases where multiple hardware vendors 450 * have implementations of the same standardised compression scheme (such as 451 * AFBC). In those cases, all implementations should use the same format 452 * modifier(s), reflecting the vendor of the standard. 453 */ 454 455 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 456 457 /* 458 * Invalid Modifier 459 * 460 * This modifier can be used as a sentinel to terminate the format modifiers 461 * list, or to initialize a variable with an invalid modifier. It might also be 462 * used to report an error back to userspace for certain APIs. 463 */ 464 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 465 466 /* 467 * Linear Layout 468 * 469 * Just plain linear layout. Note that this is different from no specifying any 470 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 471 * which tells the driver to also take driver-internal information into account 472 * and so might actually result in a tiled framebuffer. 473 */ 474 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 475 476 /* 477 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 478 * 479 * The "none" format modifier doesn't actually mean that the modifier is 480 * implicit, instead it means that the layout is linear. Whether modifiers are 481 * used is out-of-band information carried in an API-specific way (e.g. in a 482 * flag for drm_mode_fb_cmd2). 483 */ 484 #define DRM_FORMAT_MOD_NONE 0 485 486 /* Intel framebuffer modifiers */ 487 488 /* 489 * Intel X-tiling layout 490 * 491 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 492 * in row-major layout. Within the tile bytes are laid out row-major, with 493 * a platform-dependent stride. On top of that the memory can apply 494 * platform-depending swizzling of some higher address bits into bit6. 495 * 496 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 497 * On earlier platforms the is highly platforms specific and not useful for 498 * cross-driver sharing. It exists since on a given platform it does uniquely 499 * identify the layout in a simple way for i915-specific userspace, which 500 * facilitated conversion of userspace to modifiers. Additionally the exact 501 * format on some really old platforms is not known. 502 */ 503 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 504 505 /* 506 * Intel Y-tiling layout 507 * 508 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 509 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 510 * chunks column-major, with a platform-dependent height. On top of that the 511 * memory can apply platform-depending swizzling of some higher address bits 512 * into bit6. 513 * 514 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 515 * On earlier platforms the is highly platforms specific and not useful for 516 * cross-driver sharing. It exists since on a given platform it does uniquely 517 * identify the layout in a simple way for i915-specific userspace, which 518 * facilitated conversion of userspace to modifiers. Additionally the exact 519 * format on some really old platforms is not known. 520 */ 521 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 522 523 /* 524 * Intel Yf-tiling layout 525 * 526 * This is a tiled layout using 4Kb tiles in row-major layout. 527 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 528 * are arranged in four groups (two wide, two high) with column-major layout. 529 * Each group therefore consits out of four 256 byte units, which are also laid 530 * out as 2x2 column-major. 531 * 256 byte units are made out of four 64 byte blocks of pixels, producing 532 * either a square block or a 2:1 unit. 533 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 534 * in pixel depends on the pixel depth. 535 */ 536 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 537 538 /* 539 * Intel color control surface (CCS) for render compression 540 * 541 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 542 * The main surface will be plane index 0 and must be Y/Yf-tiled, 543 * the CCS will be plane index 1. 544 * 545 * Each CCS tile matches a 1024x512 pixel area of the main surface. 546 * To match certain aspects of the 3D hardware the CCS is 547 * considered to be made up of normal 128Bx32 Y tiles, Thus 548 * the CCS pitch must be specified in multiples of 128 bytes. 549 * 550 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 551 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 552 * But that fact is not relevant unless the memory is accessed 553 * directly. 554 */ 555 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 556 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 557 558 /* 559 * Intel color control surfaces (CCS) for Gen-12 render compression. 560 * 561 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 562 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 563 * main surface. In other words, 4 bits in CCS map to a main surface cache 564 * line pair. The main surface pitch is required to be a multiple of four 565 * Y-tile widths. 566 */ 567 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 568 569 /* 570 * Intel color control surfaces (CCS) for Gen-12 media compression 571 * 572 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 573 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 574 * main surface. In other words, 4 bits in CCS map to a main surface cache 575 * line pair. The main surface pitch is required to be a multiple of four 576 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 577 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 578 * planes 2 and 3 for the respective CCS. 579 */ 580 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 581 582 /* 583 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 584 * compression. 585 * 586 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 587 * and at index 1. The clear color is stored at index 2, and the pitch should 588 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits 589 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 590 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 591 * the converted clear color of size 64 bits. The first 32 bits store the Lower 592 * Converted Clear Color value and the next 32 bits store the Higher Converted 593 * Clear Color value when applicable. The Converted Clear Color values are 594 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 595 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 596 * corresponds to an area of 4x1 tiles in the main surface. The main surface 597 * pitch is required to be a multiple of 4 tile widths. 598 */ 599 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 600 601 /* 602 * Intel Tile 4 layout 603 * 604 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same 605 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It 606 * only differs from Tile Y at the 256B granularity in between. At this 607 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape 608 * of 64B x 8 rows. 609 */ 610 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) 611 612 /* 613 * Intel color control surfaces (CCS) for DG2 render compression. 614 * 615 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 616 * outside of the GEM object in a reserved memory area dedicated for the 617 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 618 * main surface pitch is required to be a multiple of four Tile 4 widths. 619 */ 620 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) 621 622 /* 623 * Intel color control surfaces (CCS) for DG2 media compression. 624 * 625 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 626 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 627 * 0 and 1, respectively. The CCS for all planes are stored outside of the 628 * GEM object in a reserved memory area dedicated for the storage of the 629 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface 630 * pitch is required to be a multiple of four Tile 4 widths. 631 */ 632 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) 633 634 /* 635 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. 636 * 637 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 638 * outside of the GEM object in a reserved memory area dedicated for the 639 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 640 * main surface pitch is required to be a multiple of four Tile 4 widths. The 641 * clear color is stored at plane index 1 and the pitch should be 64 bytes 642 * aligned. The format of the 256 bits of clear color data matches the one used 643 * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description 644 * for details. 645 */ 646 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) 647 648 /* 649 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 650 * 651 * Macroblocks are laid in a Z-shape, and each pixel data is following the 652 * standard NV12 style. 653 * As for NV12, an image is the result of two frame buffers: one for Y, 654 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 655 * Alignment requirements are (for each buffer): 656 * - multiple of 128 pixels for the width 657 * - multiple of 32 pixels for the height 658 * 659 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 660 */ 661 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 662 663 /* 664 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 665 * 666 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 667 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 668 * they correspond to their 16x16 luma block. 669 */ 670 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 671 672 /* 673 * Qualcomm Compressed Format 674 * 675 * Refers to a compressed variant of the base format that is compressed. 676 * Implementation may be platform and base-format specific. 677 * 678 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 679 * Pixel data pitch/stride is aligned with macrotile width. 680 * Pixel data height is aligned with macrotile height. 681 * Entire pixel data buffer is aligned with 4k(bytes). 682 */ 683 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 684 685 /* 686 * Qualcomm Tiled Format 687 * 688 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed. 689 * Implementation may be platform and base-format specific. 690 * 691 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 692 * Pixel data pitch/stride is aligned with macrotile width. 693 * Pixel data height is aligned with macrotile height. 694 * Entire pixel data buffer is aligned with 4k(bytes). 695 */ 696 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3) 697 698 /* 699 * Qualcomm Alternate Tiled Format 700 * 701 * Alternate tiled format typically only used within GMEM. 702 * Implementation may be platform and base-format specific. 703 */ 704 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2) 705 706 707 /* Vivante framebuffer modifiers */ 708 709 /* 710 * Vivante 4x4 tiling layout 711 * 712 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 713 * layout. 714 */ 715 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 716 717 /* 718 * Vivante 64x64 super-tiling layout 719 * 720 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 721 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 722 * major layout. 723 * 724 * For more information: see 725 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 726 */ 727 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 728 729 /* 730 * Vivante 4x4 tiling layout for dual-pipe 731 * 732 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 733 * different base address. Offsets from the base addresses are therefore halved 734 * compared to the non-split tiled layout. 735 */ 736 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 737 738 /* 739 * Vivante 64x64 super-tiling layout for dual-pipe 740 * 741 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 742 * starts at a different base address. Offsets from the base addresses are 743 * therefore halved compared to the non-split super-tiled layout. 744 */ 745 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 746 747 /* NVIDIA frame buffer modifiers */ 748 749 /* 750 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 751 * 752 * Pixels are arranged in simple tiles of 16 x 16 bytes. 753 */ 754 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 755 756 /* 757 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 758 * and Tegra GPUs starting with Tegra K1. 759 * 760 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 761 * based on the architecture generation. GOBs themselves are then arranged in 762 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 763 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 764 * a block depth or height of "4"). 765 * 766 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 767 * in full detail. 768 * 769 * Macro 770 * Bits Param Description 771 * ---- ----- ----------------------------------------------------------------- 772 * 773 * 3:0 h log2(height) of each block, in GOBs. Placed here for 774 * compatibility with the existing 775 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 776 * 777 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 778 * compatibility with the existing 779 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 780 * 781 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 782 * size). Must be zero. 783 * 784 * Note there is no log2(width) parameter. Some portions of the 785 * hardware support a block width of two gobs, but it is impractical 786 * to use due to lack of support elsewhere, and has no known 787 * benefits. 788 * 789 * 11:9 - Reserved (To support 2D-array textures with variable array stride 790 * in blocks, specified via log2(tile width in blocks)). Must be 791 * zero. 792 * 793 * 19:12 k Page Kind. This value directly maps to a field in the page 794 * tables of all GPUs >= NV50. It affects the exact layout of bits 795 * in memory and can be derived from the tuple 796 * 797 * (format, GPU model, compression type, samples per pixel) 798 * 799 * Where compression type is defined below. If GPU model were 800 * implied by the format modifier, format, or memory buffer, page 801 * kind would not need to be included in the modifier itself, but 802 * since the modifier should define the layout of the associated 803 * memory buffer independent from any device or other context, it 804 * must be included here. 805 * 806 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 807 * starting with Fermi GPUs. Additionally, the mapping between page 808 * kind and bit layout has changed at various points. 809 * 810 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 811 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 812 * 2 = Gob Height 8, Turing+ Page Kind mapping 813 * 3 = Reserved for future use. 814 * 815 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 816 * bit remapping step that occurs at an even lower level than the 817 * page kind and block linear swizzles. This causes the layout of 818 * surfaces mapped in those SOC's GPUs to be incompatible with the 819 * equivalent mapping on other GPUs in the same system. 820 * 821 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 822 * 1 = Desktop GPU and Tegra Xavier+ Layout 823 * 824 * 25:23 c Lossless Framebuffer Compression type. 825 * 826 * 0 = none 827 * 1 = ROP/3D, layout 1, exact compression format implied by Page 828 * Kind field 829 * 2 = ROP/3D, layout 2, exact compression format implied by Page 830 * Kind field 831 * 3 = CDE horizontal 832 * 4 = CDE vertical 833 * 5 = Reserved for future use 834 * 6 = Reserved for future use 835 * 7 = Reserved for future use 836 * 837 * 55:25 - Reserved for future use. Must be zero. 838 */ 839 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 840 fourcc_mod_code(NVIDIA, (0x10 | \ 841 ((h) & 0xf) | \ 842 (((k) & 0xff) << 12) | \ 843 (((g) & 0x3) << 20) | \ 844 (((s) & 0x1) << 22) | \ 845 (((c) & 0x7) << 23))) 846 847 /* To grandfather in prior block linear format modifiers to the above layout, 848 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 849 * with block-linear layouts, is remapped within drivers to the value 0xfe, 850 * which corresponds to the "generic" kind used for simple single-sample 851 * uncompressed color formats on Fermi - Volta GPUs. 852 */ 853 static inline __u64 854 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 855 { 856 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 857 return modifier; 858 else 859 return modifier | (0xfe << 12); 860 } 861 862 /* 863 * 16Bx2 Block Linear layout, used by Tegra K1 and later 864 * 865 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 866 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 867 * 868 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 869 * 870 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 871 * Valid values are: 872 * 873 * 0 == ONE_GOB 874 * 1 == TWO_GOBS 875 * 2 == FOUR_GOBS 876 * 3 == EIGHT_GOBS 877 * 4 == SIXTEEN_GOBS 878 * 5 == THIRTYTWO_GOBS 879 * 880 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 881 * in full detail. 882 */ 883 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 884 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 885 886 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 887 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 888 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 889 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 890 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 891 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 892 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 893 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 894 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 895 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 896 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 897 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 898 899 /* 900 * Some Broadcom modifiers take parameters, for example the number of 901 * vertical lines in the image. Reserve the lower 32 bits for modifier 902 * type, and the next 24 bits for parameters. Top 8 bits are the 903 * vendor code. 904 */ 905 #define __fourcc_mod_broadcom_param_shift 8 906 #define __fourcc_mod_broadcom_param_bits 48 907 #define fourcc_mod_broadcom_code(val, params) \ 908 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 909 #define fourcc_mod_broadcom_param(m) \ 910 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 911 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 912 #define fourcc_mod_broadcom_mod(m) \ 913 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 914 __fourcc_mod_broadcom_param_shift)) 915 916 /* 917 * Broadcom VC4 "T" format 918 * 919 * This is the primary layout that the V3D GPU can texture from (it 920 * can't do linear). The T format has: 921 * 922 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 923 * pixels at 32 bit depth. 924 * 925 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 926 * 16x16 pixels). 927 * 928 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 929 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 930 * they're (TR, BR, BL, TL), where bottom left is start of memory. 931 * 932 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 933 * tiles) or right-to-left (odd rows of 4k tiles). 934 */ 935 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 936 937 /* 938 * Broadcom SAND format 939 * 940 * This is the native format that the H.264 codec block uses. For VC4 941 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 942 * 943 * The image can be considered to be split into columns, and the 944 * columns are placed consecutively into memory. The width of those 945 * columns can be either 32, 64, 128, or 256 pixels, but in practice 946 * only 128 pixel columns are used. 947 * 948 * The pitch between the start of each column is set to optimally 949 * switch between SDRAM banks. This is passed as the number of lines 950 * of column width in the modifier (we can't use the stride value due 951 * to various core checks that look at it , so you should set the 952 * stride to width*cpp). 953 * 954 * Note that the column height for this format modifier is the same 955 * for all of the planes, assuming that each column contains both Y 956 * and UV. Some SAND-using hardware stores UV in a separate tiled 957 * image from Y to reduce the column height, which is not supported 958 * with these modifiers. 959 * 960 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also 961 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes 962 * wide, but as this is a 10 bpp format that translates to 96 pixels. 963 */ 964 965 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 966 fourcc_mod_broadcom_code(2, v) 967 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 968 fourcc_mod_broadcom_code(3, v) 969 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 970 fourcc_mod_broadcom_code(4, v) 971 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 972 fourcc_mod_broadcom_code(5, v) 973 974 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 975 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 976 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 977 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 978 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 979 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 980 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 981 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 982 983 /* Broadcom UIF format 984 * 985 * This is the common format for the current Broadcom multimedia 986 * blocks, including V3D 3.x and newer, newer video codecs, and 987 * displays. 988 * 989 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 990 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 991 * stored in columns, with padding between the columns to ensure that 992 * moving from one column to the next doesn't hit the same SDRAM page 993 * bank. 994 * 995 * To calculate the padding, it is assumed that each hardware block 996 * and the software driving it knows the platform's SDRAM page size, 997 * number of banks, and XOR address, and that it's identical between 998 * all blocks using the format. This tiling modifier will use XOR as 999 * necessary to reduce the padding. If a hardware block can't do XOR, 1000 * the assumption is that a no-XOR tiling modifier will be created. 1001 */ 1002 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 1003 1004 /* 1005 * Arm Framebuffer Compression (AFBC) modifiers 1006 * 1007 * AFBC is a proprietary lossless image compression protocol and format. 1008 * It provides fine-grained random access and minimizes the amount of data 1009 * transferred between IP blocks. 1010 * 1011 * AFBC has several features which may be supported and/or used, which are 1012 * represented using bits in the modifier. Not all combinations are valid, 1013 * and different devices or use-cases may support different combinations. 1014 * 1015 * Further information on the use of AFBC modifiers can be found in 1016 * Documentation/gpu/afbc.rst 1017 */ 1018 1019 /* 1020 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 1021 * modifiers) denote the category for modifiers. Currently we have three 1022 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 1023 * sixteen different categories. 1024 */ 1025 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 1026 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 1027 1028 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 1029 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 1030 1031 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 1032 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 1033 1034 /* 1035 * AFBC superblock size 1036 * 1037 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 1038 * size (in pixels) must be aligned to a multiple of the superblock size. 1039 * Four lowest significant bits(LSBs) are reserved for block size. 1040 * 1041 * Where one superblock size is specified, it applies to all planes of the 1042 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 1043 * the first applies to the Luma plane and the second applies to the Chroma 1044 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 1045 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 1046 */ 1047 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 1048 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 1049 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 1050 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 1051 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 1052 1053 /* 1054 * AFBC lossless colorspace transform 1055 * 1056 * Indicates that the buffer makes use of the AFBC lossless colorspace 1057 * transform. 1058 */ 1059 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 1060 1061 /* 1062 * AFBC block-split 1063 * 1064 * Indicates that the payload of each superblock is split. The second 1065 * half of the payload is positioned at a predefined offset from the start 1066 * of the superblock payload. 1067 */ 1068 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 1069 1070 /* 1071 * AFBC sparse layout 1072 * 1073 * This flag indicates that the payload of each superblock must be stored at a 1074 * predefined position relative to the other superblocks in the same AFBC 1075 * buffer. This order is the same order used by the header buffer. In this mode 1076 * each superblock is given the same amount of space as an uncompressed 1077 * superblock of the particular format would require, rounding up to the next 1078 * multiple of 128 bytes in size. 1079 */ 1080 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 1081 1082 /* 1083 * AFBC copy-block restrict 1084 * 1085 * Buffers with this flag must obey the copy-block restriction. The restriction 1086 * is such that there are no copy-blocks referring across the border of 8x8 1087 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 1088 */ 1089 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 1090 1091 /* 1092 * AFBC tiled layout 1093 * 1094 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 1095 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 1096 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 1097 * larger bpp formats. The order between the tiles is scan line. 1098 * When the tiled layout is used, the buffer size (in pixels) must be aligned 1099 * to the tile size. 1100 */ 1101 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 1102 1103 /* 1104 * AFBC solid color blocks 1105 * 1106 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1107 * can be reduced if a whole superblock is a single color. 1108 */ 1109 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1110 1111 /* 1112 * AFBC double-buffer 1113 * 1114 * Indicates that the buffer is allocated in a layout safe for front-buffer 1115 * rendering. 1116 */ 1117 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1118 1119 /* 1120 * AFBC buffer content hints 1121 * 1122 * Indicates that the buffer includes per-superblock content hints. 1123 */ 1124 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1125 1126 /* AFBC uncompressed storage mode 1127 * 1128 * Indicates that the buffer is using AFBC uncompressed storage mode. 1129 * In this mode all superblock payloads in the buffer use the uncompressed 1130 * storage mode, which is usually only used for data which cannot be compressed. 1131 * The buffer layout is the same as for AFBC buffers without USM set, this only 1132 * affects the storage mode of the individual superblocks. Note that even a 1133 * buffer without USM set may use uncompressed storage mode for some or all 1134 * superblocks, USM just guarantees it for all. 1135 */ 1136 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1137 1138 /* 1139 * Arm Fixed-Rate Compression (AFRC) modifiers 1140 * 1141 * AFRC is a proprietary fixed rate image compression protocol and format, 1142 * designed to provide guaranteed bandwidth and memory footprint 1143 * reductions in graphics and media use-cases. 1144 * 1145 * AFRC buffers consist of one or more planes, with the same components 1146 * and meaning as an uncompressed buffer using the same pixel format. 1147 * 1148 * Within each plane, the pixel/luma/chroma values are grouped into 1149 * "coding unit" blocks which are individually compressed to a 1150 * fixed size (in bytes). All coding units within a given plane of a buffer 1151 * store the same number of values, and have the same compressed size. 1152 * 1153 * The coding unit size is configurable, allowing different rates of compression. 1154 * 1155 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1156 * depends on the coding unit size. 1157 * 1158 * Coding Unit Size Plane Alignment 1159 * ---------------- --------------- 1160 * 16 bytes 1024 bytes 1161 * 24 bytes 512 bytes 1162 * 32 bytes 2048 bytes 1163 * 1164 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1165 * to a multiple of the paging tile dimensions. 1166 * The dimensions of each paging tile depend on whether the buffer is optimised for 1167 * scanline (SCAN layout) or rotated (ROT layout) access. 1168 * 1169 * Layout Paging Tile Width Paging Tile Height 1170 * ------ ----------------- ------------------ 1171 * SCAN 16 coding units 4 coding units 1172 * ROT 8 coding units 8 coding units 1173 * 1174 * The dimensions of each coding unit depend on the number of components 1175 * in the compressed plane and whether the buffer is optimised for 1176 * scanline (SCAN layout) or rotated (ROT layout) access. 1177 * 1178 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1179 * ----------------------------- --------- ----------------- ------------------ 1180 * 1 SCAN 16 samples 4 samples 1181 * Example: 16x4 luma samples in a 'Y' plane 1182 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1183 * ----------------------------- --------- ----------------- ------------------ 1184 * 1 ROT 8 samples 8 samples 1185 * Example: 8x8 luma samples in a 'Y' plane 1186 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1187 * ----------------------------- --------- ----------------- ------------------ 1188 * 2 DONT CARE 8 samples 4 samples 1189 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1190 * ----------------------------- --------- ----------------- ------------------ 1191 * 3 DONT CARE 4 samples 4 samples 1192 * Example: 4x4 pixels in an RGB buffer without alpha 1193 * ----------------------------- --------- ----------------- ------------------ 1194 * 4 DONT CARE 4 samples 4 samples 1195 * Example: 4x4 pixels in an RGB buffer with alpha 1196 */ 1197 1198 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1199 1200 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1201 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1202 1203 /* 1204 * AFRC coding unit size modifier. 1205 * 1206 * Indicates the number of bytes used to store each compressed coding unit for 1207 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1208 * is the same for both Cb and Cr, which may be stored in separate planes. 1209 * 1210 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1211 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1212 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1213 * this corresponds to the luma plane. 1214 * 1215 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1216 * each compressed coding unit in the second and third planes in the buffer. 1217 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1218 * 1219 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1220 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1221 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1222 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1223 */ 1224 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1225 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1226 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1227 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1228 1229 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1230 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1231 1232 /* 1233 * AFRC scanline memory layout. 1234 * 1235 * Indicates if the buffer uses the scanline-optimised layout 1236 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1237 * The memory layout is the same for all planes. 1238 */ 1239 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1240 1241 /* 1242 * Arm 16x16 Block U-Interleaved modifier 1243 * 1244 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1245 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1246 * in the block are reordered. 1247 */ 1248 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1249 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1250 1251 /* 1252 * Allwinner tiled modifier 1253 * 1254 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1255 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1256 * planes. 1257 * 1258 * With this tiling, the luminance samples are disposed in tiles representing 1259 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1260 * The pixel order in each tile is linear and the tiles are disposed linearly, 1261 * both in row-major order. 1262 */ 1263 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1264 1265 /* 1266 * Amlogic Video Framebuffer Compression modifiers 1267 * 1268 * Amlogic uses a proprietary lossless image compression protocol and format 1269 * for their hardware video codec accelerators, either video decoders or 1270 * video input encoders. 1271 * 1272 * It considerably reduces memory bandwidth while writing and reading 1273 * frames in memory. 1274 * 1275 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1276 * per component YCbCr 420, single plane : 1277 * - DRM_FORMAT_YUV420_8BIT 1278 * - DRM_FORMAT_YUV420_10BIT 1279 * 1280 * The first 8 bits of the mode defines the layout, then the following 8 bits 1281 * defines the options changing the layout. 1282 * 1283 * Not all combinations are valid, and different SoCs may support different 1284 * combinations of layout and options. 1285 */ 1286 #define __fourcc_mod_amlogic_layout_mask 0xff 1287 #define __fourcc_mod_amlogic_options_shift 8 1288 #define __fourcc_mod_amlogic_options_mask 0xff 1289 1290 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1291 fourcc_mod_code(AMLOGIC, \ 1292 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1293 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1294 << __fourcc_mod_amlogic_options_shift)) 1295 1296 /* Amlogic FBC Layouts */ 1297 1298 /* 1299 * Amlogic FBC Basic Layout 1300 * 1301 * The basic layout is composed of: 1302 * - a body content organized in 64x32 superblocks with 4096 bytes per 1303 * superblock in default mode. 1304 * - a 32 bytes per 128x64 header block 1305 * 1306 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1307 */ 1308 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1309 1310 /* 1311 * Amlogic FBC Scatter Memory layout 1312 * 1313 * Indicates the header contains IOMMU references to the compressed 1314 * frames content to optimize memory access and layout. 1315 * 1316 * In this mode, only the header memory address is needed, thus the 1317 * content memory organization is tied to the current producer 1318 * execution and cannot be saved/dumped neither transferrable between 1319 * Amlogic SoCs supporting this modifier. 1320 * 1321 * Due to the nature of the layout, these buffers are not expected to 1322 * be accessible by the user-space clients, but only accessible by the 1323 * hardware producers and consumers. 1324 * 1325 * The user-space clients should expect a failure while trying to mmap 1326 * the DMA-BUF handle returned by the producer. 1327 */ 1328 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1329 1330 /* Amlogic FBC Layout Options Bit Mask */ 1331 1332 /* 1333 * Amlogic FBC Memory Saving mode 1334 * 1335 * Indicates the storage is packed when pixel size is multiple of word 1336 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1337 * memory. 1338 * 1339 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1340 * the basic layout and 3200 bytes per 64x32 superblock combined with 1341 * the scatter layout. 1342 */ 1343 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1344 1345 /* 1346 * AMD modifiers 1347 * 1348 * Memory layout: 1349 * 1350 * without DCC: 1351 * - main surface 1352 * 1353 * with DCC & without DCC_RETILE: 1354 * - main surface in plane 0 1355 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1356 * 1357 * with DCC & DCC_RETILE: 1358 * - main surface in plane 0 1359 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1360 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1361 * 1362 * For multi-plane formats the above surfaces get merged into one plane for 1363 * each format plane, based on the required alignment only. 1364 * 1365 * Bits Parameter Notes 1366 * ----- ------------------------ --------------------------------------------- 1367 * 1368 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1369 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1370 * 13 DCC 1371 * 14 DCC_RETILE 1372 * 15 DCC_PIPE_ALIGN 1373 * 16 DCC_INDEPENDENT_64B 1374 * 17 DCC_INDEPENDENT_128B 1375 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1376 * 20 DCC_CONSTANT_ENCODE 1377 * 23:21 PIPE_XOR_BITS Only for some chips 1378 * 26:24 BANK_XOR_BITS Only for some chips 1379 * 29:27 PACKERS Only for some chips 1380 * 32:30 RB Only for some chips 1381 * 35:33 PIPE Only for some chips 1382 * 55:36 - Reserved for future use, must be zero 1383 */ 1384 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1385 1386 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1387 1388 /* Reserve 0 for GFX8 and older */ 1389 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1390 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1391 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1392 #define AMD_FMT_MOD_TILE_VER_GFX11 4 1393 1394 /* 1395 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1396 * version. 1397 */ 1398 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1399 1400 /* 1401 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1402 * GFX9 as canonical version. 1403 */ 1404 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1405 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1406 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1407 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1408 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 1409 1410 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1411 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1412 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1413 1414 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1415 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1416 #define AMD_FMT_MOD_TILE_SHIFT 8 1417 #define AMD_FMT_MOD_TILE_MASK 0x1F 1418 1419 /* Whether DCC compression is enabled. */ 1420 #define AMD_FMT_MOD_DCC_SHIFT 13 1421 #define AMD_FMT_MOD_DCC_MASK 0x1 1422 1423 /* 1424 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1425 * one which is not-aligned. 1426 */ 1427 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1428 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1429 1430 /* Only set if DCC_RETILE = false */ 1431 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1432 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1433 1434 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1435 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1436 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1437 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1438 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1439 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1440 1441 /* 1442 * DCC supports embedding some clear colors directly in the DCC surface. 1443 * However, on older GPUs the rendering HW ignores the embedded clear color 1444 * and prefers the driver provided color. This necessitates doing a fastclear 1445 * eliminate operation before a process transfers control. 1446 * 1447 * If this bit is set that means the fastclear eliminate is not needed for these 1448 * embeddable colors. 1449 */ 1450 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1451 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1452 1453 /* 1454 * The below fields are for accounting for per GPU differences. These are only 1455 * relevant for GFX9 and later and if the tile field is *_X/_T. 1456 * 1457 * PIPE_XOR_BITS = always needed 1458 * BANK_XOR_BITS = only for TILE_VER_GFX9 1459 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1460 * RB = only for TILE_VER_GFX9 & DCC 1461 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1462 */ 1463 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1464 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1465 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1466 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1467 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1468 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1469 #define AMD_FMT_MOD_RB_SHIFT 30 1470 #define AMD_FMT_MOD_RB_MASK 0x7 1471 #define AMD_FMT_MOD_PIPE_SHIFT 33 1472 #define AMD_FMT_MOD_PIPE_MASK 0x7 1473 1474 #define AMD_FMT_MOD_SET(field, value) \ 1475 ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT) 1476 #define AMD_FMT_MOD_GET(field, value) \ 1477 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1478 #define AMD_FMT_MOD_CLEAR(field) \ 1479 (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1480 1481 #if defined(__cplusplus) 1482 } 1483 #endif 1484 1485 #endif /* DRM_FOURCC_H */ 1486