1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - V4l capture device 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * 7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/pm_runtime.h> 13 #include <media/v4l2-common.h> 14 #include <media/v4l2-event.h> 15 #include <media/v4l2-fh.h> 16 #include <media/v4l2-ioctl.h> 17 #include <media/v4l2-mc.h> 18 #include <media/v4l2-subdev.h> 19 #include <media/videobuf2-dma-contig.h> 20 21 #include "rkisp1-common.h" 22 23 /* 24 * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath. 25 * 26 * differences between selfpath and mainpath 27 * available mp sink input: isp 28 * available sp sink input : isp, dma(TODO) 29 * available mp sink pad fmts: yuv422, raw 30 * available sp sink pad fmts: yuv422, yuv420...... 31 * available mp source fmts: yuv, raw, jpeg(TODO) 32 * available sp source fmts: yuv, rgb 33 */ 34 35 #define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath" 36 #define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath" 37 38 #define RKISP1_MIN_BUFFERS_NEEDED 3 39 40 enum rkisp1_plane { 41 RKISP1_PLANE_Y = 0, 42 RKISP1_PLANE_CB = 1, 43 RKISP1_PLANE_CR = 2 44 }; 45 46 /* 47 * @fourcc: pixel format 48 * @fmt_type: helper filed for pixel format 49 * @uv_swap: if cb cr swapped, for yuv 50 * @write_format: defines how YCbCr self picture data is written to memory 51 * @output_format: defines sp output format 52 * @mbus: the mbus code on the src resizer pad that matches the pixel format 53 */ 54 struct rkisp1_capture_fmt_cfg { 55 u32 fourcc; 56 u8 uv_swap; 57 u32 write_format; 58 u32 output_format; 59 u32 mbus; 60 }; 61 62 struct rkisp1_capture_ops { 63 void (*config)(struct rkisp1_capture *cap); 64 void (*stop)(struct rkisp1_capture *cap); 65 void (*enable)(struct rkisp1_capture *cap); 66 void (*disable)(struct rkisp1_capture *cap); 67 void (*set_data_path)(struct rkisp1_capture *cap); 68 bool (*is_stopped)(struct rkisp1_capture *cap); 69 }; 70 71 struct rkisp1_capture_config { 72 const struct rkisp1_capture_fmt_cfg *fmts; 73 int fmt_size; 74 struct { 75 u32 y_size_init; 76 u32 cb_size_init; 77 u32 cr_size_init; 78 u32 y_base_ad_init; 79 u32 cb_base_ad_init; 80 u32 cr_base_ad_init; 81 u32 y_offs_cnt_init; 82 u32 cb_offs_cnt_init; 83 u32 cr_offs_cnt_init; 84 } mi; 85 }; 86 87 /* 88 * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus' 89 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 90 */ 91 static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { 92 /* yuv422 */ 93 { 94 .fourcc = V4L2_PIX_FMT_YUYV, 95 .uv_swap = 0, 96 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, 97 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 98 }, { 99 .fourcc = V4L2_PIX_FMT_YUV422P, 100 .uv_swap = 0, 101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 102 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 103 }, { 104 .fourcc = V4L2_PIX_FMT_NV16, 105 .uv_swap = 0, 106 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 107 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 108 }, { 109 .fourcc = V4L2_PIX_FMT_NV61, 110 .uv_swap = 1, 111 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 112 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 113 }, { 114 .fourcc = V4L2_PIX_FMT_NV16M, 115 .uv_swap = 0, 116 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 117 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 118 }, { 119 .fourcc = V4L2_PIX_FMT_NV61M, 120 .uv_swap = 1, 121 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 122 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 123 }, { 124 .fourcc = V4L2_PIX_FMT_YVU422M, 125 .uv_swap = 1, 126 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 127 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 128 }, 129 /* yuv400 */ 130 { 131 .fourcc = V4L2_PIX_FMT_GREY, 132 .uv_swap = 0, 133 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 134 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 135 }, 136 /* yuv420 */ 137 { 138 .fourcc = V4L2_PIX_FMT_NV21, 139 .uv_swap = 1, 140 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 141 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 142 }, { 143 .fourcc = V4L2_PIX_FMT_NV12, 144 .uv_swap = 0, 145 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 146 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 147 }, { 148 .fourcc = V4L2_PIX_FMT_NV21M, 149 .uv_swap = 1, 150 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 151 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 152 }, { 153 .fourcc = V4L2_PIX_FMT_NV12M, 154 .uv_swap = 0, 155 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 156 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 157 }, { 158 .fourcc = V4L2_PIX_FMT_YUV420, 159 .uv_swap = 0, 160 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 161 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 162 }, { 163 .fourcc = V4L2_PIX_FMT_YVU420, 164 .uv_swap = 1, 165 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 166 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 167 }, 168 /* raw */ 169 { 170 .fourcc = V4L2_PIX_FMT_SRGGB8, 171 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 172 .mbus = MEDIA_BUS_FMT_SRGGB8_1X8, 173 }, { 174 .fourcc = V4L2_PIX_FMT_SGRBG8, 175 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 176 .mbus = MEDIA_BUS_FMT_SGRBG8_1X8, 177 }, { 178 .fourcc = V4L2_PIX_FMT_SGBRG8, 179 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 180 .mbus = MEDIA_BUS_FMT_SGBRG8_1X8, 181 }, { 182 .fourcc = V4L2_PIX_FMT_SBGGR8, 183 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 184 .mbus = MEDIA_BUS_FMT_SBGGR8_1X8, 185 }, { 186 .fourcc = V4L2_PIX_FMT_SRGGB10, 187 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 188 .mbus = MEDIA_BUS_FMT_SRGGB10_1X10, 189 }, { 190 .fourcc = V4L2_PIX_FMT_SGRBG10, 191 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 192 .mbus = MEDIA_BUS_FMT_SGRBG10_1X10, 193 }, { 194 .fourcc = V4L2_PIX_FMT_SGBRG10, 195 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 196 .mbus = MEDIA_BUS_FMT_SGBRG10_1X10, 197 }, { 198 .fourcc = V4L2_PIX_FMT_SBGGR10, 199 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 200 .mbus = MEDIA_BUS_FMT_SBGGR10_1X10, 201 }, { 202 .fourcc = V4L2_PIX_FMT_SRGGB12, 203 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 204 .mbus = MEDIA_BUS_FMT_SRGGB12_1X12, 205 }, { 206 .fourcc = V4L2_PIX_FMT_SGRBG12, 207 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 208 .mbus = MEDIA_BUS_FMT_SGRBG12_1X12, 209 }, { 210 .fourcc = V4L2_PIX_FMT_SGBRG12, 211 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 212 .mbus = MEDIA_BUS_FMT_SGBRG12_1X12, 213 }, { 214 .fourcc = V4L2_PIX_FMT_SBGGR12, 215 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 216 .mbus = MEDIA_BUS_FMT_SBGGR12_1X12, 217 }, 218 }; 219 220 /* 221 * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus' 222 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 223 */ 224 static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = { 225 /* yuv422 */ 226 { 227 .fourcc = V4L2_PIX_FMT_YUYV, 228 .uv_swap = 0, 229 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT, 230 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 231 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 232 }, { 233 .fourcc = V4L2_PIX_FMT_YUV422P, 234 .uv_swap = 0, 235 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 236 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 237 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 238 }, { 239 .fourcc = V4L2_PIX_FMT_NV16, 240 .uv_swap = 0, 241 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 242 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 243 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 244 }, { 245 .fourcc = V4L2_PIX_FMT_NV61, 246 .uv_swap = 1, 247 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 248 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 249 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 250 }, { 251 .fourcc = V4L2_PIX_FMT_NV16M, 252 .uv_swap = 0, 253 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 254 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 255 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 256 }, { 257 .fourcc = V4L2_PIX_FMT_NV61M, 258 .uv_swap = 1, 259 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 260 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 261 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 262 }, { 263 .fourcc = V4L2_PIX_FMT_YVU422M, 264 .uv_swap = 1, 265 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 266 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 267 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 268 }, 269 /* yuv400 */ 270 { 271 .fourcc = V4L2_PIX_FMT_GREY, 272 .uv_swap = 0, 273 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 274 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 275 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 276 }, 277 /* rgb */ 278 { 279 .fourcc = V4L2_PIX_FMT_XBGR32, 280 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 281 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888, 282 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 283 }, { 284 .fourcc = V4L2_PIX_FMT_RGB565, 285 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 286 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565, 287 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 288 }, 289 /* yuv420 */ 290 { 291 .fourcc = V4L2_PIX_FMT_NV21, 292 .uv_swap = 1, 293 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 294 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 295 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 296 }, { 297 .fourcc = V4L2_PIX_FMT_NV12, 298 .uv_swap = 0, 299 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 300 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 301 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 302 }, { 303 .fourcc = V4L2_PIX_FMT_NV21M, 304 .uv_swap = 1, 305 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 306 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 307 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 308 }, { 309 .fourcc = V4L2_PIX_FMT_NV12M, 310 .uv_swap = 0, 311 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 312 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 313 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 314 }, { 315 .fourcc = V4L2_PIX_FMT_YUV420, 316 .uv_swap = 0, 317 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 318 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 319 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 320 }, { 321 .fourcc = V4L2_PIX_FMT_YVU420, 322 .uv_swap = 1, 323 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 324 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 325 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 326 }, 327 }; 328 329 static const struct rkisp1_capture_config rkisp1_capture_config_mp = { 330 .fmts = rkisp1_mp_fmts, 331 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts), 332 .mi = { 333 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT, 334 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT, 335 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT, 336 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT, 337 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT, 338 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT, 339 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT, 340 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT, 341 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT, 342 }, 343 }; 344 345 static const struct rkisp1_capture_config rkisp1_capture_config_sp = { 346 .fmts = rkisp1_sp_fmts, 347 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts), 348 .mi = { 349 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT, 350 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT, 351 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT, 352 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT, 353 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT, 354 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT, 355 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT, 356 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT, 357 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT, 358 }, 359 }; 360 361 static inline struct rkisp1_vdev_node * 362 rkisp1_vdev_to_node(struct video_device *vdev) 363 { 364 return container_of(vdev, struct rkisp1_vdev_node, vdev); 365 } 366 367 int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap, 368 struct v4l2_subdev_mbus_code_enum *code) 369 { 370 const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts; 371 /* 372 * initialize curr_mbus to non existing mbus code 0 to ensure it is 373 * different from fmts[0].mbus 374 */ 375 u32 curr_mbus = 0; 376 int i, n = 0; 377 378 for (i = 0; i < cap->config->fmt_size; i++) { 379 if (fmts[i].mbus == curr_mbus) 380 continue; 381 382 curr_mbus = fmts[i].mbus; 383 if (n++ == code->index) { 384 code->code = curr_mbus; 385 return 0; 386 } 387 } 388 return -EINVAL; 389 } 390 391 /* ---------------------------------------------------------------------------- 392 * Stream operations for self-picture path (sp) and main-picture path (mp) 393 */ 394 395 static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap) 396 { 397 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 398 399 mi_ctrl &= ~GENMASK(17, 16); 400 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64; 401 402 mi_ctrl &= ~GENMASK(19, 18); 403 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64; 404 405 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN | 406 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN; 407 408 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 409 } 410 411 static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm, 412 unsigned int component) 413 { 414 /* 415 * If packed format, then plane_fmt[0].sizeimage is the sum of all 416 * components, so we need to calculate just the size of Y component. 417 * See rkisp1_fill_pixfmt(). 418 */ 419 if (!component && pixm->num_planes == 1) 420 return pixm->plane_fmt[0].bytesperline * pixm->height; 421 return pixm->plane_fmt[component].sizeimage; 422 } 423 424 static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap) 425 { 426 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC); 427 428 mi_imsc |= RKISP1_CIF_MI_FRAME(cap); 429 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_IMSC, mi_imsc); 430 } 431 432 static void rkisp1_mp_config(struct rkisp1_capture *cap) 433 { 434 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 435 struct rkisp1_device *rkisp1 = cap->rkisp1; 436 u32 reg; 437 438 rkisp1_write(rkisp1, cap->config->mi.y_size_init, 439 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y)); 440 rkisp1_write(rkisp1, cap->config->mi.cb_size_init, 441 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB)); 442 rkisp1_write(rkisp1, cap->config->mi.cr_size_init, 443 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 444 445 rkisp1_irq_frame_end_enable(cap); 446 447 /* set uv swapping for semiplanar formats */ 448 if (cap->pix.info->comp_planes == 2) { 449 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 450 if (cap->pix.cfg->uv_swap) 451 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 452 else 453 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 454 rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg); 455 } 456 457 rkisp1_mi_config_ctrl(cap); 458 459 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 460 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK; 461 reg |= cap->pix.cfg->write_format; 462 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, reg); 463 464 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 465 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE; 466 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, reg); 467 } 468 469 static void rkisp1_sp_config(struct rkisp1_capture *cap) 470 { 471 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 472 struct rkisp1_device *rkisp1 = cap->rkisp1; 473 u32 mi_ctrl, reg; 474 475 rkisp1_write(rkisp1, cap->config->mi.y_size_init, 476 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y)); 477 rkisp1_write(rkisp1, cap->config->mi.cb_size_init, 478 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB)); 479 rkisp1_write(rkisp1, cap->config->mi.cr_size_init, 480 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 481 482 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_WIDTH, pixm->width); 483 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT, pixm->height); 484 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_LLENGTH, cap->sp_y_stride); 485 486 rkisp1_irq_frame_end_enable(cap); 487 488 /* set uv swapping for semiplanar formats */ 489 if (cap->pix.info->comp_planes == 2) { 490 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 491 if (cap->pix.cfg->uv_swap) 492 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 493 else 494 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 495 rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg); 496 } 497 498 rkisp1_mi_config_ctrl(cap); 499 500 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 501 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK; 502 mi_ctrl |= cap->pix.cfg->write_format | 503 RKISP1_MI_CTRL_SP_INPUT_YUV422 | 504 cap->pix.cfg->output_format | 505 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE; 506 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 507 } 508 509 static void rkisp1_mp_disable(struct rkisp1_capture *cap) 510 { 511 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 512 513 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE | 514 RKISP1_CIF_MI_CTRL_RAW_ENABLE); 515 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 516 } 517 518 static void rkisp1_sp_disable(struct rkisp1_capture *cap) 519 { 520 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 521 522 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE; 523 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 524 } 525 526 static void rkisp1_mp_enable(struct rkisp1_capture *cap) 527 { 528 u32 mi_ctrl; 529 530 rkisp1_mp_disable(cap); 531 532 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 533 if (v4l2_is_format_bayer(cap->pix.info)) 534 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE; 535 /* YUV */ 536 else 537 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE; 538 539 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 540 } 541 542 static void rkisp1_sp_enable(struct rkisp1_capture *cap) 543 { 544 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 545 546 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE; 547 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 548 } 549 550 static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap) 551 { 552 if (!cap->is_streaming) 553 return; 554 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_ICR, RKISP1_CIF_MI_FRAME(cap)); 555 cap->ops->disable(cap); 556 } 557 558 static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap) 559 { 560 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED | 561 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED; 562 563 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en); 564 } 565 566 static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap) 567 { 568 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & 569 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED); 570 } 571 572 static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap) 573 { 574 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 575 576 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP | 577 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI; 578 rkisp1_write(cap->rkisp1, RKISP1_CIF_VI_DPCL, dpcl); 579 } 580 581 static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap) 582 { 583 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 584 585 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP; 586 rkisp1_write(cap->rkisp1, RKISP1_CIF_VI_DPCL, dpcl); 587 } 588 589 static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = { 590 .config = rkisp1_mp_config, 591 .enable = rkisp1_mp_enable, 592 .disable = rkisp1_mp_disable, 593 .stop = rkisp1_mp_sp_stop, 594 .set_data_path = rkisp1_mp_set_data_path, 595 .is_stopped = rkisp1_mp_is_stopped, 596 }; 597 598 static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = { 599 .config = rkisp1_sp_config, 600 .enable = rkisp1_sp_enable, 601 .disable = rkisp1_sp_disable, 602 .stop = rkisp1_mp_sp_stop, 603 .set_data_path = rkisp1_sp_set_data_path, 604 .is_stopped = rkisp1_sp_is_stopped, 605 }; 606 607 /* ---------------------------------------------------------------------------- 608 * Frame buffer operations 609 */ 610 611 static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap) 612 { 613 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 614 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy; 615 616 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 617 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 618 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 619 620 /* The driver never access vaddr, no mapping is required */ 621 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev, 622 dummy_buf->size, 623 &dummy_buf->dma_addr, 624 GFP_KERNEL, 625 DMA_ATTR_NO_KERNEL_MAPPING); 626 if (!dummy_buf->vaddr) 627 return -ENOMEM; 628 629 return 0; 630 } 631 632 static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap) 633 { 634 dma_free_attrs(cap->rkisp1->dev, 635 cap->buf.dummy.size, cap->buf.dummy.vaddr, 636 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING); 637 } 638 639 static void rkisp1_set_next_buf(struct rkisp1_capture *cap) 640 { 641 cap->buf.curr = cap->buf.next; 642 cap->buf.next = NULL; 643 644 if (!list_empty(&cap->buf.queue)) { 645 u32 *buff_addr; 646 647 cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue); 648 list_del(&cap->buf.next->queue); 649 650 buff_addr = cap->buf.next->buff_addr; 651 652 rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init, 653 buff_addr[RKISP1_PLANE_Y]); 654 /* 655 * In order to support grey format we capture 656 * YUV422 planar format from the camera and 657 * set the U and V planes to the dummy buffer 658 */ 659 if (cap->pix.cfg->fourcc == V4L2_PIX_FMT_GREY) { 660 rkisp1_write(cap->rkisp1, 661 cap->config->mi.cb_base_ad_init, 662 cap->buf.dummy.dma_addr); 663 rkisp1_write(cap->rkisp1, 664 cap->config->mi.cr_base_ad_init, 665 cap->buf.dummy.dma_addr); 666 } else { 667 rkisp1_write(cap->rkisp1, 668 cap->config->mi.cb_base_ad_init, 669 buff_addr[RKISP1_PLANE_CB]); 670 rkisp1_write(cap->rkisp1, 671 cap->config->mi.cr_base_ad_init, 672 buff_addr[RKISP1_PLANE_CR]); 673 } 674 } else { 675 /* 676 * Use the dummy space allocated by dma_alloc_coherent to 677 * throw data if there is no available buffer. 678 */ 679 rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init, 680 cap->buf.dummy.dma_addr); 681 rkisp1_write(cap->rkisp1, cap->config->mi.cb_base_ad_init, 682 cap->buf.dummy.dma_addr); 683 rkisp1_write(cap->rkisp1, cap->config->mi.cr_base_ad_init, 684 cap->buf.dummy.dma_addr); 685 } 686 687 /* Set plane offsets */ 688 rkisp1_write(cap->rkisp1, cap->config->mi.y_offs_cnt_init, 0); 689 rkisp1_write(cap->rkisp1, cap->config->mi.cb_offs_cnt_init, 0); 690 rkisp1_write(cap->rkisp1, cap->config->mi.cr_offs_cnt_init, 0); 691 } 692 693 /* 694 * This function is called when a frame end comes. The next frame 695 * is processing and we should set up buffer for next-next frame, 696 * otherwise it will overflow. 697 */ 698 static void rkisp1_handle_buffer(struct rkisp1_capture *cap) 699 { 700 struct rkisp1_isp *isp = &cap->rkisp1->isp; 701 struct rkisp1_buffer *curr_buf; 702 703 spin_lock(&cap->buf.lock); 704 curr_buf = cap->buf.curr; 705 706 if (curr_buf) { 707 curr_buf->vb.sequence = isp->frame_sequence; 708 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns(); 709 curr_buf->vb.field = V4L2_FIELD_NONE; 710 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 711 } else { 712 cap->rkisp1->debug.frame_drop[cap->id]++; 713 } 714 715 rkisp1_set_next_buf(cap); 716 spin_unlock(&cap->buf.lock); 717 } 718 719 irqreturn_t rkisp1_capture_isr(int irq, void *ctx) 720 { 721 struct device *dev = ctx; 722 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 723 unsigned int i; 724 u32 status; 725 726 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS); 727 if (!status) 728 return IRQ_NONE; 729 730 rkisp1_write(rkisp1, RKISP1_CIF_MI_ICR, status); 731 732 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) { 733 struct rkisp1_capture *cap = &rkisp1->capture_devs[i]; 734 735 if (!(status & RKISP1_CIF_MI_FRAME(cap))) 736 continue; 737 if (!cap->is_stopping) { 738 rkisp1_handle_buffer(cap); 739 continue; 740 } 741 /* 742 * Make sure stream is actually stopped, whose state 743 * can be read from the shadow register, before 744 * wake_up() thread which would immediately free all 745 * frame buffers. stop() takes effect at the next 746 * frame end that sync the configurations to shadow 747 * regs. 748 */ 749 if (!cap->ops->is_stopped(cap)) { 750 cap->ops->stop(cap); 751 continue; 752 } 753 cap->is_stopping = false; 754 cap->is_streaming = false; 755 wake_up(&cap->done); 756 } 757 758 return IRQ_HANDLED; 759 } 760 761 /* ---------------------------------------------------------------------------- 762 * Vb2 operations 763 */ 764 765 static int rkisp1_vb2_queue_setup(struct vb2_queue *queue, 766 unsigned int *num_buffers, 767 unsigned int *num_planes, 768 unsigned int sizes[], 769 struct device *alloc_devs[]) 770 { 771 struct rkisp1_capture *cap = queue->drv_priv; 772 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 773 unsigned int i; 774 775 if (*num_planes) { 776 if (*num_planes != pixm->num_planes) 777 return -EINVAL; 778 779 for (i = 0; i < pixm->num_planes; i++) 780 if (sizes[i] < pixm->plane_fmt[i].sizeimage) 781 return -EINVAL; 782 } else { 783 *num_planes = pixm->num_planes; 784 for (i = 0; i < pixm->num_planes; i++) 785 sizes[i] = pixm->plane_fmt[i].sizeimage; 786 } 787 788 return 0; 789 } 790 791 static int rkisp1_vb2_buf_init(struct vb2_buffer *vb) 792 { 793 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 794 struct rkisp1_buffer *ispbuf = 795 container_of(vbuf, struct rkisp1_buffer, vb); 796 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 797 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 798 unsigned int i; 799 800 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr)); 801 for (i = 0; i < pixm->num_planes; i++) 802 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); 803 804 /* Convert to non-MPLANE */ 805 if (pixm->num_planes == 1) { 806 ispbuf->buff_addr[RKISP1_PLANE_CB] = 807 ispbuf->buff_addr[RKISP1_PLANE_Y] + 808 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y); 809 ispbuf->buff_addr[RKISP1_PLANE_CR] = 810 ispbuf->buff_addr[RKISP1_PLANE_CB] + 811 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB); 812 } 813 814 /* 815 * uv swap can be supported for planar formats by switching 816 * the address of cb and cr 817 */ 818 if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap) 819 swap(ispbuf->buff_addr[RKISP1_PLANE_CR], 820 ispbuf->buff_addr[RKISP1_PLANE_CB]); 821 return 0; 822 } 823 824 static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb) 825 { 826 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 827 struct rkisp1_buffer *ispbuf = 828 container_of(vbuf, struct rkisp1_buffer, vb); 829 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 830 831 spin_lock_irq(&cap->buf.lock); 832 list_add_tail(&ispbuf->queue, &cap->buf.queue); 833 spin_unlock_irq(&cap->buf.lock); 834 } 835 836 static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb) 837 { 838 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 839 unsigned int i; 840 841 for (i = 0; i < cap->pix.fmt.num_planes; i++) { 842 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage; 843 844 if (vb2_plane_size(vb, i) < size) { 845 dev_err(cap->rkisp1->dev, 846 "User buffer too small (%ld < %ld)\n", 847 vb2_plane_size(vb, i), size); 848 return -EINVAL; 849 } 850 vb2_set_plane_payload(vb, i, size); 851 } 852 853 return 0; 854 } 855 856 static void rkisp1_return_all_buffers(struct rkisp1_capture *cap, 857 enum vb2_buffer_state state) 858 { 859 struct rkisp1_buffer *buf; 860 861 spin_lock_irq(&cap->buf.lock); 862 if (cap->buf.curr) { 863 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state); 864 cap->buf.curr = NULL; 865 } 866 if (cap->buf.next) { 867 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state); 868 cap->buf.next = NULL; 869 } 870 while (!list_empty(&cap->buf.queue)) { 871 buf = list_first_entry(&cap->buf.queue, 872 struct rkisp1_buffer, queue); 873 list_del(&buf->queue); 874 vb2_buffer_done(&buf->vb.vb2_buf, state); 875 } 876 spin_unlock_irq(&cap->buf.lock); 877 } 878 879 /* 880 * Most registers inside the rockchip ISP1 have shadow register since 881 * they must not be changed while processing a frame. 882 * Usually, each sub-module updates its shadow register after 883 * processing the last pixel of a frame. 884 */ 885 static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap) 886 { 887 struct rkisp1_device *rkisp1 = cap->rkisp1; 888 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1]; 889 890 cap->ops->set_data_path(cap); 891 cap->ops->config(cap); 892 893 /* Setup a buffer for the next frame */ 894 spin_lock_irq(&cap->buf.lock); 895 rkisp1_set_next_buf(cap); 896 cap->ops->enable(cap); 897 /* It's safe to configure ACTIVE and SHADOW registers for the 898 * first stream. While when the second is starting, do NOT 899 * force update because it also updates the first one. 900 * 901 * The latter case would drop one more buffer(that is 2) since 902 * there's no buffer in a shadow register when the second FE received. 903 * This's also required because the second FE maybe corrupt 904 * especially when run at 120fps. 905 */ 906 if (!other->is_streaming) { 907 /* force cfg update */ 908 rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, 909 RKISP1_CIF_MI_INIT_SOFT_UPD); 910 rkisp1_set_next_buf(cap); 911 } 912 spin_unlock_irq(&cap->buf.lock); 913 cap->is_streaming = true; 914 } 915 916 static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap) 917 { 918 int ret; 919 920 /* Stream should stop in interrupt. If it doesn't, stop it by force. */ 921 cap->is_stopping = true; 922 ret = wait_event_timeout(cap->done, 923 !cap->is_streaming, 924 msecs_to_jiffies(1000)); 925 if (!ret) { 926 cap->rkisp1->debug.stop_timeout[cap->id]++; 927 cap->ops->stop(cap); 928 cap->is_stopping = false; 929 cap->is_streaming = false; 930 } 931 } 932 933 /* 934 * rkisp1_pipeline_stream_disable - disable nodes in the pipeline 935 * 936 * Call s_stream(false) in the reverse order from 937 * rkisp1_pipeline_stream_enable() and disable the DMA engine. 938 * Should be called before video_device_pipeline_stop() 939 */ 940 static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap) 941 __must_hold(&cap->rkisp1->stream_lock) 942 { 943 struct rkisp1_device *rkisp1 = cap->rkisp1; 944 945 rkisp1_cap_stream_disable(cap); 946 947 /* 948 * If the other capture is streaming, isp and sensor nodes shouldn't 949 * be disabled, skip them. 950 */ 951 if (rkisp1->pipe.start_count < 2) 952 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 953 954 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 955 false); 956 } 957 958 /* 959 * rkisp1_pipeline_stream_enable - enable nodes in the pipeline 960 * 961 * Enable the DMA Engine and call s_stream(true) through the pipeline. 962 * Should be called after video_device_pipeline_start() 963 */ 964 static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap) 965 __must_hold(&cap->rkisp1->stream_lock) 966 { 967 struct rkisp1_device *rkisp1 = cap->rkisp1; 968 int ret; 969 970 rkisp1_cap_stream_enable(cap); 971 972 ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, 973 s_stream, true); 974 if (ret) 975 goto err_disable_cap; 976 977 /* 978 * If the other capture is streaming, isp and sensor nodes are already 979 * enabled, skip them. 980 */ 981 if (rkisp1->pipe.start_count > 1) 982 return 0; 983 984 ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true); 985 if (ret) 986 goto err_disable_rsz; 987 988 return 0; 989 990 err_disable_rsz: 991 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 992 false); 993 err_disable_cap: 994 rkisp1_cap_stream_disable(cap); 995 996 return ret; 997 } 998 999 static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue) 1000 { 1001 struct rkisp1_capture *cap = queue->drv_priv; 1002 struct rkisp1_vdev_node *node = &cap->vnode; 1003 struct rkisp1_device *rkisp1 = cap->rkisp1; 1004 int ret; 1005 1006 mutex_lock(&cap->rkisp1->stream_lock); 1007 1008 rkisp1_pipeline_stream_disable(cap); 1009 1010 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR); 1011 1012 v4l2_pipeline_pm_put(&node->vdev.entity); 1013 ret = pm_runtime_put(rkisp1->dev); 1014 if (ret < 0) 1015 dev_err(rkisp1->dev, "power down failed error:%d\n", ret); 1016 1017 rkisp1_dummy_buf_destroy(cap); 1018 1019 video_device_pipeline_stop(&node->vdev); 1020 1021 mutex_unlock(&cap->rkisp1->stream_lock); 1022 } 1023 1024 static int 1025 rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count) 1026 { 1027 struct rkisp1_capture *cap = queue->drv_priv; 1028 struct media_entity *entity = &cap->vnode.vdev.entity; 1029 int ret; 1030 1031 mutex_lock(&cap->rkisp1->stream_lock); 1032 1033 ret = video_device_pipeline_start(&cap->vnode.vdev, &cap->rkisp1->pipe); 1034 if (ret) { 1035 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret); 1036 goto err_ret_buffers; 1037 } 1038 1039 ret = rkisp1_dummy_buf_create(cap); 1040 if (ret) 1041 goto err_pipeline_stop; 1042 1043 ret = pm_runtime_resume_and_get(cap->rkisp1->dev); 1044 if (ret < 0) { 1045 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret); 1046 goto err_destroy_dummy; 1047 } 1048 ret = v4l2_pipeline_pm_get(entity); 1049 if (ret) { 1050 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret); 1051 goto err_pipe_pm_put; 1052 } 1053 1054 ret = rkisp1_pipeline_stream_enable(cap); 1055 if (ret) 1056 goto err_v4l2_pm_put; 1057 1058 mutex_unlock(&cap->rkisp1->stream_lock); 1059 1060 return 0; 1061 1062 err_v4l2_pm_put: 1063 v4l2_pipeline_pm_put(entity); 1064 err_pipe_pm_put: 1065 pm_runtime_put(cap->rkisp1->dev); 1066 err_destroy_dummy: 1067 rkisp1_dummy_buf_destroy(cap); 1068 err_pipeline_stop: 1069 video_device_pipeline_stop(&cap->vnode.vdev); 1070 err_ret_buffers: 1071 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED); 1072 mutex_unlock(&cap->rkisp1->stream_lock); 1073 1074 return ret; 1075 } 1076 1077 static const struct vb2_ops rkisp1_vb2_ops = { 1078 .queue_setup = rkisp1_vb2_queue_setup, 1079 .buf_init = rkisp1_vb2_buf_init, 1080 .buf_queue = rkisp1_vb2_buf_queue, 1081 .buf_prepare = rkisp1_vb2_buf_prepare, 1082 .wait_prepare = vb2_ops_wait_prepare, 1083 .wait_finish = vb2_ops_wait_finish, 1084 .stop_streaming = rkisp1_vb2_stop_streaming, 1085 .start_streaming = rkisp1_vb2_start_streaming, 1086 }; 1087 1088 /* ---------------------------------------------------------------------------- 1089 * IOCTLs operations 1090 */ 1091 1092 static const struct v4l2_format_info * 1093 rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm, 1094 enum rkisp1_stream_id id) 1095 { 1096 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0]; 1097 const struct v4l2_format_info *info; 1098 unsigned int i; 1099 u32 stride; 1100 1101 memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt)); 1102 info = v4l2_format_info(pixm->pixelformat); 1103 pixm->num_planes = info->mem_planes; 1104 stride = info->bpp[0] * pixm->width; 1105 /* Self path supports custom stride but Main path doesn't */ 1106 if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride) 1107 plane_y->bytesperline = stride; 1108 plane_y->sizeimage = plane_y->bytesperline * pixm->height; 1109 1110 /* normalize stride to pixels per line */ 1111 stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]); 1112 1113 for (i = 1; i < info->comp_planes; i++) { 1114 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i]; 1115 1116 /* bytesperline for other components derive from Y component */ 1117 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) * 1118 info->bpp[i]; 1119 plane->sizeimage = plane->bytesperline * 1120 DIV_ROUND_UP(pixm->height, info->vdiv); 1121 } 1122 1123 /* 1124 * If pixfmt is packed, then plane_fmt[0] should contain the total size 1125 * considering all components. plane_fmt[i] for i > 0 should be ignored 1126 * by userspace as mem_planes == 1, but we are keeping information there 1127 * for convenience. 1128 */ 1129 if (info->mem_planes == 1) 1130 for (i = 1; i < info->comp_planes; i++) 1131 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage; 1132 1133 return info; 1134 } 1135 1136 static const struct rkisp1_capture_fmt_cfg * 1137 rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt) 1138 { 1139 unsigned int i; 1140 1141 for (i = 0; i < cap->config->fmt_size; i++) { 1142 if (cap->config->fmts[i].fourcc == pixelfmt) 1143 return &cap->config->fmts[i]; 1144 } 1145 return NULL; 1146 } 1147 1148 static void rkisp1_try_fmt(const struct rkisp1_capture *cap, 1149 struct v4l2_pix_format_mplane *pixm, 1150 const struct rkisp1_capture_fmt_cfg **fmt_cfg, 1151 const struct v4l2_format_info **fmt_info) 1152 { 1153 const struct rkisp1_capture_config *config = cap->config; 1154 const struct rkisp1_capture_fmt_cfg *fmt; 1155 const struct v4l2_format_info *info; 1156 static const unsigned int max_widths[] = { 1157 RKISP1_RSZ_MP_SRC_MAX_WIDTH, RKISP1_RSZ_SP_SRC_MAX_WIDTH 1158 }; 1159 static const unsigned int max_heights[] = { 1160 RKISP1_RSZ_MP_SRC_MAX_HEIGHT, RKISP1_RSZ_SP_SRC_MAX_HEIGHT 1161 }; 1162 1163 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat); 1164 if (!fmt) { 1165 fmt = config->fmts; 1166 pixm->pixelformat = fmt->fourcc; 1167 } 1168 1169 pixm->width = clamp_t(u32, pixm->width, 1170 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]); 1171 pixm->height = clamp_t(u32, pixm->height, 1172 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]); 1173 1174 pixm->field = V4L2_FIELD_NONE; 1175 pixm->colorspace = V4L2_COLORSPACE_DEFAULT; 1176 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1177 pixm->quantization = V4L2_QUANTIZATION_DEFAULT; 1178 1179 info = rkisp1_fill_pixfmt(pixm, cap->id); 1180 1181 if (fmt_cfg) 1182 *fmt_cfg = fmt; 1183 if (fmt_info) 1184 *fmt_info = info; 1185 } 1186 1187 static void rkisp1_set_fmt(struct rkisp1_capture *cap, 1188 struct v4l2_pix_format_mplane *pixm) 1189 { 1190 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info); 1191 cap->pix.fmt = *pixm; 1192 1193 /* SP supports custom stride in number of pixels of the Y plane */ 1194 if (cap->id == RKISP1_SELFPATH) 1195 cap->sp_y_stride = pixm->plane_fmt[0].bytesperline / 1196 cap->pix.info->bpp[0]; 1197 } 1198 1199 static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh, 1200 struct v4l2_format *f) 1201 { 1202 struct rkisp1_capture *cap = video_drvdata(file); 1203 1204 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL); 1205 1206 return 0; 1207 } 1208 1209 static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv, 1210 struct v4l2_fmtdesc *f) 1211 { 1212 struct rkisp1_capture *cap = video_drvdata(file); 1213 const struct rkisp1_capture_fmt_cfg *fmt = NULL; 1214 unsigned int i, n = 0; 1215 1216 if (!f->mbus_code) { 1217 if (f->index >= cap->config->fmt_size) 1218 return -EINVAL; 1219 1220 fmt = &cap->config->fmts[f->index]; 1221 f->pixelformat = fmt->fourcc; 1222 return 0; 1223 } 1224 1225 for (i = 0; i < cap->config->fmt_size; i++) { 1226 if (cap->config->fmts[i].mbus != f->mbus_code) 1227 continue; 1228 1229 if (n++ == f->index) { 1230 f->pixelformat = cap->config->fmts[i].fourcc; 1231 return 0; 1232 } 1233 } 1234 return -EINVAL; 1235 } 1236 1237 static int rkisp1_enum_framesizes(struct file *file, void *fh, 1238 struct v4l2_frmsizeenum *fsize) 1239 { 1240 static const unsigned int max_widths[] = { 1241 RKISP1_RSZ_MP_SRC_MAX_WIDTH, 1242 RKISP1_RSZ_SP_SRC_MAX_WIDTH, 1243 }; 1244 static const unsigned int max_heights[] = { 1245 RKISP1_RSZ_MP_SRC_MAX_HEIGHT, 1246 RKISP1_RSZ_SP_SRC_MAX_HEIGHT, 1247 }; 1248 struct rkisp1_capture *cap = video_drvdata(file); 1249 1250 if (fsize->index != 0) 1251 return -EINVAL; 1252 1253 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 1254 1255 fsize->stepwise.min_width = RKISP1_RSZ_SRC_MIN_WIDTH; 1256 fsize->stepwise.max_width = max_widths[cap->id]; 1257 fsize->stepwise.step_width = 2; 1258 1259 fsize->stepwise.min_height = RKISP1_RSZ_SRC_MIN_HEIGHT; 1260 fsize->stepwise.max_height = max_heights[cap->id]; 1261 fsize->stepwise.step_height = 2; 1262 1263 return 0; 1264 } 1265 1266 static int rkisp1_s_fmt_vid_cap_mplane(struct file *file, 1267 void *priv, struct v4l2_format *f) 1268 { 1269 struct rkisp1_capture *cap = video_drvdata(file); 1270 struct rkisp1_vdev_node *node = 1271 rkisp1_vdev_to_node(&cap->vnode.vdev); 1272 1273 if (vb2_is_busy(&node->buf_queue)) 1274 return -EBUSY; 1275 1276 rkisp1_set_fmt(cap, &f->fmt.pix_mp); 1277 1278 return 0; 1279 } 1280 1281 static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh, 1282 struct v4l2_format *f) 1283 { 1284 struct rkisp1_capture *cap = video_drvdata(file); 1285 1286 f->fmt.pix_mp = cap->pix.fmt; 1287 1288 return 0; 1289 } 1290 1291 static int 1292 rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap) 1293 { 1294 strscpy(cap->driver, RKISP1_DRIVER_NAME, sizeof(cap->driver)); 1295 strscpy(cap->card, RKISP1_DRIVER_NAME, sizeof(cap->card)); 1296 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info)); 1297 1298 return 0; 1299 } 1300 1301 static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = { 1302 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1303 .vidioc_querybuf = vb2_ioctl_querybuf, 1304 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1305 .vidioc_qbuf = vb2_ioctl_qbuf, 1306 .vidioc_expbuf = vb2_ioctl_expbuf, 1307 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1308 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1309 .vidioc_streamon = vb2_ioctl_streamon, 1310 .vidioc_streamoff = vb2_ioctl_streamoff, 1311 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane, 1312 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane, 1313 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane, 1314 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane, 1315 .vidioc_enum_framesizes = rkisp1_enum_framesizes, 1316 .vidioc_querycap = rkisp1_querycap, 1317 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1318 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1319 }; 1320 1321 static int rkisp1_capture_link_validate(struct media_link *link) 1322 { 1323 struct video_device *vdev = 1324 media_entity_to_video_device(link->sink->entity); 1325 struct v4l2_subdev *sd = 1326 media_entity_to_v4l2_subdev(link->source->entity); 1327 struct rkisp1_capture *cap = video_get_drvdata(vdev); 1328 const struct rkisp1_capture_fmt_cfg *fmt = 1329 rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat); 1330 struct v4l2_subdev_format sd_fmt = { 1331 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1332 .pad = link->source->index, 1333 }; 1334 int ret; 1335 1336 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt); 1337 if (ret) 1338 return ret; 1339 1340 if (sd_fmt.format.height != cap->pix.fmt.height || 1341 sd_fmt.format.width != cap->pix.fmt.width || 1342 sd_fmt.format.code != fmt->mbus) { 1343 dev_dbg(cap->rkisp1->dev, 1344 "link '%s':%u -> '%s':%u not valid: 0x%04x/%ux%u != 0x%04x/%ux%u\n", 1345 link->source->entity->name, link->source->index, 1346 link->sink->entity->name, link->sink->index, 1347 sd_fmt.format.code, sd_fmt.format.width, 1348 sd_fmt.format.height, fmt->mbus, cap->pix.fmt.width, 1349 cap->pix.fmt.height); 1350 return -EPIPE; 1351 } 1352 1353 return 0; 1354 } 1355 1356 /* ---------------------------------------------------------------------------- 1357 * core functions 1358 */ 1359 1360 static const struct media_entity_operations rkisp1_media_ops = { 1361 .link_validate = rkisp1_capture_link_validate, 1362 }; 1363 1364 static const struct v4l2_file_operations rkisp1_fops = { 1365 .open = v4l2_fh_open, 1366 .release = vb2_fop_release, 1367 .unlocked_ioctl = video_ioctl2, 1368 .poll = vb2_fop_poll, 1369 .mmap = vb2_fop_mmap, 1370 }; 1371 1372 static void rkisp1_unregister_capture(struct rkisp1_capture *cap) 1373 { 1374 if (!video_is_registered(&cap->vnode.vdev)) 1375 return; 1376 1377 media_entity_cleanup(&cap->vnode.vdev.entity); 1378 vb2_video_unregister_device(&cap->vnode.vdev); 1379 mutex_destroy(&cap->vnode.vlock); 1380 } 1381 1382 void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1) 1383 { 1384 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH]; 1385 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH]; 1386 1387 rkisp1_unregister_capture(mp); 1388 rkisp1_unregister_capture(sp); 1389 } 1390 1391 static int rkisp1_register_capture(struct rkisp1_capture *cap) 1392 { 1393 static const char * const dev_names[] = { 1394 RKISP1_MP_DEV_NAME, RKISP1_SP_DEV_NAME 1395 }; 1396 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev; 1397 struct video_device *vdev = &cap->vnode.vdev; 1398 struct rkisp1_vdev_node *node; 1399 struct vb2_queue *q; 1400 int ret; 1401 1402 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name)); 1403 node = rkisp1_vdev_to_node(vdev); 1404 mutex_init(&node->vlock); 1405 1406 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops; 1407 vdev->release = video_device_release_empty; 1408 vdev->fops = &rkisp1_fops; 1409 vdev->minor = -1; 1410 vdev->v4l2_dev = v4l2_dev; 1411 vdev->lock = &node->vlock; 1412 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | 1413 V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; 1414 vdev->entity.ops = &rkisp1_media_ops; 1415 video_set_drvdata(vdev, cap); 1416 vdev->vfl_dir = VFL_DIR_RX; 1417 node->pad.flags = MEDIA_PAD_FL_SINK; 1418 1419 q = &node->buf_queue; 1420 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1421 q->io_modes = VB2_MMAP | VB2_DMABUF; 1422 q->drv_priv = cap; 1423 q->ops = &rkisp1_vb2_ops; 1424 q->mem_ops = &vb2_dma_contig_memops; 1425 q->buf_struct_size = sizeof(struct rkisp1_buffer); 1426 q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED; 1427 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1428 q->lock = &node->vlock; 1429 q->dev = cap->rkisp1->dev; 1430 ret = vb2_queue_init(q); 1431 if (ret) { 1432 dev_err(cap->rkisp1->dev, 1433 "vb2 queue init failed (err=%d)\n", ret); 1434 goto error; 1435 } 1436 1437 vdev->queue = q; 1438 1439 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad); 1440 if (ret) 1441 goto error; 1442 1443 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1444 if (ret) { 1445 dev_err(cap->rkisp1->dev, 1446 "failed to register %s, ret=%d\n", vdev->name, ret); 1447 goto error; 1448 } 1449 1450 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name, 1451 vdev->num); 1452 1453 return 0; 1454 1455 error: 1456 media_entity_cleanup(&vdev->entity); 1457 mutex_destroy(&node->vlock); 1458 return ret; 1459 } 1460 1461 static void 1462 rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id) 1463 { 1464 struct rkisp1_capture *cap = &rkisp1->capture_devs[id]; 1465 struct v4l2_pix_format_mplane pixm; 1466 1467 memset(cap, 0, sizeof(*cap)); 1468 cap->id = id; 1469 cap->rkisp1 = rkisp1; 1470 1471 INIT_LIST_HEAD(&cap->buf.queue); 1472 init_waitqueue_head(&cap->done); 1473 spin_lock_init(&cap->buf.lock); 1474 if (cap->id == RKISP1_SELFPATH) { 1475 cap->ops = &rkisp1_capture_ops_sp; 1476 cap->config = &rkisp1_capture_config_sp; 1477 } else { 1478 cap->ops = &rkisp1_capture_ops_mp; 1479 cap->config = &rkisp1_capture_config_mp; 1480 } 1481 1482 cap->is_streaming = false; 1483 1484 memset(&pixm, 0, sizeof(pixm)); 1485 pixm.pixelformat = V4L2_PIX_FMT_YUYV; 1486 pixm.width = RKISP1_DEFAULT_WIDTH; 1487 pixm.height = RKISP1_DEFAULT_HEIGHT; 1488 rkisp1_set_fmt(cap, &pixm); 1489 } 1490 1491 int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1) 1492 { 1493 unsigned int i; 1494 int ret; 1495 1496 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) { 1497 struct rkisp1_capture *cap = &rkisp1->capture_devs[i]; 1498 1499 rkisp1_capture_init(rkisp1, i); 1500 1501 ret = rkisp1_register_capture(cap); 1502 if (ret) { 1503 rkisp1_capture_devs_unregister(rkisp1); 1504 return ret; 1505 } 1506 } 1507 1508 return 0; 1509 1510 } 1511