1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * arch/arm/mach-at91/pm_slow_clock.S 4 * 5 * Copyright (C) 2006 Savin Zlobec 6 * 7 * AT91SAM9 support: 8 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee> 9 */ 10#include <linux/linkage.h> 11#include <linux/clk/at91_pmc.h> 12#include "pm.h" 13#include "pm_data-offsets.h" 14 15#define SRAMC_SELF_FRESH_ACTIVE 0x01 16#define SRAMC_SELF_FRESH_EXIT 0x00 17 18pmc .req r0 19tmp1 .req r4 20tmp2 .req r5 21tmp3 .req r6 22 23/* 24 * Wait until master clock is ready (after switching master clock source) 25 * 26 * @r_mckid: register holding master clock identifier 27 * 28 * Side effects: overwrites r7, r8 29 */ 30 .macro wait_mckrdy r_mckid 31#ifdef CONFIG_SOC_SAMA7 32 cmp \r_mckid, #0 33 beq 1f 34 mov r7, #AT91_PMC_MCKXRDY 35 b 2f 36#endif 371: mov r7, #AT91_PMC_MCKRDY 382: ldr r8, [pmc, #AT91_PMC_SR] 39 and r8, r7 40 cmp r8, r7 41 bne 2b 42 .endm 43 44/* 45 * Wait until master oscillator has stabilized. 46 * 47 * Side effects: overwrites r7 48 */ 49 .macro wait_moscrdy 501: ldr r7, [pmc, #AT91_PMC_SR] 51 tst r7, #AT91_PMC_MOSCS 52 beq 1b 53 .endm 54 55/* 56 * Wait for main oscillator selection is done 57 * 58 * Side effects: overwrites r7 59 */ 60 .macro wait_moscsels 611: ldr r7, [pmc, #AT91_PMC_SR] 62 tst r7, #AT91_PMC_MOSCSELS 63 beq 1b 64 .endm 65 66/* 67 * Put the processor to enter the idle state 68 * 69 * Side effects: overwrites r7 70 */ 71 .macro at91_cpu_idle 72 73#if defined(CONFIG_CPU_V7) 74 mov r7, #AT91_PMC_PCK 75 str r7, [pmc, #AT91_PMC_SCDR] 76 77 dsb 78 79 wfi @ Wait For Interrupt 80#else 81 mcr p15, 0, tmp1, c7, c0, 4 82#endif 83 84 .endm 85 86/** 87 * Set state for 2.5V low power regulator 88 * @ena: 0 - disable regulator 89 * 1 - enable regulator 90 * 91 * Side effects: overwrites r7, r8, r9, r10 92 */ 93 .macro at91_2_5V_reg_set_low_power ena 94#ifdef CONFIG_SOC_SAMA7 95 ldr r7, .sfrbu 96 mov r8, #\ena 97 ldr r9, [r7, #AT91_SFRBU_25LDOCR] 98 orr r9, r9, #AT91_SFRBU_25LDOCR_LP 99 cmp r8, #1 100 beq lp_done_\ena 101 bic r9, r9, #AT91_SFRBU_25LDOCR_LP 102lp_done_\ena: 103 ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY 104 orr r9, r9, r10 105 str r9, [r7, #AT91_SFRBU_25LDOCR] 106#endif 107 .endm 108 109 .macro at91_backup_set_lpm reg 110#ifdef CONFIG_SOC_SAMA7 111 orr \reg, \reg, #0x200000 112#endif 113 .endm 114 115 .text 116 117 .arm 118 119#ifdef CONFIG_SOC_SAMA7 120/** 121 * Enable self-refresh 122 * 123 * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7 124 */ 125.macro at91_sramc_self_refresh_ena 126 ldr r2, .sramc_base 127 ldr r3, .sramc_phy_base 128 ldr r7, .pm_mode 129 130 dsb 131 132 /* Disable all AXI ports. */ 133 ldr tmp1, [r2, #UDDRC_PCTRL_0] 134 bic tmp1, tmp1, #0x1 135 str tmp1, [r2, #UDDRC_PCTRL_0] 136 137 ldr tmp1, [r2, #UDDRC_PCTRL_1] 138 bic tmp1, tmp1, #0x1 139 str tmp1, [r2, #UDDRC_PCTRL_1] 140 141 ldr tmp1, [r2, #UDDRC_PCTRL_2] 142 bic tmp1, tmp1, #0x1 143 str tmp1, [r2, #UDDRC_PCTRL_2] 144 145 ldr tmp1, [r2, #UDDRC_PCTRL_3] 146 bic tmp1, tmp1, #0x1 147 str tmp1, [r2, #UDDRC_PCTRL_3] 148 149 ldr tmp1, [r2, #UDDRC_PCTRL_4] 150 bic tmp1, tmp1, #0x1 151 str tmp1, [r2, #UDDRC_PCTRL_4] 152 153sr_ena_1: 154 /* Wait for all ports to disable. */ 155 ldr tmp1, [r2, #UDDRC_PSTAT] 156 ldr tmp2, =UDDRC_PSTAT_ALL_PORTS 157 tst tmp1, tmp2 158 bne sr_ena_1 159 160 /* Switch to self-refresh. */ 161 ldr tmp1, [r2, #UDDRC_PWRCTL] 162 orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW 163 str tmp1, [r2, #UDDRC_PWRCTL] 164 165sr_ena_2: 166 /* Wait for self-refresh enter. */ 167 ldr tmp1, [r2, #UDDRC_STAT] 168 bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK 169 cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW 170 bne sr_ena_2 171 172 /* Put DDR PHY's DLL in bypass mode for non-backup modes. */ 173 cmp r7, #AT91_PM_BACKUP 174 beq sr_ena_3 175 176 /* Disable DX DLLs. */ 177 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR] 178 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS 179 str tmp1, [r3, #DDR3PHY_DX0DLLCR] 180 181 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR] 182 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS 183 str tmp1, [r3, #DDR3PHY_DX1DLLCR] 184 185sr_ena_3: 186 /* Power down DDR PHY data receivers. */ 187 ldr tmp1, [r3, #DDR3PHY_DXCCR] 188 orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR 189 str tmp1, [r3, #DDR3PHY_DXCCR] 190 191 /* Power down ADDR/CMD IO. */ 192 ldr tmp1, [r3, #DDR3PHY_ACIOCR] 193 orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD 194 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 195 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 196 str tmp1, [r3, #DDR3PHY_ACIOCR] 197 198 /* Power down ODT. */ 199 ldr tmp1, [r3, #DDR3PHY_DSGCR] 200 orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 201 str tmp1, [r3, #DDR3PHY_DSGCR] 202.endm 203 204/** 205 * Disable self-refresh 206 * 207 * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3 208 */ 209.macro at91_sramc_self_refresh_dis 210 ldr r2, .sramc_base 211 ldr r3, .sramc_phy_base 212 213 /* Power up DDR PHY data receivers. */ 214 ldr tmp1, [r3, #DDR3PHY_DXCCR] 215 bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR 216 str tmp1, [r3, #DDR3PHY_DXCCR] 217 218 /* Power up the output of CK and CS pins. */ 219 ldr tmp1, [r3, #DDR3PHY_ACIOCR] 220 bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD 221 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 222 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 223 str tmp1, [r3, #DDR3PHY_ACIOCR] 224 225 /* Power up ODT. */ 226 ldr tmp1, [r3, #DDR3PHY_DSGCR] 227 bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 228 str tmp1, [r3, #DDR3PHY_DSGCR] 229 230 /* Enable DX DLLs. */ 231 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR] 232 bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS 233 str tmp1, [r3, #DDR3PHY_DX0DLLCR] 234 235 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR] 236 bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS 237 str tmp1, [r3, #DDR3PHY_DX1DLLCR] 238 239 /* Enable quasi-dynamic programming. */ 240 mov tmp1, #0 241 str tmp1, [r2, #UDDRC_SWCTRL] 242 243 /* De-assert SDRAM initialization. */ 244 ldr tmp1, [r2, #UDDRC_DFIMISC] 245 bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN 246 str tmp1, [r2, #UDDRC_DFIMISC] 247 248 /* Quasi-dynamic programming done. */ 249 mov tmp1, #UDDRC_SWCTRL_SW_DONE 250 str tmp1, [r2, #UDDRC_SWCTRL] 251 252sr_dis_1: 253 ldr tmp1, [r2, #UDDRC_SWSTAT] 254 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK 255 beq sr_dis_1 256 257 /* DLL soft-reset + DLL lock wait + ITM reset */ 258 mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \ 259 DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST) 260 str tmp1, [r3, #DDR3PHY_PIR] 261 262sr_dis_4: 263 /* Wait for it. */ 264 ldr tmp1, [r3, #DDR3PHY_PGSR] 265 tst tmp1, #DDR3PHY_PGSR_IDONE 266 beq sr_dis_4 267 268 /* Enable quasi-dynamic programming. */ 269 mov tmp1, #0 270 str tmp1, [r2, #UDDRC_SWCTRL] 271 272 /* Assert PHY init complete enable signal. */ 273 ldr tmp1, [r2, #UDDRC_DFIMISC] 274 orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN 275 str tmp1, [r2, #UDDRC_DFIMISC] 276 277 /* Programming is done. Set sw_done. */ 278 mov tmp1, #UDDRC_SWCTRL_SW_DONE 279 str tmp1, [r2, #UDDRC_SWCTRL] 280 281sr_dis_5: 282 /* Wait for it. */ 283 ldr tmp1, [r2, #UDDRC_SWSTAT] 284 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK 285 beq sr_dis_5 286 287 /* Trigger self-refresh exit. */ 288 ldr tmp1, [r2, #UDDRC_PWRCTL] 289 bic tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW 290 str tmp1, [r2, #UDDRC_PWRCTL] 291 292sr_dis_6: 293 /* Wait for self-refresh exit done. */ 294 ldr tmp1, [r2, #UDDRC_STAT] 295 bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK 296 cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL 297 bne sr_dis_6 298 299 /* Enable all AXI ports. */ 300 ldr tmp1, [r2, #UDDRC_PCTRL_0] 301 orr tmp1, tmp1, #0x1 302 str tmp1, [r2, #UDDRC_PCTRL_0] 303 304 ldr tmp1, [r2, #UDDRC_PCTRL_1] 305 orr tmp1, tmp1, #0x1 306 str tmp1, [r2, #UDDRC_PCTRL_1] 307 308 ldr tmp1, [r2, #UDDRC_PCTRL_2] 309 orr tmp1, tmp1, #0x1 310 str tmp1, [r2, #UDDRC_PCTRL_2] 311 312 ldr tmp1, [r2, #UDDRC_PCTRL_3] 313 orr tmp1, tmp1, #0x1 314 str tmp1, [r2, #UDDRC_PCTRL_3] 315 316 ldr tmp1, [r2, #UDDRC_PCTRL_4] 317 orr tmp1, tmp1, #0x1 318 str tmp1, [r2, #UDDRC_PCTRL_4] 319 320 dsb 321.endm 322#else 323/** 324 * Enable self-refresh 325 * 326 * register usage: 327 * @r1: memory type 328 * @r2: base address of the sram controller 329 * @r3: temporary 330 */ 331.macro at91_sramc_self_refresh_ena 332 ldr r1, .memtype 333 ldr r2, .sramc_base 334 335 cmp r1, #AT91_MEMCTRL_MC 336 bne sr_ena_ddrc_sf 337 338 /* Active SDRAM self-refresh mode */ 339 mov r3, #1 340 str r3, [r2, #AT91_MC_SDRAMC_SRR] 341 b sr_ena_exit 342 343sr_ena_ddrc_sf: 344 cmp r1, #AT91_MEMCTRL_DDRSDR 345 bne sr_ena_sdramc_sf 346 347 /* 348 * DDR Memory controller 349 */ 350 351 /* LPDDR1 --> force DDR2 mode during self-refresh */ 352 ldr r3, [r2, #AT91_DDRSDRC_MDR] 353 str r3, .saved_sam9_mdr 354 bic r3, r3, #~AT91_DDRSDRC_MD 355 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR 356 ldreq r3, [r2, #AT91_DDRSDRC_MDR] 357 biceq r3, r3, #AT91_DDRSDRC_MD 358 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 359 streq r3, [r2, #AT91_DDRSDRC_MDR] 360 361 /* Active DDRC self-refresh mode */ 362 ldr r3, [r2, #AT91_DDRSDRC_LPR] 363 str r3, .saved_sam9_lpr 364 bic r3, r3, #AT91_DDRSDRC_LPCB 365 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 366 str r3, [r2, #AT91_DDRSDRC_LPR] 367 368 /* If using the 2nd ddr controller */ 369 ldr r2, .sramc1_base 370 cmp r2, #0 371 beq sr_ena_no_2nd_ddrc 372 373 ldr r3, [r2, #AT91_DDRSDRC_MDR] 374 str r3, .saved_sam9_mdr1 375 bic r3, r3, #~AT91_DDRSDRC_MD 376 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR 377 ldreq r3, [r2, #AT91_DDRSDRC_MDR] 378 biceq r3, r3, #AT91_DDRSDRC_MD 379 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 380 streq r3, [r2, #AT91_DDRSDRC_MDR] 381 382 /* Active DDRC self-refresh mode */ 383 ldr r3, [r2, #AT91_DDRSDRC_LPR] 384 str r3, .saved_sam9_lpr1 385 bic r3, r3, #AT91_DDRSDRC_LPCB 386 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 387 str r3, [r2, #AT91_DDRSDRC_LPR] 388 389sr_ena_no_2nd_ddrc: 390 b sr_ena_exit 391 392 /* 393 * SDRAMC Memory controller 394 */ 395sr_ena_sdramc_sf: 396 /* Active SDRAMC self-refresh mode */ 397 ldr r3, [r2, #AT91_SDRAMC_LPR] 398 str r3, .saved_sam9_lpr 399 bic r3, r3, #AT91_SDRAMC_LPCB 400 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 401 str r3, [r2, #AT91_SDRAMC_LPR] 402 403 ldr r3, .saved_sam9_lpr 404 str r3, [r2, #AT91_SDRAMC_LPR] 405 406sr_ena_exit: 407.endm 408 409/** 410 * Disable self-refresh 411 * 412 * register usage: 413 * @r1: memory type 414 * @r2: base address of the sram controller 415 * @r3: temporary 416 */ 417.macro at91_sramc_self_refresh_dis 418 ldr r1, .memtype 419 ldr r2, .sramc_base 420 421 cmp r1, #AT91_MEMCTRL_MC 422 bne sr_dis_ddrc_exit_sf 423 424 /* 425 * at91rm9200 Memory controller 426 */ 427 428 /* 429 * For exiting the self-refresh mode, do nothing, 430 * automatically exit the self-refresh mode. 431 */ 432 b sr_dis_exit 433 434sr_dis_ddrc_exit_sf: 435 cmp r1, #AT91_MEMCTRL_DDRSDR 436 bne sdramc_exit_sf 437 438 /* DDR Memory controller */ 439 440 /* Restore MDR in case of LPDDR1 */ 441 ldr r3, .saved_sam9_mdr 442 str r3, [r2, #AT91_DDRSDRC_MDR] 443 /* Restore LPR on AT91 with DDRAM */ 444 ldr r3, .saved_sam9_lpr 445 str r3, [r2, #AT91_DDRSDRC_LPR] 446 447 /* If using the 2nd ddr controller */ 448 ldr r2, .sramc1_base 449 cmp r2, #0 450 ldrne r3, .saved_sam9_mdr1 451 strne r3, [r2, #AT91_DDRSDRC_MDR] 452 ldrne r3, .saved_sam9_lpr1 453 strne r3, [r2, #AT91_DDRSDRC_LPR] 454 455 b sr_dis_exit 456 457sdramc_exit_sf: 458 /* SDRAMC Memory controller */ 459 ldr r3, .saved_sam9_lpr 460 str r3, [r2, #AT91_SDRAMC_LPR] 461 462sr_dis_exit: 463.endm 464#endif 465 466.macro at91_pm_ulp0_mode 467 ldr pmc, .pmc_base 468 ldr tmp2, .pm_mode 469 ldr tmp3, .mckr_offset 470 471 /* Check if ULP0 fast variant has been requested. */ 472 cmp tmp2, #AT91_PM_ULP0_FAST 473 bne 0f 474 475 /* Set highest prescaler for power saving */ 476 ldr tmp1, [pmc, tmp3] 477 bic tmp1, tmp1, #AT91_PMC_PRES 478 orr tmp1, tmp1, #AT91_PMC_PRES_64 479 str tmp1, [pmc, tmp3] 480 481 mov tmp3, #0 482 wait_mckrdy tmp3 483 b 1f 484 4850: 486 /* Turn off the crystal oscillator */ 487 ldr tmp1, [pmc, #AT91_CKGR_MOR] 488 bic tmp1, tmp1, #AT91_PMC_MOSCEN 489 orr tmp1, tmp1, #AT91_PMC_KEY 490 str tmp1, [pmc, #AT91_CKGR_MOR] 491 492 /* Save RC oscillator state */ 493 ldr tmp1, [pmc, #AT91_PMC_SR] 494 str tmp1, .saved_osc_status 495 tst tmp1, #AT91_PMC_MOSCRCS 496 bne 1f 497 498 /* Turn off RC oscillator */ 499 ldr tmp1, [pmc, #AT91_CKGR_MOR] 500 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 501 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 502 orr tmp1, tmp1, #AT91_PMC_KEY 503 str tmp1, [pmc, #AT91_CKGR_MOR] 504 505 /* Wait main RC disabled done */ 5062: ldr tmp1, [pmc, #AT91_PMC_SR] 507 tst tmp1, #AT91_PMC_MOSCRCS 508 bne 2b 509 510 /* Wait for interrupt */ 5111: at91_cpu_idle 512 513 /* Check if ULP0 fast variant has been requested. */ 514 cmp tmp2, #AT91_PM_ULP0_FAST 515 bne 5f 516 517 /* Set lowest prescaler for fast resume. */ 518 ldr tmp3, .mckr_offset 519 ldr tmp1, [pmc, tmp3] 520 bic tmp1, tmp1, #AT91_PMC_PRES 521 str tmp1, [pmc, tmp3] 522 523 mov tmp3, #0 524 wait_mckrdy tmp3 525 b 6f 526 5275: /* Restore RC oscillator state */ 528 ldr tmp1, .saved_osc_status 529 tst tmp1, #AT91_PMC_MOSCRCS 530 beq 4f 531 532 /* Turn on RC oscillator */ 533 ldr tmp1, [pmc, #AT91_CKGR_MOR] 534 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 535 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 536 orr tmp1, tmp1, #AT91_PMC_KEY 537 str tmp1, [pmc, #AT91_CKGR_MOR] 538 539 /* Wait main RC stabilization */ 5403: ldr tmp1, [pmc, #AT91_PMC_SR] 541 tst tmp1, #AT91_PMC_MOSCRCS 542 beq 3b 543 544 /* Turn on the crystal oscillator */ 5454: ldr tmp1, [pmc, #AT91_CKGR_MOR] 546 orr tmp1, tmp1, #AT91_PMC_MOSCEN 547 orr tmp1, tmp1, #AT91_PMC_KEY 548 str tmp1, [pmc, #AT91_CKGR_MOR] 549 550 wait_moscrdy 5516: 552.endm 553 554/** 555 * Note: This procedure only applies on the platform which uses 556 * the external crystal oscillator as a main clock source. 557 */ 558.macro at91_pm_ulp1_mode 559 ldr pmc, .pmc_base 560 ldr tmp2, .mckr_offset 561 mov tmp3, #0 562 563 /* Save RC oscillator state and check if it is enabled. */ 564 ldr tmp1, [pmc, #AT91_PMC_SR] 565 str tmp1, .saved_osc_status 566 tst tmp1, #AT91_PMC_MOSCRCS 567 bne 2f 568 569 /* Enable RC oscillator */ 570 ldr tmp1, [pmc, #AT91_CKGR_MOR] 571 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 572 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 573 orr tmp1, tmp1, #AT91_PMC_KEY 574 str tmp1, [pmc, #AT91_CKGR_MOR] 575 576 /* Wait main RC stabilization */ 5771: ldr tmp1, [pmc, #AT91_PMC_SR] 578 tst tmp1, #AT91_PMC_MOSCRCS 579 beq 1b 580 581 /* Switch the main clock source to 12-MHz RC oscillator */ 5822: ldr tmp1, [pmc, #AT91_CKGR_MOR] 583 bic tmp1, tmp1, #AT91_PMC_MOSCSEL 584 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 585 orr tmp1, tmp1, #AT91_PMC_KEY 586 str tmp1, [pmc, #AT91_CKGR_MOR] 587 588 wait_moscsels 589 590 /* Disable the crystal oscillator */ 591 ldr tmp1, [pmc, #AT91_CKGR_MOR] 592 bic tmp1, tmp1, #AT91_PMC_MOSCEN 593 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 594 orr tmp1, tmp1, #AT91_PMC_KEY 595 str tmp1, [pmc, #AT91_CKGR_MOR] 596 597 /* Switch the master clock source to main clock */ 598 ldr tmp1, [pmc, tmp2] 599 bic tmp1, tmp1, #AT91_PMC_CSS 600 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 601 str tmp1, [pmc, tmp2] 602 603 wait_mckrdy tmp3 604 605 /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ 606 ldr tmp1, [pmc, #AT91_CKGR_MOR] 607 orr tmp1, tmp1, #AT91_PMC_WAITMODE 608 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 609 orr tmp1, tmp1, #AT91_PMC_KEY 610 str tmp1, [pmc, #AT91_CKGR_MOR] 611 612 /* Quirk for SAM9X60's PMC */ 613 nop 614 nop 615 616 wait_mckrdy tmp3 617 618 /* Enable the crystal oscillator */ 619 ldr tmp1, [pmc, #AT91_CKGR_MOR] 620 orr tmp1, tmp1, #AT91_PMC_MOSCEN 621 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 622 orr tmp1, tmp1, #AT91_PMC_KEY 623 str tmp1, [pmc, #AT91_CKGR_MOR] 624 625 wait_moscrdy 626 627 /* Switch the master clock source to slow clock */ 628 ldr tmp1, [pmc, tmp2] 629 bic tmp1, tmp1, #AT91_PMC_CSS 630 str tmp1, [pmc, tmp2] 631 632 wait_mckrdy tmp3 633 634 /* Switch main clock source to crystal oscillator */ 635 ldr tmp1, [pmc, #AT91_CKGR_MOR] 636 orr tmp1, tmp1, #AT91_PMC_MOSCSEL 637 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 638 orr tmp1, tmp1, #AT91_PMC_KEY 639 str tmp1, [pmc, #AT91_CKGR_MOR] 640 641 wait_moscsels 642 643 /* Switch the master clock source to main clock */ 644 ldr tmp1, [pmc, tmp2] 645 bic tmp1, tmp1, #AT91_PMC_CSS 646 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 647 str tmp1, [pmc, tmp2] 648 649 wait_mckrdy tmp3 650 651 /* Restore RC oscillator state */ 652 ldr tmp1, .saved_osc_status 653 tst tmp1, #AT91_PMC_MOSCRCS 654 bne 3f 655 656 /* Disable RC oscillator */ 657 ldr tmp1, [pmc, #AT91_CKGR_MOR] 658 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 659 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 660 orr tmp1, tmp1, #AT91_PMC_KEY 661 str tmp1, [pmc, #AT91_CKGR_MOR] 662 663 /* Wait RC oscillator disable done */ 6644: ldr tmp1, [pmc, #AT91_PMC_SR] 665 tst tmp1, #AT91_PMC_MOSCRCS 666 bne 4b 667 6683: 669.endm 670 671.macro at91_plla_disable 672 /* Save PLLA setting and disable it */ 673 ldr tmp1, .pmc_version 674 cmp tmp1, #AT91_PMC_V1 675 beq 1f 676 677#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL 678 /* Save PLLA settings. */ 679 ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] 680 bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID 681 str tmp2, [pmc, #AT91_PMC_PLL_UPDT] 682 683 /* save div. */ 684 mov tmp1, #0 685 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] 686 bic tmp2, tmp2, #0xffffff00 687 orr tmp1, tmp1, tmp2 688 689 /* save mul. */ 690 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1] 691 bic tmp2, tmp2, #0xffffff 692 orr tmp1, tmp1, tmp2 693 str tmp1, .saved_pllar 694 695 /* step 2. */ 696 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 697 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 698 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 699 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 700 701 /* step 3. */ 702 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 703 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 704 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 705 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 706 707 /* step 4. */ 708 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 709 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 710 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 711 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 712 713 /* step 5. */ 714 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 715 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 716 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 717 718 /* step 7. */ 719 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 720 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 721 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 722 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 723 724 b 2f 725#endif 726 7271: /* Save PLLA setting and disable it */ 728 ldr tmp1, [pmc, #AT91_CKGR_PLLAR] 729 str tmp1, .saved_pllar 730 731 /* Disable PLLA. */ 732 mov tmp1, #AT91_PMC_PLLCOUNT 733 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ 734 str tmp1, [pmc, #AT91_CKGR_PLLAR] 7352: 736.endm 737 738.macro at91_plla_enable 739 ldr tmp2, .saved_pllar 740 ldr tmp3, .pmc_version 741 cmp tmp3, #AT91_PMC_V1 742 beq 4f 743 744#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL 745 /* step 1. */ 746 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 747 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 748 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 749 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 750 751 /* step 2. */ 752 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA 753 str tmp1, [pmc, #AT91_PMC_PLL_ACR] 754 755 /* step 3. */ 756 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 757 mov tmp3, tmp2 758 bic tmp3, tmp3, #0xffffff 759 orr tmp1, tmp1, tmp3 760 str tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 761 762 /* step 8. */ 763 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 764 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 765 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 766 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 767 768 /* step 9. */ 769 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 770 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK 771 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 772 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 773 bic tmp1, tmp1, #0xff 774 mov tmp3, tmp2 775 bic tmp3, tmp3, #0xffffff00 776 orr tmp1, tmp1, tmp3 777 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 778 779 /* step 10. */ 780 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 781 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 782 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 783 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 784 785 /* step 11. */ 7863: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0] 787 tst tmp1, #0x1 788 beq 3b 789 b 2f 790#endif 791 792 /* Restore PLLA setting */ 7934: str tmp2, [pmc, #AT91_CKGR_PLLAR] 794 795 /* Enable PLLA. */ 796 tst tmp2, #(AT91_PMC_MUL & 0xff0000) 797 bne 1f 798 tst tmp2, #(AT91_PMC_MUL & ~0xff0000) 799 beq 2f 800 8011: ldr tmp1, [pmc, #AT91_PMC_SR] 802 tst tmp1, #AT91_PMC_LOCKA 803 beq 1b 8042: 805.endm 806 807/** 808 * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock 809 * 810 * Side effects: overwrites tmp1, tmp2 811 */ 812.macro at91_mckx_ps_enable 813#ifdef CONFIG_SOC_SAMA7 814 ldr pmc, .pmc_base 815 816 /* There are 4 MCKs we need to handle: MCK1..4 */ 817 mov tmp1, #1 818e_loop: cmp tmp1, #5 819 beq e_done 820 821 /* Write MCK ID to retrieve the settings. */ 822 str tmp1, [pmc, #AT91_PMC_MCR_V2] 823 ldr tmp2, [pmc, #AT91_PMC_MCR_V2] 824 825e_save_mck1: 826 cmp tmp1, #1 827 bne e_save_mck2 828 str tmp2, .saved_mck1 829 b e_ps 830 831e_save_mck2: 832 cmp tmp1, #2 833 bne e_save_mck3 834 str tmp2, .saved_mck2 835 b e_ps 836 837e_save_mck3: 838 cmp tmp1, #3 839 bne e_save_mck4 840 str tmp2, .saved_mck3 841 b e_ps 842 843e_save_mck4: 844 str tmp2, .saved_mck4 845 846e_ps: 847 /* Use CSS=MAINCK and DIV=1. */ 848 bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS 849 bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV 850 orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK 851 orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1 852 str tmp2, [pmc, #AT91_PMC_MCR_V2] 853 854 wait_mckrdy tmp1 855 856 add tmp1, tmp1, #1 857 b e_loop 858 859e_done: 860#endif 861.endm 862 863/** 864 * at91_mckx_ps_restore: restore MCK1..4 settings 865 * 866 * Side effects: overwrites tmp1, tmp2 867 */ 868.macro at91_mckx_ps_restore 869#ifdef CONFIG_SOC_SAMA7 870 ldr pmc, .pmc_base 871 872 /* There are 4 MCKs we need to handle: MCK1..4 */ 873 mov tmp1, #1 874r_loop: cmp tmp1, #5 875 beq r_done 876 877r_save_mck1: 878 cmp tmp1, #1 879 bne r_save_mck2 880 ldr tmp2, .saved_mck1 881 b r_ps 882 883r_save_mck2: 884 cmp tmp1, #2 885 bne r_save_mck3 886 ldr tmp2, .saved_mck2 887 b r_ps 888 889r_save_mck3: 890 cmp tmp1, #3 891 bne r_save_mck4 892 ldr tmp2, .saved_mck3 893 b r_ps 894 895r_save_mck4: 896 ldr tmp2, .saved_mck4 897 898r_ps: 899 /* Write MCK ID to retrieve the settings. */ 900 str tmp1, [pmc, #AT91_PMC_MCR_V2] 901 ldr tmp3, [pmc, #AT91_PMC_MCR_V2] 902 903 /* We need to restore CSS and DIV. */ 904 bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS 905 bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV 906 orr tmp3, tmp3, tmp2 907 bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK 908 orr tmp3, tmp3, tmp1 909 orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD 910 str tmp2, [pmc, #AT91_PMC_MCR_V2] 911 912 wait_mckrdy tmp1 913 914 add tmp1, tmp1, #1 915 b r_loop 916r_done: 917#endif 918.endm 919 920.macro at91_ulp_mode 921 at91_mckx_ps_enable 922 923 ldr pmc, .pmc_base 924 ldr tmp2, .mckr_offset 925 ldr tmp3, .pm_mode 926 927 /* Save Master clock setting */ 928 ldr tmp1, [pmc, tmp2] 929 str tmp1, .saved_mckr 930 931 /* 932 * Set master clock source to: 933 * - MAINCK if using ULP0 fast variant 934 * - slow clock, otherwise 935 */ 936 bic tmp1, tmp1, #AT91_PMC_CSS 937 cmp tmp3, #AT91_PM_ULP0_FAST 938 bne save_mck 939 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 940save_mck: 941 str tmp1, [pmc, tmp2] 942 943 mov tmp3, #0 944 wait_mckrdy tmp3 945 946 at91_plla_disable 947 948 /* Enable low power mode for 2.5V regulator. */ 949 at91_2_5V_reg_set_low_power 1 950 951 ldr tmp3, .pm_mode 952 cmp tmp3, #AT91_PM_ULP1 953 beq ulp1_mode 954 955 at91_pm_ulp0_mode 956 b ulp_exit 957 958ulp1_mode: 959 at91_pm_ulp1_mode 960 b ulp_exit 961 962ulp_exit: 963 /* Disable low power mode for 2.5V regulator. */ 964 at91_2_5V_reg_set_low_power 0 965 966 ldr pmc, .pmc_base 967 968 at91_plla_enable 969 970 /* 971 * Restore master clock setting 972 */ 973 ldr tmp1, .mckr_offset 974 ldr tmp2, .saved_mckr 975 str tmp2, [pmc, tmp1] 976 977 mov tmp3, #0 978 wait_mckrdy tmp3 979 980 at91_mckx_ps_restore 981.endm 982 983.macro at91_backup_mode 984 /* Switch the master clock source to slow clock. */ 985 ldr pmc, .pmc_base 986 ldr tmp2, .mckr_offset 987 ldr tmp1, [pmc, tmp2] 988 bic tmp1, tmp1, #AT91_PMC_CSS 989 str tmp1, [pmc, tmp2] 990 991 mov tmp3, #0 992 wait_mckrdy tmp3 993 994 /*BUMEN*/ 995 ldr r0, .sfrbu 996 mov tmp1, #0x1 997 str tmp1, [r0, #0x10] 998 999 /* Wait for it. */ 10001: ldr tmp1, [r0, #0x10] 1001 tst tmp1, #0x1 1002 beq 1b 1003 1004 /* Shutdown */ 1005 ldr r0, .shdwc 1006 mov tmp1, #0xA5000000 1007 add tmp1, tmp1, #0x1 1008 at91_backup_set_lpm tmp1 1009 str tmp1, [r0, #0] 1010.endm 1011 1012/* 1013 * void at91_suspend_sram_fn(struct at91_pm_data*) 1014 * @input param: 1015 * @r0: base address of struct at91_pm_data 1016 */ 1017/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ 1018 .align 3 1019ENTRY(at91_pm_suspend_in_sram) 1020 /* Save registers on stack */ 1021 stmfd sp!, {r4 - r12, lr} 1022 1023 /* Drain write buffer */ 1024 mov tmp1, #0 1025 mcr p15, 0, tmp1, c7, c10, 4 1026 1027 /* Flush tlb. */ 1028 mov r4, #0 1029 mcr p15, 0, r4, c8, c7, 0 1030 1031 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] 1032 str tmp1, .mckr_offset 1033 ldr tmp1, [r0, #PM_DATA_PMC_VERSION] 1034 str tmp1, .pmc_version 1035 ldr tmp1, [r0, #PM_DATA_MEMCTRL] 1036 str tmp1, .memtype 1037 ldr tmp1, [r0, #PM_DATA_MODE] 1038 str tmp1, .pm_mode 1039 1040 /* 1041 * ldrne below are here to preload their address in the TLB as access 1042 * to RAM may be limited while in self-refresh. 1043 */ 1044 ldr tmp1, [r0, #PM_DATA_PMC] 1045 str tmp1, .pmc_base 1046 cmp tmp1, #0 1047 ldrne tmp2, [tmp1, #0] 1048 1049 ldr tmp1, [r0, #PM_DATA_RAMC0] 1050 str tmp1, .sramc_base 1051 cmp tmp1, #0 1052 ldrne tmp2, [tmp1, #0] 1053 1054 ldr tmp1, [r0, #PM_DATA_RAMC1] 1055 str tmp1, .sramc1_base 1056 cmp tmp1, #0 1057 ldrne tmp2, [tmp1, #0] 1058 1059#ifndef CONFIG_SOC_SAM_V4_V5 1060 /* ldrne below are here to preload their address in the TLB */ 1061 ldr tmp1, [r0, #PM_DATA_RAMC_PHY] 1062 str tmp1, .sramc_phy_base 1063 cmp tmp1, #0 1064 ldrne tmp2, [tmp1, #0] 1065 1066 ldr tmp1, [r0, #PM_DATA_SHDWC] 1067 str tmp1, .shdwc 1068 cmp tmp1, #0 1069 ldrne tmp2, [tmp1, #0] 1070 1071 ldr tmp1, [r0, #PM_DATA_SFRBU] 1072 str tmp1, .sfrbu 1073 cmp tmp1, #0 1074 ldrne tmp2, [tmp1, #0x10] 1075#endif 1076 1077 /* Active the self-refresh mode */ 1078 at91_sramc_self_refresh_ena 1079 1080 ldr r0, .pm_mode 1081 cmp r0, #AT91_PM_STANDBY 1082 beq standby 1083 cmp r0, #AT91_PM_BACKUP 1084 beq backup_mode 1085 1086 at91_ulp_mode 1087 b exit_suspend 1088 1089standby: 1090 /* Wait for interrupt */ 1091 ldr pmc, .pmc_base 1092 at91_cpu_idle 1093 b exit_suspend 1094 1095backup_mode: 1096 at91_backup_mode 1097 1098exit_suspend: 1099 /* Exit the self-refresh mode */ 1100 at91_sramc_self_refresh_dis 1101 1102 /* Restore registers, and return */ 1103 ldmfd sp!, {r4 - r12, pc} 1104ENDPROC(at91_pm_suspend_in_sram) 1105 1106.pmc_base: 1107 .word 0 1108.sramc_base: 1109 .word 0 1110.sramc1_base: 1111 .word 0 1112.sramc_phy_base: 1113 .word 0 1114.shdwc: 1115 .word 0 1116.sfrbu: 1117 .word 0 1118.memtype: 1119 .word 0 1120.pm_mode: 1121 .word 0 1122.mckr_offset: 1123 .word 0 1124.pmc_version: 1125 .word 0 1126.saved_mckr: 1127 .word 0 1128.saved_pllar: 1129 .word 0 1130.saved_sam9_lpr: 1131 .word 0 1132.saved_sam9_lpr1: 1133 .word 0 1134.saved_sam9_mdr: 1135 .word 0 1136.saved_sam9_mdr1: 1137 .word 0 1138.saved_osc_status: 1139 .word 0 1140#ifdef CONFIG_SOC_SAMA7 1141.saved_mck1: 1142 .word 0 1143.saved_mck2: 1144 .word 0 1145.saved_mck3: 1146 .word 0 1147.saved_mck4: 1148 .word 0 1149#endif 1150 1151ENTRY(at91_pm_suspend_in_sram_sz) 1152 .word .-at91_pm_suspend_in_sram 1153