xref: /linux/arch/arm64/boot/dts/mediatek/mt8183-evb.dts (revision c4101e55974cc7d835fbd2d8e01553a3f61e9e75) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8/dts-v1/;
9#include "mt8183.dtsi"
10#include "mt6358.dtsi"
11
12/ {
13	model = "MediaTek MT8183 evaluation board";
14	chassis-type = "embedded";
15	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
16
17	aliases {
18		serial0 = &uart0;
19	};
20
21	memory@40000000 {
22		device_type = "memory";
23		reg = <0 0x40000000 0 0x80000000>;
24	};
25
26	chosen {
27		stdout-path = "serial0:921600n8";
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34		scp_mem_reserved: memory@50000000 {
35			compatible = "shared-dma-pool";
36			reg = <0 0x50000000 0 0x2900000>;
37			no-map;
38		};
39	};
40
41	thermal-sensor {
42		compatible = "murata,ncp03wf104";
43		pullup-uv = <1800000>;
44		pullup-ohm = <390000>;
45		pulldown-ohm = <0>;
46		io-channels = <&auxadc 0>;
47	};
48};
49
50&auxadc {
51	status = "okay";
52};
53
54&gpu {
55	mali-supply = <&mt6358_vgpu_reg>;
56};
57
58&i2c0 {
59	pinctrl-names = "default";
60	pinctrl-0 = <&i2c_pins_0>;
61	status = "okay";
62	clock-frequency = <100000>;
63};
64
65&i2c1 {
66	pinctrl-names = "default";
67	pinctrl-0 = <&i2c_pins_1>;
68	status = "okay";
69	clock-frequency = <100000>;
70};
71
72&i2c2 {
73	pinctrl-names = "default";
74	pinctrl-0 = <&i2c_pins_2>;
75	status = "okay";
76	clock-frequency = <100000>;
77};
78
79&i2c3 {
80	pinctrl-names = "default";
81	pinctrl-0 = <&i2c_pins_3>;
82	status = "okay";
83	clock-frequency = <100000>;
84};
85
86&i2c4 {
87	pinctrl-names = "default";
88	pinctrl-0 = <&i2c_pins_4>;
89	status = "okay";
90	clock-frequency = <1000000>;
91};
92
93&i2c5 {
94	pinctrl-names = "default";
95	pinctrl-0 = <&i2c_pins_5>;
96	status = "okay";
97	clock-frequency = <1000000>;
98};
99
100&mmc0 {
101	status = "okay";
102	pinctrl-names = "default", "state_uhs";
103	pinctrl-0 = <&mmc0_pins_default>;
104	pinctrl-1 = <&mmc0_pins_uhs>;
105	bus-width = <8>;
106	max-frequency = <200000000>;
107	cap-mmc-highspeed;
108	mmc-hs200-1_8v;
109	mmc-hs400-1_8v;
110	cap-mmc-hw-reset;
111	no-sdio;
112	no-sd;
113	hs400-ds-delay = <0x12814>;
114	vmmc-supply = <&mt6358_vemc_reg>;
115	vqmmc-supply = <&mt6358_vio18_reg>;
116	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
117	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
118	non-removable;
119};
120
121&mmc1 {
122	status = "okay";
123	pinctrl-names = "default", "state_uhs";
124	pinctrl-0 = <&mmc1_pins_default>;
125	pinctrl-1 = <&mmc1_pins_uhs>;
126	bus-width = <4>;
127	max-frequency = <200000000>;
128	cap-sd-highspeed;
129	sd-uhs-sdr50;
130	sd-uhs-sdr104;
131	cap-sdio-irq;
132	no-mmc;
133	no-sd;
134	vmmc-supply = <&mt6358_vmch_reg>;
135	vqmmc-supply = <&mt6358_vmc_reg>;
136	keep-power-in-suspend;
137	wakeup-source;
138	non-removable;
139};
140
141&mt6358_vgpu_reg {
142	regulator-min-microvolt = <625000>;
143	regulator-max-microvolt = <900000>;
144
145	regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
146	regulator-coupled-max-spread = <100000>;
147};
148
149&mt6358_vsram_gpu_reg {
150	regulator-min-microvolt = <850000>;
151	regulator-max-microvolt = <1000000>;
152
153	regulator-coupled-with = <&mt6358_vgpu_reg>;
154	regulator-coupled-max-spread = <100000>;
155};
156
157&pio {
158	i2c_pins_0: i2c0 {
159		pins_i2c {
160			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
161				 <PINMUX_GPIO83__FUNC_SCL0>;
162			mediatek,pull-up-adv = <3>;
163			mediatek,drive-strength-adv = <00>;
164		};
165	};
166
167	i2c_pins_1: i2c1 {
168		pins_i2c {
169			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
170				 <PINMUX_GPIO84__FUNC_SCL1>;
171			mediatek,pull-up-adv = <3>;
172			mediatek,drive-strength-adv = <00>;
173		};
174	};
175
176	i2c_pins_2: i2c2 {
177		pins_i2c {
178			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
179				 <PINMUX_GPIO104__FUNC_SDA2>;
180			mediatek,pull-up-adv = <3>;
181			mediatek,drive-strength-adv = <00>;
182		};
183	};
184
185	i2c_pins_3: i2c3 {
186		pins_i2c {
187			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
188				 <PINMUX_GPIO51__FUNC_SDA3>;
189			mediatek,pull-up-adv = <3>;
190			mediatek,drive-strength-adv = <00>;
191		};
192	};
193
194	i2c_pins_4: i2c4 {
195		pins_i2c {
196			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
197				 <PINMUX_GPIO106__FUNC_SDA4>;
198			mediatek,pull-up-adv = <3>;
199			mediatek,drive-strength-adv = <00>;
200		};
201	};
202
203	i2c_pins_5: i2c5 {
204		pins_i2c {
205			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
206				 <PINMUX_GPIO49__FUNC_SDA5>;
207			mediatek,pull-up-adv = <3>;
208			mediatek,drive-strength-adv = <00>;
209		};
210	};
211
212	spi_pins_0: spi0 {
213		pins_spi {
214			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
215				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
216				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
217				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
218			bias-disable;
219		};
220	};
221
222	mmc0_pins_default: mmc0default {
223		pins_cmd_dat {
224			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
225				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
226				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
227				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
228				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
229				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
230				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
231				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
232				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
233			input-enable;
234			bias-pull-up;
235		};
236
237		pins_clk {
238			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
239			bias-pull-down;
240		};
241
242		pins_rst {
243			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
244			bias-pull-up;
245		};
246	};
247
248	mmc0_pins_uhs: mmc0 {
249		pins_cmd_dat {
250			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
251				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
252				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
253				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
254				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
255				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
256				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
257				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
258				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
259			input-enable;
260			drive-strength = <MTK_DRIVE_10mA>;
261			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
262		};
263
264		pins_clk {
265			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
266			drive-strength = <MTK_DRIVE_10mA>;
267			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
268		};
269
270		pins_ds {
271			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
272			drive-strength = <MTK_DRIVE_10mA>;
273			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
274		};
275
276		pins_rst {
277			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
278			drive-strength = <MTK_DRIVE_10mA>;
279			bias-pull-up;
280		};
281	};
282
283	mmc1_pins_default: mmc1default {
284		pins_cmd_dat {
285			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
286				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
287				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
288				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
289				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
290			input-enable;
291			bias-pull-up;
292		};
293
294		pins_clk {
295			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
296			input-enable;
297			bias-pull-down;
298		};
299
300		pins_pmu {
301			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
302				   <PINMUX_GPIO166__FUNC_GPIO166>;
303			output-high;
304		};
305	};
306
307	mmc1_pins_uhs: mmc1 {
308		pins_cmd_dat {
309			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
310				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
311				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
312				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
313				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
314			drive-strength = <MTK_DRIVE_6mA>;
315			input-enable;
316			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
317		};
318
319		pins_clk {
320			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
321			drive-strength = <MTK_DRIVE_6mA>;
322			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
323			input-enable;
324		};
325	};
326
327	spi_pins_1: spi1 {
328		pins_spi {
329			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
330				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
331				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
332				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
333			bias-disable;
334		};
335	};
336
337	spi_pins_2: spi2 {
338		pins_spi {
339			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
340				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
341				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
342				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
343			bias-disable;
344		};
345	};
346
347	spi_pins_3: spi3 {
348		pins_spi {
349			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
350				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
351				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
352				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
353			bias-disable;
354		};
355	};
356
357	spi_pins_4: spi4 {
358		pins_spi {
359			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
360				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
361				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
362				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
363			bias-disable;
364		};
365	};
366
367	spi_pins_5: spi5 {
368		pins_spi {
369			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
370				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
371				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
372				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
373			bias-disable;
374		};
375	};
376
377	pwm_pins_1: pwm1 {
378		pins_pwm {
379			pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
380		};
381	};
382};
383
384&pmic {
385	interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
386};
387
388&mfg {
389	domain-supply = <&mt6358_vgpu_reg>;
390};
391
392&spi0 {
393	pinctrl-names = "default";
394	pinctrl-0 = <&spi_pins_0>;
395	mediatek,pad-select = <0>;
396	status = "okay";
397};
398
399&spi1 {
400	pinctrl-names = "default";
401	pinctrl-0 = <&spi_pins_1>;
402	mediatek,pad-select = <0>;
403	status = "okay";
404};
405
406&spi2 {
407	pinctrl-names = "default";
408	pinctrl-0 = <&spi_pins_2>;
409	mediatek,pad-select = <0>;
410	status = "okay";
411};
412
413&spi3 {
414	pinctrl-names = "default";
415	pinctrl-0 = <&spi_pins_3>;
416	mediatek,pad-select = <0>;
417	status = "okay";
418};
419
420&spi4 {
421	pinctrl-names = "default";
422	pinctrl-0 = <&spi_pins_4>;
423	mediatek,pad-select = <0>;
424	status = "okay";
425};
426
427&spi5 {
428	pinctrl-names = "default";
429	pinctrl-0 = <&spi_pins_5>;
430	mediatek,pad-select = <0>;
431	status = "okay";
432
433};
434
435&cci {
436	proc-supply = <&mt6358_vproc12_reg>;
437};
438
439&cpu0 {
440	proc-supply = <&mt6358_vproc12_reg>;
441};
442
443&cpu1 {
444	proc-supply = <&mt6358_vproc12_reg>;
445};
446
447&cpu2 {
448	proc-supply = <&mt6358_vproc12_reg>;
449};
450
451&cpu3 {
452	proc-supply = <&mt6358_vproc12_reg>;
453};
454
455&cpu4 {
456	proc-supply = <&mt6358_vproc11_reg>;
457};
458
459&cpu5 {
460	proc-supply = <&mt6358_vproc11_reg>;
461};
462
463&cpu6 {
464	proc-supply = <&mt6358_vproc11_reg>;
465};
466
467&cpu7 {
468	proc-supply = <&mt6358_vproc11_reg>;
469};
470
471&uart0 {
472	status = "okay";
473};
474
475&pwm1 {
476	status = "okay";
477	pinctrl-0 = <&pwm_pins_1>;
478	pinctrl-names = "default";
479};
480