1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2022 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Meteorlake. 10 */ 11 12 #include <linux/firmware.h> 13 #include <sound/sof/ipc4/header.h> 14 #include <trace/events/sof_intel.h> 15 #include "../ipc4-priv.h" 16 #include "../ops.h" 17 #include "hda.h" 18 #include "hda-ipc.h" 19 #include "../sof-audio.h" 20 #include "mtl.h" 21 22 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = { 23 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 24 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 26 }; 27 28 static void mtl_ipc_host_done(struct snd_sof_dev *sdev) 29 { 30 /* 31 * clear busy interrupt to tell dsp controller this interrupt has been accepted, 32 * not trigger it again 33 */ 34 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR, 35 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY); 36 /* 37 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp 38 */ 39 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA, 40 MTL_DSP_REG_HFIPCXTDA_BUSY, 0); 41 } 42 43 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev) 44 { 45 /* 46 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it, 47 * don't send more reply to host 48 */ 49 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA, 50 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE); 51 52 /* unmask Done interrupt */ 53 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 54 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE); 55 } 56 57 /* Check if an IPC IRQ occurred */ 58 static bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev) 59 { 60 u32 irq_status; 61 u32 hfintipptr; 62 63 /* read Interrupt IP Pointer */ 64 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 65 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 66 67 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status); 68 69 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC)) 70 return true; 71 72 return false; 73 } 74 75 /* Check if an SDW IRQ occurred */ 76 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 77 { 78 u32 irq_status; 79 u32 hfintipptr; 80 81 /* read Interrupt IP Pointer */ 82 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 83 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 84 85 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW)) 86 return true; 87 88 return false; 89 } 90 91 static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 92 { 93 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 94 struct sof_ipc4_msg *msg_data = msg->msg_data; 95 96 if (hda_ipc4_tx_is_busy(sdev)) { 97 hdev->delayed_ipc_tx_msg = msg; 98 return 0; 99 } 100 101 hdev->delayed_ipc_tx_msg = NULL; 102 103 /* send the message via mailbox */ 104 if (msg_data->data_size) 105 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, 106 msg_data->data_size); 107 108 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY, 109 msg_data->extension); 110 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR, 111 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY); 112 113 return 0; 114 } 115 116 static void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev) 117 { 118 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 119 const struct sof_intel_dsp_desc *chip = hda->desc; 120 121 /* enable IPC DONE and BUSY interrupts */ 122 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 123 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 124 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE); 125 } 126 127 static void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev) 128 { 129 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 130 const struct sof_intel_dsp_desc *chip = hda->desc; 131 132 /* disable IPC DONE and BUSY interrupts */ 133 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 134 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0); 135 } 136 137 static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 138 { 139 u32 hipcie; 140 u32 mask; 141 u32 val; 142 int ret; 143 144 /* Enable/Disable SoundWire interrupt */ 145 mask = MTL_DSP_REG_HfSNDWIE_IE_MASK; 146 if (enable) 147 val = mask; 148 else 149 val = 0; 150 151 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val); 152 153 /* check if operation was successful */ 154 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 155 (hipcie & mask) == val, 156 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 157 if (ret < 0) 158 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n", 159 enable ? "enable" : "disable"); 160 } 161 162 static int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable) 163 { 164 u32 hfintipptr; 165 u32 irqinten; 166 u32 hipcie; 167 u32 mask; 168 u32 val; 169 int ret; 170 171 /* read Interrupt IP Pointer */ 172 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 173 174 /* Enable/Disable Host IPC and SOUNDWIRE */ 175 mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 176 if (enable) 177 val = mask; 178 else 179 val = 0; 180 181 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val); 182 183 /* check if operation was successful */ 184 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 185 (irqinten & mask) == val, 186 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 187 if (ret < 0) { 188 dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n", 189 enable ? "enable" : "disable"); 190 return ret; 191 } 192 193 /* Enable/Disable Host IPC interrupt*/ 194 mask = MTL_DSP_REG_HfHIPCIE_IE_MASK; 195 if (enable) 196 val = mask; 197 else 198 val = 0; 199 200 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val); 201 202 /* check if operation was successful */ 203 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 204 (hipcie & mask) == val, 205 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 206 if (ret < 0) { 207 dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n", 208 enable ? "enable" : "disable"); 209 return ret; 210 } 211 212 return ret; 213 } 214 215 /* pre fw run operations */ 216 static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) 217 { 218 u32 dsphfpwrsts; 219 u32 dsphfdsscs; 220 u32 cpa; 221 u32 pgs; 222 int ret; 223 224 /* Set the DSP subsystem power on */ 225 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 226 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK); 227 228 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 229 usleep_range(1000, 1010); 230 231 /* poll with timeout to check if operation successful */ 232 cpa = MTL_HFDSSCS_CPA_MASK; 233 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 234 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 235 HDA_DSP_RESET_TIMEOUT_US); 236 if (ret < 0) { 237 dev_err(sdev->dev, "failed to enable DSP subsystem\n"); 238 return ret; 239 } 240 241 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */ 242 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 243 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); 244 245 usleep_range(1000, 1010); 246 247 /* poll with timeout to check if operation successful */ 248 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK; 249 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts, 250 (dsphfpwrsts & pgs) == pgs, 251 HDA_DSP_REG_POLL_INTERVAL_US, 252 HDA_DSP_RESET_TIMEOUT_US); 253 if (ret < 0) 254 dev_err(sdev->dev, "failed to power up gated DSP domain\n"); 255 256 /* make sure SoundWire is not power-gated */ 257 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL, 258 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); 259 return ret; 260 } 261 262 static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) 263 { 264 int ret; 265 266 if (sdev->first_boot) { 267 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 268 269 ret = hda_sdw_startup(sdev); 270 if (ret < 0) { 271 dev_err(sdev->dev, "could not startup SoundWire links\n"); 272 return ret; 273 } 274 275 /* Check if IMR boot is usable */ 276 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) 277 hdev->imrboot_supported = true; 278 } 279 280 hda_sdw_int_enable(sdev, true); 281 return 0; 282 } 283 284 static void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 285 { 286 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 287 u32 romdbgsts; 288 u32 romdbgerr; 289 u32 fwsts; 290 u32 fwlec; 291 292 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS); 293 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); 294 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY); 295 romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR); 296 297 dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec); 298 dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts, 299 romdbgerr); 300 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3); 301 dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n", 302 romdbgsts & BIT(24) ? "" : " not"); 303 } 304 305 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev) 306 { 307 int val; 308 309 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE); 310 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) 311 return true; 312 313 return false; 314 } 315 316 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core) 317 { 318 unsigned int cpa; 319 u32 dspcxctl; 320 int ret; 321 322 /* Only the primary core can be powered up by the host */ 323 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev)) 324 return 0; 325 326 /* Program the owner of the IP & shim registers (10: Host CPU) */ 327 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 328 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL, 329 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT); 330 331 /* enable SPA bit */ 332 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 333 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 334 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK); 335 336 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 337 usleep_range(1000, 1010); 338 339 /* poll with timeout to check if operation successful */ 340 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK; 341 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 342 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 343 HDA_DSP_RESET_TIMEOUT_US); 344 if (ret < 0) 345 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n", 346 __func__); 347 348 return ret; 349 } 350 351 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core) 352 { 353 u32 dspcxctl; 354 int ret; 355 356 /* Only the primary core can be powered down by the host */ 357 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev)) 358 return 0; 359 360 /* disable SPA bit */ 361 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 362 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); 363 364 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ 365 usleep_range(1000, 1010); 366 367 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 368 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK), 369 HDA_DSP_REG_POLL_INTERVAL_US, 370 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 371 if (ret < 0) 372 dev_err(sdev->dev, "failed to power down primary core\n"); 373 374 return ret; 375 } 376 377 static int mtl_power_down_dsp(struct snd_sof_dev *sdev) 378 { 379 u32 dsphfdsscs, cpa; 380 int ret; 381 382 /* first power down core */ 383 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 384 if (ret) { 385 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret); 386 return ret; 387 } 388 389 /* Set the DSP subsystem power down */ 390 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 391 MTL_HFDSSCS_SPA_MASK, 0); 392 393 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ 394 usleep_range(1000, 1010); 395 396 /* poll with timeout to check if operation successful */ 397 cpa = MTL_HFDSSCS_CPA_MASK; 398 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 399 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 400 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US, 401 HDA_DSP_RESET_TIMEOUT_US); 402 } 403 404 static int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) 405 { 406 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 407 const struct sof_intel_dsp_desc *chip = hda->desc; 408 unsigned int status; 409 u32 ipc_hdr; 410 int ret; 411 412 /* step 1: purge FW request */ 413 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL; 414 if (!imr_boot) 415 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); 416 417 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); 418 419 /* step 2: power up primary core */ 420 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 421 if (ret < 0) { 422 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 423 dev_err(sdev->dev, "dsp core 0/1 power up failed\n"); 424 goto err; 425 } 426 427 dev_dbg(sdev->dev, "Primary core power up successful\n"); 428 429 /* step 3: wait for IPC DONE bit from ROM */ 430 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status, 431 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask), 432 HDA_DSP_REG_POLL_INTERVAL_US, MTL_DSP_PURGE_TIMEOUT_US); 433 if (ret < 0) { 434 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 435 dev_err(sdev->dev, "timeout waiting for purge IPC done\n"); 436 goto err; 437 } 438 439 /* set DONE bit to clear the reply IPC message */ 440 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask, 441 chip->ipc_ack_mask); 442 443 /* step 4: enable interrupts */ 444 ret = mtl_enable_interrupts(sdev, true); 445 if (ret < 0) { 446 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 447 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__); 448 goto err; 449 } 450 451 mtl_enable_ipc_interrupts(sdev); 452 453 /* 454 * ACE workaround: don't wait for ROM INIT. 455 * The platform cannot catch ROM_INIT_DONE because of a very short 456 * timing window. Follow the recommendations and skip this part. 457 */ 458 459 return 0; 460 461 err: 462 snd_sof_dsp_dbg_dump(sdev, "MTL DSP init fail", 0); 463 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 464 return ret; 465 } 466 467 static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) 468 { 469 struct sof_ipc4_msg notification_data = {{ 0 }}; 470 struct snd_sof_dev *sdev = context; 471 bool ack_received = false; 472 bool ipc_irq = false; 473 u32 hipcida; 474 u32 hipctdr; 475 476 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 477 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 478 479 /* reply message from DSP */ 480 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) { 481 /* DSP received the message */ 482 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 483 MTL_DSP_REG_HFIPCXCTL_DONE, 0); 484 485 mtl_ipc_dsp_done(sdev); 486 487 ipc_irq = true; 488 ack_received = true; 489 } 490 491 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) { 492 /* Message from DSP (reply or notification) */ 493 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 494 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK; 495 496 /* 497 * ACE fw sends a new fw ipc message to host to 498 * notify the status of the last host ipc message 499 */ 500 if (primary & SOF_IPC4_MSG_DIR_MASK) { 501 /* Reply received */ 502 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { 503 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; 504 505 data->primary = primary; 506 data->extension = extension; 507 508 spin_lock_irq(&sdev->ipc_lock); 509 510 snd_sof_ipc_get_reply(sdev); 511 mtl_ipc_host_done(sdev); 512 snd_sof_ipc_reply(sdev, data->primary); 513 514 spin_unlock_irq(&sdev->ipc_lock); 515 } else { 516 dev_dbg_ratelimited(sdev->dev, 517 "IPC reply before FW_READY: %#x|%#x\n", 518 primary, extension); 519 } 520 } else { 521 /* Notification received */ 522 notification_data.primary = primary; 523 notification_data.extension = extension; 524 525 sdev->ipc->msg.rx_data = ¬ification_data; 526 snd_sof_ipc_msgs_rx(sdev); 527 sdev->ipc->msg.rx_data = NULL; 528 529 mtl_ipc_host_done(sdev); 530 } 531 532 ipc_irq = true; 533 } 534 535 if (!ipc_irq) { 536 /* This interrupt is not shared so no need to return IRQ_NONE. */ 537 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); 538 } 539 540 if (ack_received) { 541 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 542 543 if (hdev->delayed_ipc_tx_msg) 544 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg); 545 } 546 547 return IRQ_HANDLED; 548 } 549 550 static int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 551 { 552 return MTL_DSP_MBOX_UPLINK_OFFSET; 553 } 554 555 static int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 556 { 557 return MTL_SRAM_WINDOW_OFFSET(id); 558 } 559 560 static void mtl_ipc_dump(struct snd_sof_dev *sdev) 561 { 562 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl; 563 564 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR); 565 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY); 566 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 567 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 568 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 569 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA); 570 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL); 571 572 dev_err(sdev->dev, 573 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n", 574 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl); 575 } 576 577 static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 578 { 579 mtl_enable_sdw_irq(sdev, false); 580 mtl_disable_ipc_interrupts(sdev); 581 return mtl_enable_interrupts(sdev, false); 582 } 583 584 /* Meteorlake ops */ 585 struct snd_sof_dsp_ops sof_mtl_ops; 586 EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 587 588 int sof_mtl_ops_init(struct snd_sof_dev *sdev) 589 { 590 struct sof_ipc4_fw_data *ipc4_data; 591 592 /* common defaults */ 593 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 594 595 /* shutdown */ 596 sof_mtl_ops.shutdown = hda_dsp_shutdown; 597 598 /* doorbell */ 599 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread; 600 601 /* ipc */ 602 sof_mtl_ops.send_msg = mtl_ipc_send_msg; 603 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 604 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 605 606 /* debug */ 607 sof_mtl_ops.debug_map = mtl_dsp_debugfs; 608 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs); 609 sof_mtl_ops.dbg_dump = mtl_dsp_dump; 610 sof_mtl_ops.ipc_dump = mtl_ipc_dump; 611 612 /* pre/post fw run */ 613 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 614 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run; 615 616 /* parse platform specific extended manifest */ 617 sof_mtl_ops.parse_platform_ext_manifest = NULL; 618 619 /* dsp core get/put */ 620 /* TODO: add core_get and core_put */ 621 622 sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 623 if (!sdev->private) 624 return -ENOMEM; 625 626 ipc4_data = sdev->private; 627 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 628 629 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 630 631 /* External library loading support */ 632 ipc4_data->load_library = hda_dsp_ipc4_load_library; 633 634 /* set DAI ops */ 635 hda_set_dai_drv_ops(sdev, &sof_mtl_ops); 636 637 return 0; 638 }; 639 EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 640 641 const struct sof_intel_dsp_desc mtl_chip_info = { 642 .cores_num = 3, 643 .init_core_mask = BIT(0), 644 .host_managed_cores_mask = BIT(0), 645 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 646 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 647 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 648 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 649 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 650 .rom_status_reg = MTL_DSP_ROM_STS, 651 .rom_init_timeout = 300, 652 .ssp_count = MTL_SSP_COUNT, 653 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 654 .sdw_shim_base = SDW_SHIM_BASE_ACE, 655 .sdw_alh_base = SDW_ALH_BASE_ACE, 656 .d0i3_offset = MTL_HDA_VS_D0I3C, 657 .read_sdw_lcount = hda_sdw_check_lcount_common, 658 .enable_sdw_irq = mtl_enable_sdw_irq, 659 .check_sdw_irq = mtl_dsp_check_sdw_irq, 660 .check_ipc_irq = mtl_dsp_check_ipc_irq, 661 .cl_init = mtl_dsp_cl_init, 662 .power_down_dsp = mtl_power_down_dsp, 663 .disable_interrupts = mtl_dsp_disable_interrupts, 664 .hw_ip_version = SOF_INTEL_ACE_1_0, 665 }; 666 EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 667