| 38eff72f | 14-Nov-2025 |
Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> |
arm64: dts: socfpga: agilex5: update qspi partitions for 013b board
Update qspi flash partitions to support Remote System Update (RSU).
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara
arm64: dts: socfpga: agilex5: update qspi partitions for 013b board
Update qspi flash partitions to support Remote System Update (RSU).
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 44964e81 | 14-Nov-2025 |
Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> |
arm64: dts: socfpga: add Agilex3 board
Agilex3 SoCFPGA development kit is a small form factor board similar to
Agilex5 013b board. Agilex3 is derived from Agilex5 SoCFPGA, with the main
difference o
arm64: dts: socfpga: add Agilex3 board
Agilex3 SoCFPGA development kit is a small form factor board similar to
Agilex5 013b board. Agilex3 is derived from Agilex5 SoCFPGA, with the main
difference of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5.
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 5e7235d1 | 04-Nov-2025 |
Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> |
arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers
Add the "altr,agilex5-dw-i3c-master" compatible string to the
I3C controller nodes on the Agilex5 SoCFPGA platform.
Signed-off-
arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers
Add the "altr,agilex5-dw-i3c-master" compatible string to the
I3C controller nodes on the Agilex5 SoCFPGA platform.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 1aa4ee53 | 07-Nov-2025 |
Khairul Anuar Romli <khairul.anuar.romli@altera.com> |
arm64: dts: socfpga: Add Agilex5 SVC node with memory region
Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and r
arm64: dts: socfpga: Add Agilex5 SVC node with memory region
Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and references a
reserved memory region used for communication with the Secure Device
Manager (SDM).
Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations. This commit updates the device tree
structure to support Agilex5-specific handling of the SVC interface.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| aef9703d | 15-Oct-2025 |
Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> |
arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
Add SMMU-V3 Performance Monitoring Counter Group (PMCG) nodes for
Agilex5 to support SMMU performance event monitoring.
Signed-off-by: Adrian Ng
arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
Add SMMU-V3 Performance Monitoring Counter Group (PMCG) nodes for
Agilex5 to support SMMU performance event monitoring.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 3e99d51a | 15-Oct-2025 |
Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> |
arm64: dts: socfpga: agilex5: Add L2 and L3 cache
Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.
Signed-off-by: Adrian
arm64: dts: socfpga: agilex5: Add L2 and L3 cache
Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 2f6da95c | 04-Nov-2025 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: socfpga: agilex5: fix CHECK_DTBS warning for NAND
Add the required clock-names property NAND controller. This change corrects
the warning:
socfpga_agilex5_socdk_nand.dtb: nand-controlle
arm64: dts: socfpga: agilex5: fix CHECK_DTBS warning for NAND
Add the required clock-names property NAND controller. This change corrects
the warning:
socfpga_agilex5_socdk_nand.dtb: nand-controller@10b80000 (cdns,hp-nfc):
'clock-names' is a required property
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 95853aaa | 31-Oct-2025 |
Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> |
arm64: dts: socfpga: agilex5: add support for 013b board
Agilex5 SoCFPGA 013b is a small form factor development kit.
Supports both tabletop and PCIe add-in card operation. It features
expansion hea
arm64: dts: socfpga: agilex5: add support for 013b board
Agilex5 SoCFPGA 013b is a small form factor development kit.
Supports both tabletop and PCIe add-in card operation. It features
expansion headers for Raspberry Pi 4/5 HATs and Digilent Pmod modules,
enabling integration with popular ecosystems.
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| d07eddcd | 11-Mar-2025 |
Niravkumar L Rabara <niravkumar.l.rabara@intel.com> |
arm64: dts: socfpga: agilex5: add VGIC maintenance interrupt
Add VGIC maintenance interrupt and interrupt-parent property for
interrupt controller, required to run Linux in virtualized environment.
arm64: dts: socfpga: agilex5: add VGIC maintenance interrupt
Add VGIC maintenance interrupt and interrupt-parent property for
interrupt controller, required to run Linux in virtualized environment.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| d37c4716 | 21-Oct-2025 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: socfpga: agilex: fix dtbs_check warning for NAND
nand-controller@ffb90000 (altr,socfpga-denali-nand): Unevaluated
properties are not allowed ('flash@0' was unexpected)
Signed-off-by: Di
arm64: dts: socfpga: agilex: fix dtbs_check warning for NAND
nand-controller@ffb90000 (altr,socfpga-denali-nand): Unevaluated
properties are not allowed ('flash@0' was unexpected)
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 2fab0552 | 15-Oct-2025 |
Khairul Anuar Romli <khairul.anuar.romli@altera.com> |
arm64: dts: socfpga: agilex5: Add SMMU nodes
Agilex5 includes an ARM SMMU v3 (System Memory Management Unit) to provide
address translation and memory protection for DMA-capable devices such as
PCIe
arm64: dts: socfpga: agilex5: Add SMMU nodes
Agilex5 includes an ARM SMMU v3 (System Memory Management Unit) to provide
address translation and memory protection for DMA-capable devices such as
PCIe, USB, and other peripherals.
This commit adds the SMMU node to the Agilex5 device tree with compatible
string "arm,smmu-v3", along with its register space and interrupts.
The SMMU is required to:
- Enable DMA address translation for devices that cannot directly access
the full physical memory space.
- Provide isolation and memory protection by restricting device access
to specific regions of memory, improving system security.
- Support virtualization use cases by enabling safe and isolated device
passthrough to guest VMs.
- Align with ARM platform architecture requirements for IOMMU support.
By describing the SMMU in the device tree, the Linux IOMMU framework
can probe and initialize it during boot. Devices in the system can then
bind to the SMMU via the `iommus` property, enabling memory translation
and protection features as expected.
The following devices are updated to reference the SMMU:
- NAND controller
- DMA controller
- SPI controller
This change is a necessary step toward full enablement high-speed
peripherals on Agilex5.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| a025e1fb | 11-Sep-2025 |
Fong, Yan Kei <yan.kei.fong@altera.com> |
arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex5 device tree. This update configures the SPI controller to use a
arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex5 device tree. This update configures the SPI controller to use a
4-bit bus width for both transmission and reception, potentially improving
SPI throughput and matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| e928e15a | 11-Sep-2025 |
Fong, Yan Kei <yan.kei.fong@altera.com> |
arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex device tree. This update configures the SPI controller to use a
4
arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex device tree. This update configures the SPI controller to use a
4-bit bus width for both transmission and reception, potentially improving
SPI throughput and matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 9cb76813 | 18-Aug-2025 |
Matthew Gerlach <matthew.gerlach@altera.com> |
arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected
to a RGMII PHY on a daughter card. There are no RGMII cloc
arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected
to a RGMII PHY on a daughter card. There are no RGMII clock delays
implemented the on PCB.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| e417c5b1 | 06-Jan-2025 |
Niravkumar L Rabara <niravkumar.l.rabara@intel.com> |
arm64: dts: socfpga: agilex: Add dma channel id for spi
Add DMA channel ids for spi0 and spi1 nodes in device tree.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by:
arm64: dts: socfpga: agilex: Add dma channel id for spi
Add DMA channel ids for spi0 and spi1 nodes in device tree.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 17d321d4 | 18-Feb-2025 |
Niravkumar L Rabara <niravkumar.l.rabara@intel.com> |
arm64: dts: socfpga: agilex5: add led and memory nodes
Add LED and memory nodes, and enabled GPIO0 for Agilex5 devkit.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-
arm64: dts: socfpga: agilex5: add led and memory nodes
Add LED and memory nodes, and enabled GPIO0 for Agilex5 devkit.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 76f15cd9 | 26-Feb-2025 |
Matthew Gerlach <matthew.gerlach@altera.com> |
arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators
Add clock-frequency property to the internal oscillators, cb_intosc_ls_clk
and cb_intosc_hs_div2_clk.
Signed-off-by: Matth
arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators
Add clock-frequency property to the internal oscillators, cb_intosc_ls_clk
and cb_intosc_hs_div2_clk.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| a6c9896e | 13-Feb-2025 |
Niravkumar L Rabara <niravkumar.l.rabara@intel.com> |
arm64: dts: socfpga: agilex5: fix gpio0 address
Use the correct gpio0 address for Agilex5.
Fixes: 3f7c869e143a ("arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake id")
Cc: stable@v
arm64: dts: socfpga: agilex5: fix gpio0 address
Use the correct gpio0 address for Agilex5.
Fixes: 3f7c869e143a ("arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake id")
Cc: stable@vger.kernel.org
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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