1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef __SOC_TEGRA_FUSE_H__ 7 #define __SOC_TEGRA_FUSE_H__ 8 9 #include <linux/types.h> 10 11 #define TEGRA20 0x20 12 #define TEGRA30 0x30 13 #define TEGRA114 0x35 14 #define TEGRA124 0x40 15 #define TEGRA132 0x13 16 #define TEGRA210 0x21 17 #define TEGRA186 0x18 18 #define TEGRA194 0x19 19 #define TEGRA234 0x23 20 #define TEGRA241 0x24 21 #define TEGRA264 0x26 22 23 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 24 #define TEGRA30_FUSE_SATA_CALIB 0x124 25 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 26 27 #ifndef __ASSEMBLY__ 28 29 enum tegra_revision { 30 TEGRA_REVISION_UNKNOWN = 0, 31 TEGRA_REVISION_A01, 32 TEGRA_REVISION_A02, 33 TEGRA_REVISION_A03, 34 TEGRA_REVISION_A03p, 35 TEGRA_REVISION_A04, 36 TEGRA_REVISION_MAX, 37 }; 38 39 enum tegra_platform { 40 TEGRA_PLATFORM_SILICON = 0, 41 TEGRA_PLATFORM_QT, 42 TEGRA_PLATFORM_SYSTEM_FPGA, 43 TEGRA_PLATFORM_UNIT_FPGA, 44 TEGRA_PLATFORM_ASIM_QT, 45 TEGRA_PLATFORM_ASIM_LINSIM, 46 TEGRA_PLATFORM_DSIM_ASIM_LINSIM, 47 TEGRA_PLATFORM_VERIFICATION_SIMULATION, 48 TEGRA_PLATFORM_VDK, 49 TEGRA_PLATFORM_VSP, 50 TEGRA_PLATFORM_MAX, 51 }; 52 53 struct tegra_sku_info { 54 int sku_id; 55 int cpu_process_id; 56 int cpu_speedo_id; 57 int cpu_speedo_value; 58 int cpu_iddq_value; 59 int soc_process_id; 60 int soc_speedo_id; 61 int soc_speedo_value; 62 int gpu_process_id; 63 int gpu_speedo_id; 64 int gpu_speedo_value; 65 enum tegra_revision revision; 66 enum tegra_platform platform; 67 }; 68 69 #ifdef CONFIG_ARCH_TEGRA 70 extern struct tegra_sku_info tegra_sku_info; 71 u32 tegra_read_straps(void); 72 u32 tegra_read_ram_code(void); 73 int tegra_fuse_readl(unsigned long offset, u32 *value); 74 u32 tegra_read_chipid(void); 75 u8 tegra_get_chip_id(void); 76 u8 tegra_get_platform(void); 77 bool tegra_is_silicon(void); 78 int tegra194_miscreg_mask_serror(void); 79 #else 80 static struct tegra_sku_info tegra_sku_info __maybe_unused; 81 82 static inline u32 tegra_read_straps(void) 83 { 84 return 0; 85 } 86 87 static inline u32 tegra_read_ram_code(void) 88 { 89 return 0; 90 } 91 92 static inline int tegra_fuse_readl(unsigned long offset, u32 *value) 93 { 94 return -ENODEV; 95 } 96 97 static inline u32 tegra_read_chipid(void) 98 { 99 return 0; 100 } 101 102 static inline u8 tegra_get_chip_id(void) 103 { 104 return 0; 105 } 106 107 static inline u8 tegra_get_platform(void) 108 { 109 return 0; 110 } 111 112 static inline bool tegra_is_silicon(void) 113 { 114 return false; 115 } 116 117 static inline int tegra194_miscreg_mask_serror(void) 118 { 119 return false; 120 } 121 #endif 122 123 struct device *tegra_soc_device_register(void); 124 125 #endif /* __ASSEMBLY__ */ 126 127 #endif /* __SOC_TEGRA_FUSE_H__ */ 128