1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "smu_v13_0_10.h" 25 #include "amdgpu_reset.h" 26 #include "amdgpu_dpm.h" 27 #include "amdgpu_job.h" 28 #include "amdgpu_ring.h" 29 #include "amdgpu_ras.h" 30 #include "amdgpu_psp.h" 31 32 static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl) 33 { 34 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 35 if (adev->pm.fw_version >= 0x00502005 && !amdgpu_sriov_vf(adev)) 36 return true; 37 38 return false; 39 } 40 41 static struct amdgpu_reset_handler * 42 smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl, 43 struct amdgpu_reset_context *reset_context) 44 { 45 struct amdgpu_reset_handler *handler; 46 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 47 48 if (reset_context->method != AMD_RESET_METHOD_NONE) { 49 list_for_each_entry(handler, &reset_ctl->reset_handlers, 50 handler_list) { 51 if (handler->reset_method == reset_context->method) 52 return handler; 53 } 54 } 55 56 if (smu_v13_0_10_is_mode2_default(reset_ctl) && 57 amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE2) { 58 list_for_each_entry (handler, &reset_ctl->reset_handlers, 59 handler_list) { 60 if (handler->reset_method == AMD_RESET_METHOD_MODE2) 61 return handler; 62 } 63 } 64 65 return NULL; 66 } 67 68 static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev) 69 { 70 int r, i; 71 72 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 73 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 74 75 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 76 if (!(adev->ip_blocks[i].version->type == 77 AMD_IP_BLOCK_TYPE_GFX || 78 adev->ip_blocks[i].version->type == 79 AMD_IP_BLOCK_TYPE_SDMA || 80 adev->ip_blocks[i].version->type == 81 AMD_IP_BLOCK_TYPE_MES)) 82 continue; 83 84 r = adev->ip_blocks[i].version->funcs->suspend(adev); 85 86 if (r) { 87 dev_err(adev->dev, 88 "suspend of IP block <%s> failed %d\n", 89 adev->ip_blocks[i].version->funcs->name, r); 90 return r; 91 } 92 adev->ip_blocks[i].status.hw = false; 93 } 94 95 return r; 96 } 97 98 static int 99 smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, 100 struct amdgpu_reset_context *reset_context) 101 { 102 int r = 0; 103 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 104 105 if (!amdgpu_sriov_vf(adev)) 106 r = smu_v13_0_10_mode2_suspend_ip(adev); 107 108 return r; 109 } 110 111 static int smu_v13_0_10_mode2_reset(struct amdgpu_device *adev) 112 { 113 return amdgpu_dpm_mode2_reset(adev); 114 } 115 116 static void smu_v13_0_10_async_reset(struct work_struct *work) 117 { 118 struct amdgpu_reset_handler *handler; 119 struct amdgpu_reset_control *reset_ctl = 120 container_of(work, struct amdgpu_reset_control, reset_work); 121 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 122 123 list_for_each_entry(handler, &reset_ctl->reset_handlers, 124 handler_list) { 125 if (handler->reset_method == reset_ctl->active_reset) { 126 dev_dbg(adev->dev, "Resetting device\n"); 127 handler->do_reset(adev); 128 break; 129 } 130 } 131 } 132 static int 133 smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 134 struct amdgpu_reset_context *reset_context) 135 { 136 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 137 int r; 138 139 r = smu_v13_0_10_mode2_reset(adev); 140 if (r) { 141 dev_err(adev->dev, 142 "ASIC reset failed with error, %d ", r); 143 } 144 return r; 145 } 146 147 static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev) 148 { 149 int i, r; 150 struct psp_context *psp = &adev->psp; 151 struct amdgpu_firmware_info *ucode; 152 struct amdgpu_firmware_info *ucode_list[2]; 153 int ucode_count = 0; 154 155 for (i = 0; i < adev->firmware.max_ucodes; i++) { 156 ucode = &adev->firmware.ucode[i]; 157 158 switch (ucode->ucode_id) { 159 case AMDGPU_UCODE_ID_IMU_I: 160 case AMDGPU_UCODE_ID_IMU_D: 161 ucode_list[ucode_count++] = ucode; 162 break; 163 default: 164 break; 165 } 166 } 167 168 r = psp_load_fw_list(psp, ucode_list, ucode_count); 169 if (r) { 170 dev_err(adev->dev, "IMU ucode load failed after mode2 reset\n"); 171 return r; 172 } 173 174 r = psp_rlc_autoload_start(psp); 175 if (r) { 176 DRM_ERROR("Failed to start rlc autoload after mode2 reset\n"); 177 return r; 178 } 179 180 amdgpu_dpm_enable_gfx_features(adev); 181 182 for (i = 0; i < adev->num_ip_blocks; i++) { 183 if (!(adev->ip_blocks[i].version->type == 184 AMD_IP_BLOCK_TYPE_GFX || 185 adev->ip_blocks[i].version->type == 186 AMD_IP_BLOCK_TYPE_MES || 187 adev->ip_blocks[i].version->type == 188 AMD_IP_BLOCK_TYPE_SDMA)) 189 continue; 190 r = adev->ip_blocks[i].version->funcs->resume(adev); 191 if (r) { 192 dev_err(adev->dev, 193 "resume of IP block <%s> failed %d\n", 194 adev->ip_blocks[i].version->funcs->name, r); 195 return r; 196 } 197 198 adev->ip_blocks[i].status.hw = true; 199 } 200 201 for (i = 0; i < adev->num_ip_blocks; i++) { 202 if (!(adev->ip_blocks[i].version->type == 203 AMD_IP_BLOCK_TYPE_GFX || 204 adev->ip_blocks[i].version->type == 205 AMD_IP_BLOCK_TYPE_MES || 206 adev->ip_blocks[i].version->type == 207 AMD_IP_BLOCK_TYPE_SDMA)) 208 continue; 209 210 if (adev->ip_blocks[i].version->funcs->late_init) { 211 r = adev->ip_blocks[i].version->funcs->late_init( 212 (void *)adev); 213 if (r) { 214 dev_err(adev->dev, 215 "late_init of IP block <%s> failed %d after reset\n", 216 adev->ip_blocks[i].version->funcs->name, 217 r); 218 return r; 219 } 220 } 221 adev->ip_blocks[i].status.late_initialized = true; 222 } 223 224 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); 225 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); 226 227 return r; 228 } 229 230 static int 231 smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 232 struct amdgpu_reset_context *reset_context) 233 { 234 int r; 235 struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle; 236 237 dev_info(tmp_adev->dev, 238 "GPU reset succeeded, trying to resume\n"); 239 r = smu_v13_0_10_mode2_restore_ip(tmp_adev); 240 if (r) 241 goto end; 242 243 amdgpu_register_gpu_instance(tmp_adev); 244 245 /* Resume RAS */ 246 amdgpu_ras_resume(tmp_adev); 247 248 amdgpu_irq_gpu_reset_resume_helper(tmp_adev); 249 250 r = amdgpu_ib_ring_tests(tmp_adev); 251 if (r) { 252 dev_err(tmp_adev->dev, 253 "ib ring test failed (%d).\n", r); 254 r = -EAGAIN; 255 goto end; 256 } 257 258 end: 259 if (r) 260 return -EAGAIN; 261 else 262 return r; 263 } 264 265 static struct amdgpu_reset_handler smu_v13_0_10_mode2_handler = { 266 .reset_method = AMD_RESET_METHOD_MODE2, 267 .prepare_env = NULL, 268 .prepare_hwcontext = smu_v13_0_10_mode2_prepare_hwcontext, 269 .perform_reset = smu_v13_0_10_mode2_perform_reset, 270 .restore_hwcontext = smu_v13_0_10_mode2_restore_hwcontext, 271 .restore_env = NULL, 272 .do_reset = smu_v13_0_10_mode2_reset, 273 }; 274 275 int smu_v13_0_10_reset_init(struct amdgpu_device *adev) 276 { 277 struct amdgpu_reset_control *reset_ctl; 278 279 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL); 280 if (!reset_ctl) 281 return -ENOMEM; 282 283 reset_ctl->handle = adev; 284 reset_ctl->async_reset = smu_v13_0_10_async_reset; 285 reset_ctl->active_reset = AMD_RESET_METHOD_NONE; 286 reset_ctl->get_reset_handler = smu_v13_0_10_get_reset_handler; 287 288 INIT_LIST_HEAD(&reset_ctl->reset_handlers); 289 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset); 290 /* Only mode2 is handled through reset control now */ 291 amdgpu_reset_add_handler(reset_ctl, &smu_v13_0_10_mode2_handler); 292 293 adev->reset_cntl = reset_ctl; 294 295 return 0; 296 } 297 298 int smu_v13_0_10_reset_fini(struct amdgpu_device *adev) 299 { 300 kfree(adev->reset_cntl); 301 adev->reset_cntl = NULL; 302 return 0; 303 } 304