1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/kallsyms.h> 13 #include <linux/kprobes.h> 14 #include <linux/spinlock.h> 15 #include <linux/uaccess.h> 16 #include <linux/hardirq.h> 17 #include <linux/kdebug.h> 18 #include <linux/module.h> 19 #include <linux/kexec.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/sched/signal.h> 23 #include <linux/sched/debug.h> 24 #include <linux/sched/task_stack.h> 25 #include <linux/sizes.h> 26 #include <linux/syscalls.h> 27 #include <linux/mm_types.h> 28 #include <linux/kasan.h> 29 #include <linux/cfi.h> 30 31 #include <asm/atomic.h> 32 #include <asm/bug.h> 33 #include <asm/cpufeature.h> 34 #include <asm/daifflags.h> 35 #include <asm/debug-monitors.h> 36 #include <asm/esr.h> 37 #include <asm/exception.h> 38 #include <asm/extable.h> 39 #include <asm/insn.h> 40 #include <asm/kprobes.h> 41 #include <asm/patching.h> 42 #include <asm/traps.h> 43 #include <asm/smp.h> 44 #include <asm/stack_pointer.h> 45 #include <asm/stacktrace.h> 46 #include <asm/system_misc.h> 47 #include <asm/sysreg.h> 48 49 static bool __kprobes __check_eq(unsigned long pstate) 50 { 51 return (pstate & PSR_Z_BIT) != 0; 52 } 53 54 static bool __kprobes __check_ne(unsigned long pstate) 55 { 56 return (pstate & PSR_Z_BIT) == 0; 57 } 58 59 static bool __kprobes __check_cs(unsigned long pstate) 60 { 61 return (pstate & PSR_C_BIT) != 0; 62 } 63 64 static bool __kprobes __check_cc(unsigned long pstate) 65 { 66 return (pstate & PSR_C_BIT) == 0; 67 } 68 69 static bool __kprobes __check_mi(unsigned long pstate) 70 { 71 return (pstate & PSR_N_BIT) != 0; 72 } 73 74 static bool __kprobes __check_pl(unsigned long pstate) 75 { 76 return (pstate & PSR_N_BIT) == 0; 77 } 78 79 static bool __kprobes __check_vs(unsigned long pstate) 80 { 81 return (pstate & PSR_V_BIT) != 0; 82 } 83 84 static bool __kprobes __check_vc(unsigned long pstate) 85 { 86 return (pstate & PSR_V_BIT) == 0; 87 } 88 89 static bool __kprobes __check_hi(unsigned long pstate) 90 { 91 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 92 return (pstate & PSR_C_BIT) != 0; 93 } 94 95 static bool __kprobes __check_ls(unsigned long pstate) 96 { 97 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 98 return (pstate & PSR_C_BIT) == 0; 99 } 100 101 static bool __kprobes __check_ge(unsigned long pstate) 102 { 103 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 104 return (pstate & PSR_N_BIT) == 0; 105 } 106 107 static bool __kprobes __check_lt(unsigned long pstate) 108 { 109 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 110 return (pstate & PSR_N_BIT) != 0; 111 } 112 113 static bool __kprobes __check_gt(unsigned long pstate) 114 { 115 /*PSR_N_BIT ^= PSR_V_BIT */ 116 unsigned long temp = pstate ^ (pstate << 3); 117 118 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 119 return (temp & PSR_N_BIT) == 0; 120 } 121 122 static bool __kprobes __check_le(unsigned long pstate) 123 { 124 /*PSR_N_BIT ^= PSR_V_BIT */ 125 unsigned long temp = pstate ^ (pstate << 3); 126 127 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 128 return (temp & PSR_N_BIT) != 0; 129 } 130 131 static bool __kprobes __check_al(unsigned long pstate) 132 { 133 return true; 134 } 135 136 /* 137 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that 138 * it behaves identically to 0b1110 ("al"). 139 */ 140 pstate_check_t * const aarch32_opcode_cond_checks[16] = { 141 __check_eq, __check_ne, __check_cs, __check_cc, 142 __check_mi, __check_pl, __check_vs, __check_vc, 143 __check_hi, __check_ls, __check_ge, __check_lt, 144 __check_gt, __check_le, __check_al, __check_al 145 }; 146 147 int show_unhandled_signals = 0; 148 149 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 150 { 151 unsigned long addr = instruction_pointer(regs); 152 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 153 int i; 154 155 if (user_mode(regs)) 156 return; 157 158 for (i = -4; i < 1; i++) { 159 unsigned int val, bad; 160 161 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 162 163 if (!bad) 164 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 165 else { 166 p += sprintf(p, "bad PC value"); 167 break; 168 } 169 } 170 171 printk("%sCode: %s\n", lvl, str); 172 } 173 174 #ifdef CONFIG_PREEMPT 175 #define S_PREEMPT " PREEMPT" 176 #elif defined(CONFIG_PREEMPT_RT) 177 #define S_PREEMPT " PREEMPT_RT" 178 #else 179 #define S_PREEMPT "" 180 #endif 181 182 #define S_SMP " SMP" 183 184 static int __die(const char *str, long err, struct pt_regs *regs) 185 { 186 static int die_counter; 187 int ret; 188 189 pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n", 190 str, err, ++die_counter); 191 192 /* trap and error numbers are mostly meaningless on ARM */ 193 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 194 if (ret == NOTIFY_STOP) 195 return ret; 196 197 print_modules(); 198 show_regs(regs); 199 200 dump_kernel_instr(KERN_EMERG, regs); 201 202 return ret; 203 } 204 205 static DEFINE_RAW_SPINLOCK(die_lock); 206 207 /* 208 * This function is protected against re-entrancy. 209 */ 210 void die(const char *str, struct pt_regs *regs, long err) 211 { 212 int ret; 213 unsigned long flags; 214 215 raw_spin_lock_irqsave(&die_lock, flags); 216 217 oops_enter(); 218 219 console_verbose(); 220 bust_spinlocks(1); 221 ret = __die(str, err, regs); 222 223 if (regs && kexec_should_crash(current)) 224 crash_kexec(regs); 225 226 bust_spinlocks(0); 227 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 228 oops_exit(); 229 230 if (in_interrupt()) 231 panic("%s: Fatal exception in interrupt", str); 232 if (panic_on_oops) 233 panic("%s: Fatal exception", str); 234 235 raw_spin_unlock_irqrestore(&die_lock, flags); 236 237 if (ret != NOTIFY_STOP) 238 make_task_dead(SIGSEGV); 239 } 240 241 static void arm64_show_signal(int signo, const char *str) 242 { 243 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 244 DEFAULT_RATELIMIT_BURST); 245 struct task_struct *tsk = current; 246 unsigned long esr = tsk->thread.fault_code; 247 struct pt_regs *regs = task_pt_regs(tsk); 248 249 /* Leave if the signal won't be shown */ 250 if (!show_unhandled_signals || 251 !unhandled_signal(tsk, signo) || 252 !__ratelimit(&rs)) 253 return; 254 255 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 256 if (esr) 257 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr); 258 259 pr_cont("%s", str); 260 print_vma_addr(KERN_CONT " in ", regs->pc); 261 pr_cont("\n"); 262 __show_regs(regs); 263 } 264 265 void arm64_force_sig_fault(int signo, int code, unsigned long far, 266 const char *str) 267 { 268 arm64_show_signal(signo, str); 269 if (signo == SIGKILL) 270 force_sig(SIGKILL); 271 else 272 force_sig_fault(signo, code, (void __user *)far); 273 } 274 275 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, 276 const char *str) 277 { 278 arm64_show_signal(SIGBUS, str); 279 force_sig_mceerr(code, (void __user *)far, lsb); 280 } 281 282 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, 283 const char *str) 284 { 285 arm64_show_signal(SIGTRAP, str); 286 force_sig_ptrace_errno_trap(errno, (void __user *)far); 287 } 288 289 void arm64_notify_die(const char *str, struct pt_regs *regs, 290 int signo, int sicode, unsigned long far, 291 unsigned long err) 292 { 293 if (user_mode(regs)) { 294 WARN_ON(regs != current_pt_regs()); 295 current->thread.fault_address = 0; 296 current->thread.fault_code = err; 297 298 arm64_force_sig_fault(signo, sicode, far, str); 299 } else { 300 die(str, regs, err); 301 } 302 } 303 304 #ifdef CONFIG_COMPAT 305 #define PSTATE_IT_1_0_SHIFT 25 306 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 307 #define PSTATE_IT_7_2_SHIFT 10 308 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 309 310 static u32 compat_get_it_state(struct pt_regs *regs) 311 { 312 u32 it, pstate = regs->pstate; 313 314 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 315 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 316 317 return it; 318 } 319 320 static void compat_set_it_state(struct pt_regs *regs, u32 it) 321 { 322 u32 pstate_it; 323 324 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 325 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 326 327 regs->pstate &= ~PSR_AA32_IT_MASK; 328 regs->pstate |= pstate_it; 329 } 330 331 static void advance_itstate(struct pt_regs *regs) 332 { 333 u32 it; 334 335 /* ARM mode */ 336 if (!(regs->pstate & PSR_AA32_T_BIT) || 337 !(regs->pstate & PSR_AA32_IT_MASK)) 338 return; 339 340 it = compat_get_it_state(regs); 341 342 /* 343 * If this is the last instruction of the block, wipe the IT 344 * state. Otherwise advance it. 345 */ 346 if (!(it & 7)) 347 it = 0; 348 else 349 it = (it & 0xe0) | ((it << 1) & 0x1f); 350 351 compat_set_it_state(regs, it); 352 } 353 #else 354 static void advance_itstate(struct pt_regs *regs) 355 { 356 } 357 #endif 358 359 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 360 { 361 regs->pc += size; 362 363 /* 364 * If we were single stepping, we want to get the step exception after 365 * we return from the trap. 366 */ 367 if (user_mode(regs)) 368 user_fastforward_single_step(current); 369 370 if (compat_user_mode(regs)) 371 advance_itstate(regs); 372 else 373 regs->pstate &= ~PSR_BTYPE_MASK; 374 } 375 376 static int user_insn_read(struct pt_regs *regs, u32 *insnp) 377 { 378 u32 instr; 379 unsigned long pc = instruction_pointer(regs); 380 381 if (compat_thumb_mode(regs)) { 382 /* 16-bit Thumb instruction */ 383 __le16 instr_le; 384 if (get_user(instr_le, (__le16 __user *)pc)) 385 return -EFAULT; 386 instr = le16_to_cpu(instr_le); 387 if (aarch32_insn_is_wide(instr)) { 388 u32 instr2; 389 390 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 391 return -EFAULT; 392 instr2 = le16_to_cpu(instr_le); 393 instr = (instr << 16) | instr2; 394 } 395 } else { 396 /* 32-bit ARM instruction */ 397 __le32 instr_le; 398 if (get_user(instr_le, (__le32 __user *)pc)) 399 return -EFAULT; 400 instr = le32_to_cpu(instr_le); 401 } 402 403 *insnp = instr; 404 return 0; 405 } 406 407 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err) 408 { 409 const char *desc; 410 struct pt_regs *regs = current_pt_regs(); 411 412 if (WARN_ON(!user_mode(regs))) 413 return; 414 415 switch (signal) { 416 case SIGILL: 417 desc = "undefined instruction"; 418 break; 419 case SIGSEGV: 420 desc = "illegal memory access"; 421 break; 422 default: 423 desc = "unknown or unrecoverable error"; 424 break; 425 } 426 427 /* Force signals we don't understand to SIGKILL */ 428 if (WARN_ON(signal != SIGKILL && 429 siginfo_layout(signal, code) != SIL_FAULT)) { 430 signal = SIGKILL; 431 } 432 433 arm64_notify_die(desc, regs, signal, code, address, err); 434 } 435 436 /* 437 * Set up process info to signal segmentation fault - called on access error. 438 */ 439 void arm64_notify_segfault(unsigned long addr) 440 { 441 int code; 442 443 mmap_read_lock(current->mm); 444 if (find_vma(current->mm, untagged_addr(addr)) == NULL) 445 code = SEGV_MAPERR; 446 else 447 code = SEGV_ACCERR; 448 mmap_read_unlock(current->mm); 449 450 force_signal_inject(SIGSEGV, code, addr, 0); 451 } 452 453 void do_el0_undef(struct pt_regs *regs, unsigned long esr) 454 { 455 u32 insn; 456 457 /* check for AArch32 breakpoint instructions */ 458 if (!aarch32_break_handler(regs)) 459 return; 460 461 if (user_insn_read(regs, &insn)) 462 goto out_err; 463 464 if (try_emulate_mrs(regs, insn)) 465 return; 466 467 if (try_emulate_armv8_deprecated(regs, insn)) 468 return; 469 470 out_err: 471 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 472 } 473 474 void do_el1_undef(struct pt_regs *regs, unsigned long esr) 475 { 476 u32 insn; 477 478 if (aarch64_insn_read((void *)regs->pc, &insn)) 479 goto out_err; 480 481 if (try_emulate_el1_ssbs(regs, insn)) 482 return; 483 484 out_err: 485 die("Oops - Undefined instruction", regs, esr); 486 } 487 488 void do_el0_bti(struct pt_regs *regs) 489 { 490 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 491 } 492 493 void do_el1_bti(struct pt_regs *regs, unsigned long esr) 494 { 495 die("Oops - BTI", regs, esr); 496 } 497 498 void do_el0_fpac(struct pt_regs *regs, unsigned long esr) 499 { 500 force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr); 501 } 502 503 void do_el1_fpac(struct pt_regs *regs, unsigned long esr) 504 { 505 /* 506 * Unexpected FPAC exception in the kernel: kill the task before it 507 * does any more harm. 508 */ 509 die("Oops - FPAC", regs, esr); 510 } 511 512 #define __user_cache_maint(insn, address, res) \ 513 if (address >= TASK_SIZE_MAX) { \ 514 res = -EFAULT; \ 515 } else { \ 516 uaccess_ttbr0_enable(); \ 517 asm volatile ( \ 518 "1: " insn ", %1\n" \ 519 " mov %w0, #0\n" \ 520 "2:\n" \ 521 _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ 522 : "=r" (res) \ 523 : "r" (address)); \ 524 uaccess_ttbr0_disable(); \ 525 } 526 527 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs) 528 { 529 unsigned long tagged_address, address; 530 int rt = ESR_ELx_SYS64_ISS_RT(esr); 531 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 532 int ret = 0; 533 534 tagged_address = pt_regs_read_reg(regs, rt); 535 address = untagged_addr(tagged_address); 536 537 switch (crm) { 538 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 539 __user_cache_maint("dc civac", address, ret); 540 break; 541 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 542 __user_cache_maint("dc civac", address, ret); 543 break; 544 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 545 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 546 break; 547 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 548 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 549 break; 550 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 551 __user_cache_maint("dc civac", address, ret); 552 break; 553 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 554 __user_cache_maint("ic ivau", address, ret); 555 break; 556 default: 557 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 558 return; 559 } 560 561 if (ret) 562 arm64_notify_segfault(tagged_address); 563 else 564 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 565 } 566 567 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs) 568 { 569 int rt = ESR_ELx_SYS64_ISS_RT(esr); 570 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 571 572 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 573 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 574 val &= ~BIT(CTR_EL0_DIC_SHIFT); 575 576 /* ... and fake IminLine to reduce the number of traps. */ 577 val &= ~CTR_EL0_IminLine_MASK; 578 val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK; 579 } 580 581 pt_regs_write_reg(regs, rt, val); 582 583 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 584 } 585 586 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 587 { 588 int rt = ESR_ELx_SYS64_ISS_RT(esr); 589 590 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 591 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 592 } 593 594 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 595 { 596 int rt = ESR_ELx_SYS64_ISS_RT(esr); 597 598 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 599 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 600 } 601 602 static void mrs_handler(unsigned long esr, struct pt_regs *regs) 603 { 604 u32 sysreg, rt; 605 606 rt = ESR_ELx_SYS64_ISS_RT(esr); 607 sysreg = esr_sys64_to_sysreg(esr); 608 609 if (do_emulate_mrs(regs, sysreg, rt) != 0) 610 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 611 } 612 613 static void wfi_handler(unsigned long esr, struct pt_regs *regs) 614 { 615 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 616 } 617 618 struct sys64_hook { 619 unsigned long esr_mask; 620 unsigned long esr_val; 621 void (*handler)(unsigned long esr, struct pt_regs *regs); 622 }; 623 624 static const struct sys64_hook sys64_hooks[] = { 625 { 626 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 627 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 628 .handler = user_cache_maint_handler, 629 }, 630 { 631 /* Trap read access to CTR_EL0 */ 632 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 633 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 634 .handler = ctr_read_handler, 635 }, 636 { 637 /* Trap read access to CNTVCT_EL0 */ 638 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 639 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 640 .handler = cntvct_read_handler, 641 }, 642 { 643 /* Trap read access to CNTVCTSS_EL0 */ 644 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 645 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS, 646 .handler = cntvct_read_handler, 647 }, 648 { 649 /* Trap read access to CNTFRQ_EL0 */ 650 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 651 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 652 .handler = cntfrq_read_handler, 653 }, 654 { 655 /* Trap read access to CPUID registers */ 656 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 657 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 658 .handler = mrs_handler, 659 }, 660 { 661 /* Trap WFI instructions executed in userspace */ 662 .esr_mask = ESR_ELx_WFx_MASK, 663 .esr_val = ESR_ELx_WFx_WFI_VAL, 664 .handler = wfi_handler, 665 }, 666 {}, 667 }; 668 669 #ifdef CONFIG_COMPAT 670 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs) 671 { 672 int cond; 673 674 /* Only a T32 instruction can trap without CV being set */ 675 if (!(esr & ESR_ELx_CV)) { 676 u32 it; 677 678 it = compat_get_it_state(regs); 679 if (!it) 680 return true; 681 682 cond = it >> 4; 683 } else { 684 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 685 } 686 687 return aarch32_opcode_cond_checks[cond](regs->pstate); 688 } 689 690 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 691 { 692 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 693 694 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 695 arm64_skip_faulting_instruction(regs, 4); 696 } 697 698 static const struct sys64_hook cp15_32_hooks[] = { 699 { 700 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 701 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 702 .handler = compat_cntfrq_read_handler, 703 }, 704 {}, 705 }; 706 707 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 708 { 709 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 710 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 711 u64 val = arch_timer_read_counter(); 712 713 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 714 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 715 arm64_skip_faulting_instruction(regs, 4); 716 } 717 718 static const struct sys64_hook cp15_64_hooks[] = { 719 { 720 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 721 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 722 .handler = compat_cntvct_read_handler, 723 }, 724 { 725 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 726 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS, 727 .handler = compat_cntvct_read_handler, 728 }, 729 {}, 730 }; 731 732 void do_el0_cp15(unsigned long esr, struct pt_regs *regs) 733 { 734 const struct sys64_hook *hook, *hook_base; 735 736 if (!cp15_cond_valid(esr, regs)) { 737 /* 738 * There is no T16 variant of a CP access, so we 739 * always advance PC by 4 bytes. 740 */ 741 arm64_skip_faulting_instruction(regs, 4); 742 return; 743 } 744 745 switch (ESR_ELx_EC(esr)) { 746 case ESR_ELx_EC_CP15_32: 747 hook_base = cp15_32_hooks; 748 break; 749 case ESR_ELx_EC_CP15_64: 750 hook_base = cp15_64_hooks; 751 break; 752 default: 753 do_el0_undef(regs, esr); 754 return; 755 } 756 757 for (hook = hook_base; hook->handler; hook++) 758 if ((hook->esr_mask & esr) == hook->esr_val) { 759 hook->handler(esr, regs); 760 return; 761 } 762 763 /* 764 * New cp15 instructions may previously have been undefined at 765 * EL0. Fall back to our usual undefined instruction handler 766 * so that we handle these consistently. 767 */ 768 do_el0_undef(regs, esr); 769 } 770 #endif 771 772 void do_el0_sys(unsigned long esr, struct pt_regs *regs) 773 { 774 const struct sys64_hook *hook; 775 776 for (hook = sys64_hooks; hook->handler; hook++) 777 if ((hook->esr_mask & esr) == hook->esr_val) { 778 hook->handler(esr, regs); 779 return; 780 } 781 782 /* 783 * New SYS instructions may previously have been undefined at EL0. Fall 784 * back to our usual undefined instruction handler so that we handle 785 * these consistently. 786 */ 787 do_el0_undef(regs, esr); 788 } 789 790 static const char *esr_class_str[] = { 791 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 792 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 793 [ESR_ELx_EC_WFx] = "WFI/WFE", 794 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 795 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 796 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 797 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 798 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 799 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 800 [ESR_ELx_EC_PAC] = "PAC", 801 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 802 [ESR_ELx_EC_BTI] = "BTI", 803 [ESR_ELx_EC_ILL] = "PSTATE.IL", 804 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 805 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 806 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 807 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 808 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 809 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 810 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 811 [ESR_ELx_EC_SVE] = "SVE", 812 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 813 [ESR_ELx_EC_FPAC] = "FPAC", 814 [ESR_ELx_EC_SME] = "SME", 815 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 816 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 817 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 818 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 819 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 820 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 821 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 822 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 823 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 824 [ESR_ELx_EC_SERROR] = "SError", 825 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 826 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 827 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 828 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 829 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 830 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 831 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 832 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 833 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 834 }; 835 836 const char *esr_get_class_string(unsigned long esr) 837 { 838 return esr_class_str[ESR_ELx_EC(esr)]; 839 } 840 841 /* 842 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 843 * exceptions taken from EL0. 844 */ 845 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr) 846 { 847 unsigned long pc = instruction_pointer(regs); 848 849 current->thread.fault_address = 0; 850 current->thread.fault_code = esr; 851 852 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 853 "Bad EL0 synchronous exception"); 854 } 855 856 #ifdef CONFIG_VMAP_STACK 857 858 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 859 __aligned(16); 860 861 void panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far) 862 { 863 unsigned long tsk_stk = (unsigned long)current->stack; 864 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 865 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 866 867 console_verbose(); 868 pr_emerg("Insufficient stack space to handle exception!"); 869 870 pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr)); 871 pr_emerg("FAR: 0x%016lx\n", far); 872 873 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 874 tsk_stk, tsk_stk + THREAD_SIZE); 875 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 876 irq_stk, irq_stk + IRQ_STACK_SIZE); 877 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 878 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 879 880 __show_regs(regs); 881 882 /* 883 * We use nmi_panic to limit the potential for recusive overflows, and 884 * to get a better stack trace. 885 */ 886 nmi_panic(NULL, "kernel stack overflow"); 887 cpu_park_loop(); 888 } 889 #endif 890 891 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr) 892 { 893 console_verbose(); 894 895 pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n", 896 smp_processor_id(), esr, esr_get_class_string(esr)); 897 if (regs) 898 __show_regs(regs); 899 900 nmi_panic(regs, "Asynchronous SError Interrupt"); 901 902 cpu_park_loop(); 903 unreachable(); 904 } 905 906 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr) 907 { 908 unsigned long aet = arm64_ras_serror_get_severity(esr); 909 910 switch (aet) { 911 case ESR_ELx_AET_CE: /* corrected error */ 912 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 913 /* 914 * The CPU can make progress. We may take UEO again as 915 * a more severe error. 916 */ 917 return false; 918 919 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 920 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 921 /* 922 * The CPU can't make progress. The exception may have 923 * been imprecise. 924 * 925 * Neoverse-N1 #1349291 means a non-KVM SError reported as 926 * Unrecoverable should be treated as Uncontainable. We 927 * call arm64_serror_panic() in both cases. 928 */ 929 return true; 930 931 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 932 default: 933 /* Error has been silently propagated */ 934 arm64_serror_panic(regs, esr); 935 } 936 } 937 938 void do_serror(struct pt_regs *regs, unsigned long esr) 939 { 940 /* non-RAS errors are not containable */ 941 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 942 arm64_serror_panic(regs, esr); 943 } 944 945 /* GENERIC_BUG traps */ 946 947 int is_valid_bugaddr(unsigned long addr) 948 { 949 /* 950 * bug_handler() only called for BRK #BUG_BRK_IMM. 951 * So the answer is trivial -- any spurious instances with no 952 * bug table entry will be rejected by report_bug() and passed 953 * back to the debug-monitors code and handled as a fatal 954 * unexpected debug exception. 955 */ 956 return 1; 957 } 958 959 static int bug_handler(struct pt_regs *regs, unsigned long esr) 960 { 961 switch (report_bug(regs->pc, regs)) { 962 case BUG_TRAP_TYPE_BUG: 963 die("Oops - BUG", regs, esr); 964 break; 965 966 case BUG_TRAP_TYPE_WARN: 967 break; 968 969 default: 970 /* unknown/unrecognised bug trap type */ 971 return DBG_HOOK_ERROR; 972 } 973 974 /* If thread survives, skip over the BUG instruction and continue: */ 975 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 976 return DBG_HOOK_HANDLED; 977 } 978 979 static struct break_hook bug_break_hook = { 980 .fn = bug_handler, 981 .imm = BUG_BRK_IMM, 982 }; 983 984 #ifdef CONFIG_CFI_CLANG 985 static int cfi_handler(struct pt_regs *regs, unsigned long esr) 986 { 987 unsigned long target; 988 u32 type; 989 990 target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr)); 991 type = (u32)pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TYPE, esr)); 992 993 switch (report_cfi_failure(regs, regs->pc, &target, type)) { 994 case BUG_TRAP_TYPE_BUG: 995 die("Oops - CFI", regs, 0); 996 break; 997 998 case BUG_TRAP_TYPE_WARN: 999 break; 1000 1001 default: 1002 return DBG_HOOK_ERROR; 1003 } 1004 1005 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1006 return DBG_HOOK_HANDLED; 1007 } 1008 1009 static struct break_hook cfi_break_hook = { 1010 .fn = cfi_handler, 1011 .imm = CFI_BRK_IMM_BASE, 1012 .mask = CFI_BRK_IMM_MASK, 1013 }; 1014 #endif /* CONFIG_CFI_CLANG */ 1015 1016 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr) 1017 { 1018 pr_err("%s generated an invalid instruction at %pS!\n", 1019 "Kernel text patching", 1020 (void *)instruction_pointer(regs)); 1021 1022 /* We cannot handle this */ 1023 return DBG_HOOK_ERROR; 1024 } 1025 1026 static struct break_hook fault_break_hook = { 1027 .fn = reserved_fault_handler, 1028 .imm = FAULT_BRK_IMM, 1029 }; 1030 1031 #ifdef CONFIG_KASAN_SW_TAGS 1032 1033 #define KASAN_ESR_RECOVER 0x20 1034 #define KASAN_ESR_WRITE 0x10 1035 #define KASAN_ESR_SIZE_MASK 0x0f 1036 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 1037 1038 static int kasan_handler(struct pt_regs *regs, unsigned long esr) 1039 { 1040 bool recover = esr & KASAN_ESR_RECOVER; 1041 bool write = esr & KASAN_ESR_WRITE; 1042 size_t size = KASAN_ESR_SIZE(esr); 1043 u64 addr = regs->regs[0]; 1044 u64 pc = regs->pc; 1045 1046 kasan_report(addr, size, write, pc); 1047 1048 /* 1049 * The instrumentation allows to control whether we can proceed after 1050 * a crash was detected. This is done by passing the -recover flag to 1051 * the compiler. Disabling recovery allows to generate more compact 1052 * code. 1053 * 1054 * Unfortunately disabling recovery doesn't work for the kernel right 1055 * now. KASAN reporting is disabled in some contexts (for example when 1056 * the allocator accesses slab object metadata; this is controlled by 1057 * current->kasan_depth). All these accesses are detected by the tool, 1058 * even though the reports for them are not printed. 1059 * 1060 * This is something that might be fixed at some point in the future. 1061 */ 1062 if (!recover) 1063 die("Oops - KASAN", regs, esr); 1064 1065 /* If thread survives, skip over the brk instruction and continue: */ 1066 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1067 return DBG_HOOK_HANDLED; 1068 } 1069 1070 static struct break_hook kasan_break_hook = { 1071 .fn = kasan_handler, 1072 .imm = KASAN_BRK_IMM, 1073 .mask = KASAN_BRK_MASK, 1074 }; 1075 #endif 1076 1077 1078 #define esr_comment(esr) ((esr) & ESR_ELx_BRK64_ISS_COMMENT_MASK) 1079 1080 /* 1081 * Initial handler for AArch64 BRK exceptions 1082 * This handler only used until debug_traps_init(). 1083 */ 1084 int __init early_brk64(unsigned long addr, unsigned long esr, 1085 struct pt_regs *regs) 1086 { 1087 #ifdef CONFIG_CFI_CLANG 1088 if ((esr_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE) 1089 return cfi_handler(regs, esr) != DBG_HOOK_HANDLED; 1090 #endif 1091 #ifdef CONFIG_KASAN_SW_TAGS 1092 if ((esr_comment(esr) & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1093 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1094 #endif 1095 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1096 } 1097 1098 void __init trap_init(void) 1099 { 1100 register_kernel_break_hook(&bug_break_hook); 1101 #ifdef CONFIG_CFI_CLANG 1102 register_kernel_break_hook(&cfi_break_hook); 1103 #endif 1104 register_kernel_break_hook(&fault_break_hook); 1105 #ifdef CONFIG_KASAN_SW_TAGS 1106 register_kernel_break_hook(&kasan_break_hook); 1107 #endif 1108 debug_traps_init(); 1109 } 1110